We have to disable the ssi irq, as it is not safe for all platforms to
write back into the status register. It also runs into non-linefetch
aborts.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

imx-pcm-fiq is checking for TE RE bits, so enable them only if
necessary.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

The chip errata for the i.MX35, Rev.2 has the following errata:

ENGcm06222: SSI:Transmission does not take place in bit length early frame sync
	    configuration

The workaround states, that TX_EN and SSI_EN bits should be set in the same
register write. As the next errata in the document (ENGcm06532) says to always
write RX_EN and TX_EN in the same register write in network mode.

Therefore include the whole write to
	CCSR_SSI_SCR_TE and CCSR_SSI_SCR_RE
into the write to
	CCSR_SSI_SCR_SSIEN
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

This patch adds ac97-slave support.

For ac97, the registers have to be setup earlier than for other ssi
modes because there is some communication with the external device
before streaming. So this patch introduces a fsl_ssi_setup function to
setup the registers for different ssi operation modes seperately.

This patch was tested with imx27-pca100.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>