- 04 Oct, 2023 1 commit
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Jani Nikula authored
There's no need for this to be a macro. Add some documentation too. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/480b9b697b2ffa0c8677115bd443ba633801c6c1.1696336887.git.jani.nikula@intel.com
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- 03 Oct, 2023 2 commits
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Vinod Govindapillai authored
FBC is supported with RGB32 8:8:8:8 with or without alpha Bspec: 68904, 69560 Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by:
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Vinod Govindapillai authored
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding register writes (Matt) - Update the subject to reflect that fbc can be enabled only in the first three planes (Matt) v3: - use icl_is_hdr_plane(), use wrapper macro for plane binding register access, comments update and patch split (Ville) v4: - update to the plane binding register access macro Bspec: 69560 Signed-off-by:
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- 02 Oct, 2023 4 commits
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Rodrigo Vivi authored
Introduce the basic documentation about GSC CS. This "GPU Basics" section is focused on explaining the hardware rather than the driver/uapi, so let's make sure GSC is also properly documented here. v2: Fixes from Matt: typos and acronym. Fixes: 5fd974d1 ("drm/i915/mtl: add initial definitions for GSC CS") Suggested-by:
Matt Roper <matthew.d.roper@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Rodrigo Vivi authored
Let's introduce the basic documentation about CCS. While doing that, also removed the legacy execution flag name. That flag simply doesn't exist for CCS and it is not needed on current context submission. Those flag names are only needed on legacy context, while on new ones we only need to pass the engine ID. It is worth mention that this documentation should probably live with the engine definitions rather than in the i915.rst file directly and that more updates are likely need in this section. But this should come later. v2: Overall improvements from Matt and Tvrtko. Fixes: 944823c9 ("drm/i915/xehp: Define compute class and engine") Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Rodrigo Vivi authored
The goal is to have this function ready for Xe to use directly. So, let's use the available macro. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jouni Högander authored
Intel frontbuffer tracking code is using i915_active functions -> include i915_active.h directly instead of relying getting indirectly included. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
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- 29 Sep, 2023 21 commits
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Jani Nikula authored
Add stubs for !I915. Not all the functions need to be stubbed. Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/930c8d332d425a54dae7af16aed26ec293f80afd.1694514689.git.jani.nikula@intel.com
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
Add stubs for !I915. Signed-off-by:
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Jani Nikula authored
The xe driver will reuse i915 display code by compiling it separately as part of xe. We'll want to be able to distinguish between building the i915 display code for i915 and xe. Define I915 when building i915. Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Jani Nikula authored
Signed-off-by: -
Jouni Högander authored
i915_gem_object_set_frontbuffer returns set frontbuffer pointer. When we are releasing frontbuffer we are clearing the pointer from the object. Warn on if return value is not null. v3: Check i915_gem_object_set_frontbuffer return value separately v2: Instead of ignoring do drm_WARN_ON Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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- 28 Sep, 2023 11 commits
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Imre Deak authored
Recompute the state of all CRTCs on an FDI link during a modeset that may be affected by the modeset of other CRTCs on the same link. This ensures that each CRTC on the link maximizes its BW use (after another CRTC is disabled). In practice this means recomputing pipe B's config on IVB if pipe C gets disabled. v2: - Add the change recomputing affected CRTC states in a separate patch. (Ville) v3: (Ville) - Constify old and new crtc states. - Check for fused off pipe C. - Fix new vs. old crtc state mixup. - Drop check for pipe C's enabled state. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-12-imre.deak@intel.com
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Imre Deak authored
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI lanes. Make the BW sharing more dynamic by trying to reduce pipe B's link bpp in this case, until pipe B uses only up to 2 FDI lanes. For this instead of the encoder compute config retry loop - which reduced link bpp only for the encoder's pipe - reduce the maximum link bpp for pipe B/C as required after all CRTC states are computed and recompute the CRTC states with the new bpp limit. Atm, all FDI encoder's compute config function returns an error if a BW constrain prevents increasing the pipe bpp value. The corresponding crtc_state->bw_constrained check can be replaced with checking crtc_state->max_link_bpp_x16, add TODO comments for this. SDVO is an exception where this case is only handled in the outer config retry loop, failing the modeset with a WARN, add a FIXME comment to handle this in the encoder code similarly to other encoders. v2: - Don't assume that a CRTC is already in the atomic state, while reducing its link bpp. - Add DocBook description to intel_fdi_atomic_check_link(). v3: - Enable BW management for FDI links in a separate patch. (Ville) v4: (Ville) - Fail the SDVO encoder config computation if it doesn't support the link bpp limit. - Add TODO: comments about checking link_bpp_x16 instead of bw_constrained. v5: - Replace link bpp limit check with a FIXME: comment in intel_sdvo_compute_config(). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
At the moment a modeset fails if the config computation of a pipe can't fit its required BW to the available link BW even though the limitation may be resolved by reducing the BW requirement of other pipes. To improve the above this patch adds helper functions checking the overall BW limits after all CRTC states have been computed. If the check fails the maximum link bpp for a selected pipe will be reduced and all the CRTC states will be recomputed until either the overall BW limit check passes, or further bpp reduction is not possible (because all pipes/encoders sharing the link BW reached their minimum link bpp). Atm, the MST encoder allocates twice the required BW for YUV420 format streams. A follow-up patchset will fix that, add a code comment about this. This change prepares for upcoming patches enabling the above BW management on FDI and MST links. v2: - Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani) v3: - Add the helper functions in a separate patch. (Ville) - Add the functions to intel_link_bw.c instead of intel_atomic.c (Ville) - Return -ENOSPC instead of -EINVAL to userspace in case of a link BW limit failure. v4: - Make intel_atomic_check_config() static. v5: (Ville) - Rename intel_link_bw_limits::min_bpp_pipes to min_bpp_reached_pipes and intel_link_bw_reset_pipe_limit_to_min() to intel_link_bw_set_min_bpp_for_pipe(). - Rename pipe_bpp to link_bpp in intel_link_bw_reduce_bpp(). - Add FIXME: comment about MST encoder's YUV420 BW allocation and tracking the link bpp limit accordingly. v6: - Move intel_link_bw_compute_pipe_bpp() to intel_fdi.c (Ville) - WARN_ON(BIT(pipe) & min_bpp_reached_pipes) in intel_link_bw_set_bpp_limit_for_pipe(). (Ville) - Rename intel_link_bw_set_min_bpp_for_pipe() to intel_link_bw_set_bpp_limit_for_pipe() and intel_link_bw_limits::min_bpp_reached_pipes to bpp_limit_reached_pipes. (Ville) - Remove unused header includes. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Factor out intel_atomic_check_config() to check and compute all the CRTC states. This will be used by a follow up patch to recompute/check the state until required by BW limitations between CRTCs. Reviewed-by:
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Imre Deak authored
Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late() to clarify when the function can be called (vs. intel_modeset_pipes_in_mask_early()). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Add intel_modeset_pipes_in_mask_early() to modeset a provided set of pipes, used in a follow-up patch. As opposed to intel_modeset_all_pipes() which modesets only the active pipes - others don't requiring programming the HW - modeset all enabled pipes in intel_modeset_pipes_in_mask_early() which may need to recompute their state even if they are not active (that is in the DPMS off state). While at it add DocBook descriptions for the two exported functions. v2: - Add a flag controlling if active planes are force updated as well. - Add DockBook descriptions. v3: - For clarity use _early/_late suffixes for the exported functions instead of the update_active_planes parameter. (Ville) v4: - In intel_modeset_pipes_in_mask_early() update only the crtc flags relevant to the early phase. (Ville) - Rename intel_modeset_all_pipes() in a separate patch. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Limit the output link bpp in DSC mode to the link_config_limits link.min_bpp_x16 .. max_bpp_x16 range the same way it's done in non-DSC mode. Atm this doesn't make a difference, the link bpp range being 0 .. max pipe bpp, but a follow-up patch will need a way to reduce max link bpp below its current value. v2: - Add to_bpp_int_roundup() instead of open coding it. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by:
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Imre Deak authored
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp range, while in DSC mode it can be set in 1/16 bpp steps to any value up to the maximum pipe bpp. Update the limits accordingly in both modes to prepare for a follow-up patch which may need to reduce the max link bpp value and starts to check the link bpp limits in DSC mode as well. While at it add more detail to the link limit debug print and print it also for DSC mode. v2: - Add to_bpp_frac_dec() instead of open coding it. (Jani) v3: (Ville) - Add BPP_X16_FMT / BPP_X16_ARG. - Add TODO: comment about initializing the DSC link bpp limits earlier. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Computing the non-DSC mode link config is redundant once it's determined that DSC will be needed, so skip computing it. In a follow-up patch this simplifies setting the link limits which are dependent on the DSC vs. non-DSC mode. While at it sanitize the debug print about the MST DSC fallback path, making it similar to the SST DSC one. Reviewed-by:
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Imre Deak authored
A follow-up patch will need to limit the output link bpp both in the non-DSC and DSC configuration, so track the pipe and link bpp limits separately in the link_config_limits struct. Use .4 fixed point format for link bpp matching the 1/16 bpp granularity in DSC mode and for now keep this limit matching the pipe bpp limit. v2: (Jani) - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them. - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16. Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
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Imre Deak authored
Factor out helpers that DP / DP_MST encoders can use to compute the link rate/lane count and bpp limits. A follow-up patch will call these to recalculate the limits if DSC compression is required. Reviewed-by:
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- 27 Sep, 2023 1 commit
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Ville Syrjälä authored
Normally we could be in a deep PkgC state all the way up to the point when DSB starts its execution at the transcoders undelayed vblank. The DSB will then have to wait for the hardware to wake up before it can execute anything. This will waste a huge chunk of the vblank time just waiting, and risks the DSB execution spilling into the vertical active period. That will be very bad, especially when programming the LUTs as the anti-collision logic will cause DSB to corrupt LUT writes during vertical active. To avoid these problems we can instruct the DSB to pre-wake the display engine on a specific scanline so that everything will be 100% ready to go when we hit the transcoder's undelayed vblank. One annoyance is that the scanline is specified as just that, a single scanline. So if we happen to start the DSB execution after passing said scanline no DEwake will happen and we may drop back into some PkgC state before reaching the transcoder's undelayed vblank. To prevent that we'll use the "force DEwake" bit to manually force the display engine to stay awake. We'll then have to clear the force bit again after the DSB is done (the force bit remains effective even when the DSB is otherwise disabled). Signed-off-by:
Uma Shankar <uma.shankar@intel.com>
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