- 20 Oct, 2016 1 commit
-
-
Zhenyu Wang authored
i915 core should only call functions and structures exposed through intel_gvt.h. Remove internal gvt.h and i915_pvinfo.h. Change for internal intel_gvt structure as private handler which not requires to expose gvt internal structure for i915 core. v2: Fix per Chris's comment - carefully handle dev_priv->gvt assignment - add necessary bracket for macro helper - forward declartion struct intel_gvt - keep free operation within same file handling alloc v3: fix use after free and remove intel_gvt.initialized v4: change to_gvt() to an inline Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com>
-
- 18 Oct, 2016 1 commit
-
-
Zhenyu Wang authored
Change GVT-g code reference for intel_engine_cs from static array to allocated pointer after commit 3b3f1650 ("drm/i915: Allocate intel_engine_cs structure only for the enabled engines"). Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161018014007.29369-1-zhenyuw@linux.intel.com
-
- 17 Oct, 2016 4 commits
-
-
Ville Syrjälä authored
DP link retraining causes (spurious?) underruns. We can't really avoid them, except perhaps by doing a full modeset (which has its own underrun suppression anyway). So let's just hide them. MST still has its own logic for retrainin, but a bigger hpd handling cleanup/unification is needed there anyway, so let's leave that be for now. References: https://bugs.freedesktop.org/show_bug.cgi?id=98251Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1476464574-32230-3-git-send-email-ville.syrjala@linux.intel.comReviewed-by:
-
Ville Syrjälä authored
Extract the code to determine which PCH transcoder we're using to a small helper. Signed-off-by:
-
Ville Syrjälä authored
GMBUS is part of the display engine, and thus has no need for forcewake. Let's not bother trying to grab it then. I don't recall if the display engine suffers from system hangs due to multiple accesses to the same "cacheline" in mmio space. I hope not since we're no longer protected by the uncore lock since commit 4e6c2d58 ("drm/i915: Take forcewake once for the entire GMBUS transaction") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: David Weinehall <david.weinehall@linux.intel.com> Signed-off-by:
-
https://github.com/01org/gvt-linuxDaniel Vetter authored
Zhenyu Wang writes: This is first pull request to merge GVT-g device model in i915 which contains core GVT-g device model work to virtualize GPU resources. This tries to add feature of Intel GVT-g technology for full GPU virtualization. This version will support KVM based virtualization solution named as KVMGT. More background is on official project home: https://01.org/igvt-gSigned-off-by:
Daniel Vetter <daniel.vetter@intel.com>
-
- 16 Oct, 2016 4 commits
-
-
Lyude authored
This function is a wreck, let's help it get its life back together and cleanup all of the copy pasta here. Signed-off-by:
Lyude <cpaul@redhat.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
-
Lyude authored
Having skl_wm_level contain all of the watermarks for each plane is annoying since it prevents us from having any sort of object to represent a single watermark level, something we take advantage of in the next commit to cut down on all of the copy paste code in here. Changes since v1: - Style nitpicks - Fix accidental usage of i vs. PLANE_CURSOR - Split out skl_pipe_wm_active_state simplification into separate patch Signed-off-by:
-
Lyude authored
Next part of cleaning up the watermark code for skl. This is easy, since it seems that we never actually needed to keep track of the linetime in the skl_wm_values struct anyway. Signed-off-by:
-
Lyude authored
First part of cleaning up all of the skl watermark code. This moves the structures for storing the ddb allocations of each pipe into intel_crtc_state, along with moving the structures for storing the current ddb allocations active on hardware into intel_crtc. Changes since v1: - Don't replace alloc->start = alloc->end = 0; Signed-off-by:
-
- 14 Oct, 2016 30 commits
-
-
Tvrtko Ursulin authored
I have re-ordered some struct members in patch: commit 44a655ca Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Date: Thu Oct 13 11:09:23 2016 +0100 drm/i915: Shrink cxsr_latency_table but that particular one is not initialized with named initializers which broke it. Move the bitfields back at the beginning. Space saving is still there. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 44a655ca ("drm/i915: Shrink cxsr_latency_table") Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1476453302-7580-1-git-send-email-tvrtko.ursulin@linux.intel.com
-
Michał Winiarski authored
Since "Dynamic page table allocations" were introduced, our page tables can grow (being dynamically allocated) with address space range usage. Unfortunately, their lifetime is bound to vm. This is not a huge problem when we're not using softpin - drm_mm is creating an upper bound on used range by causing addresses for our VMAs to eventually be reused. With softpin, long lived contexts can drain the system out of memory even with a single "small" object. For example: bo = bo_alloc(size); while(true) offset += size; exec(bo, offset); Will cause us to create new allocations until all memory in the system is used for tracking GPU pages (even though almost all PTEs in this vm are pointing to scratch). Let's free unused page tables in clear_range to prevent this - if no entries are used, we can safely free it and return this information to the caller (so that higher-level entry is pointing to scratch). v2: Document return value and free semantics (Joonas) v3: No newlines in vars block (Joonas) v4: Drop redundant local 'reduce' variable v5: Handle CI fail with enable_ppgtt=2 Cc: Michel Thierry <michel.thierry@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Signed-off-by:
-
Michał Winiarski authored
Let's use more top-down approach, where each gen8_ppgtt_clear_* function is responsible for clearing the struct passed as an argument and calling relevant clear_range functions on lower-level tables. Doing this rather than operating on PTE ranges makes the implementation of shrinking page tables quite simple. v2: Drop min when calculating num_entries, no negation in 48b ppgtt check, no newlines in vars block (Joonas) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
-
Michał Winiarski authored
We never used any invalid ptes, those were put in place for a possibility of doing gpu faults. However our batchbuffers are not restricted in length, so everything needs to be pointing to something and thus out-of-bounds is pointing to scratch. Remove the valid flag as it is always true. v2: Expand commit msg, patch reorder (Mika) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
-
Imre Deak authored
Currently the display INIT power domain disabling/enabling happens in a mismatched way in the suspend/resume_early hooks respectively. This can leave display power wells incorrectly disabled in the resume hook if the suspend sequence is aborted for some reason resulting in the suspend/resume hooks getting called but the suspend_late/resume_early hooks being skipped. In particular this change fixes "Unclaimed read from register 0x1e1204" on BYT/BSW triggered from i915_drm_resume()-> intel_pps_unlock_regs_wa() when suspending with /sys/power/pm_test set to devices. Fixes: 85e90679 ("drm/i915: disable power wells on suspend") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: David Weinehall <david.weinehall@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
-
Tvrtko Ursulin authored
Saves 1416 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Acked-by:
Jani Nikula <jani.nikula@linux.intel.com> Acked-by:
-
Tvrtko Ursulin authored
Saves 968 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) v3: Rebase. Signed-off-by:
-
Tvrtko Ursulin authored
Saves 944 bytes of .rodata strings and 128 bytes of .text. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 864 bytes of .rodata strings and ~100 of .text. v2: Add parantheses around dev_priv. (Ville Syrjala) v3: Rebase. Signed-off-by:
-
Tvrtko Ursulin authored
Saves 472 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 472 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 1392 bytes of .rodata strings. Also change a few function/macro prototypes in i915_gem_gtt.c from dev to dev_priv where it made more sense to do so. v2: Add parantheses around dev_priv. (Ville Syrjala) v3: Mention function prototype changes. (David Weinehall) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 1016 bytes of .rodata strings and couple hundred of .text. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 1320 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 2432 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 1808 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 848 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) v3: Rebase. Signed-off-by:
-
Tvrtko Ursulin authored
Saves 4472 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 944 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
Saves 1520 bytes of .rodata strings. Signed-off-by:
-
Tvrtko Ursulin authored
Saves 960 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
More .rodata string saving by avoid __I915__ magic inside WARNs. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
This saves 1872 bytes of .rodata strings. v2: * Rebase. * Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Tvrtko Ursulin authored
This saves 3248 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by:
-
Zhi Wang authored
GVT-g supports Intel Skylake platform. Enable it. Signed-off-by:
Zhi Wang <zhi.a.wang@intel.com> Signed-off-by:
-
Zhi Wang authored
This patch introduces a command scanner to scan guest command buffers. Signed-off-by:
Yulei Zhang <yulei.zhang@intel.com> Signed-off-by:
-
Zhi Wang authored
As different VM may configure different render MMIOs when executing workload, to schedule workloads between different VM, the render MMIOs have to be switched. Signed-off-by:
-
Zhi Wang authored
This patch introduces a vGPU schedule policy framework, with a timer based schedule policy module for now Signed-off-by:
-
Zhi Wang authored
This patch introduces the vGPU workload scheduler routines. GVT workload scheduler is responsible for picking and executing GVT workload from current scheduled vGPU. Before the workload is submitted to host i915, the guest execlist context will be shadowed in the host GVT shadow context. the instructions in guest ring buffer will be copied into GVT shadow ring buffer. Then GVT-g workload scheduler will scan the instructions in guest ring buffer and submit it to host i915. Signed-off-by:
-
Zhi Wang authored
This patch introduces the vGPU workload submission logics. Under virtualization environment, guest will submit workload through virtual execlist submit port. The submitted workload load will be wrapped into an gvt workload which will be picked by GVT workload scheduler and executed on host i915 later. Signed-off-by:
-
