- 20 Jan, 2023 1 commit
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Jani Nikula authored
We already have i915_config.c. Add the i915_config.h counterpart, and declutter i915_drv.h in the process. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by:
Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230118131538.3558599-1-jani.nikula@intel.com
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- 18 Jan, 2023 11 commits
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Deepak R Varma authored
Convert function i9xx_pipe_crc_auto_source() to return void instead of int since the current implementation always returns 0 to the caller. Issue identified using returnvar Coccinelle semantic patch. $ make coccicheck COCCI=scripts/coccinelle/misc/returnvar.cocci \ M=drivers/gpu/drm/i915/ Signed-off-by:
Deepak R Varma <drv@mailo.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Jani Nikula authored
Move the display related members to the struct drm_i915_private display sub-struct. Put them under "state", as they are related to storing values that aren't readable from the hardware, to appease the state checker. Signed-off-by:
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Jani Nikula authored
Move the display related member to the struct drm_i915_private display sub-struct. Signed-off-by:
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Jani Nikula authored
Move the display related member to the struct drm_i915_private display sub-struct. Signed-off-by:
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Jani Nikula authored
Since commit 52c4d11f ("resource: Convert DEFINE_RES_NAMED() to be compound literal") it's no longer necessary to cast DEFINE_RES_MEM() to struct resource. This also fixes sparse warnings "cast from non-scalar" and "cast to non-scalar". Signed-off-by:
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Jani Nikula authored
Wrap the stolen memory related struct drm_i915_private members (dsm, dsm_reserved, and stolen_usable_size) together in a a new struct i915_dsm. Signed-off-by:
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Jani Nikula authored
Add intel_de_read64_2x32() wrapper for the uncore version of the same, and use it to read the high and low frame registers. Avoid duplicating code for existing helpers. The slight functional difference is checking that the entire high register remains the same across two reads, instead of just the part we're interested in. This should be of no consequence. (Unless those bits function as a PRNG.) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/33853549adff82045b95af527e14cfdff5712470.1673873708.git.jani.nikula@intel.com
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Jani Nikula authored
Use the intel_de_* functions for display registers. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
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Jani Nikula authored
cpt_verify_modeset() is roughly the same as intel_wait_for_pipe_scanline_moving(). Assume it's close enough. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Reduce clutter in intel_display.c by moving the scanline moving/stopped wait functions to intel_vblank.[ch]. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
The vblank/scanline code is fairly isolated in i915_irq.c. Split it out to new intel_vblank.[ch]. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 17 Jan, 2023 1 commit
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Jouni Högander authored
Add 4th pipe and extend TGL Wa_16013835468 to support ADLP, MTL and DG2 and all TGL steppings. BSpec: 54369, 55378, 66624 v3: - commit message modified v2: - apply for PSR1 as well - remove stepping information from comments Cc: Matt Roper <matthew.d.roper@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230105065637.2063311-1-jouni.hogander@intel.com
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- 16 Jan, 2023 1 commit
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Jani Nikula authored
Drop the redundant sub-directory from #includes under display/. Group and sort the results. v2: Rebase Reviewed-by:
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- 13 Jan, 2023 13 commits
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Deepak R Varma authored
Using DEFINE_SIMPLE_ATTRIBUTE macro with the debugfs_create_file() function adds the overhead of introducing a proxy file operation functions to wrap the original read/write inside file removal protection functions. This adds significant overhead in terms of introducing and managing the proxy factory file operations structure and function wrapping at runtime. As a replacement, a combination of DEFINE_DEBUGFS_ATTRIBUTE macro paired with debugfs_create_file_unsafe() is suggested to be used instead. The DEFINE_DEBUGFS_ATTRIBUTE utilises debugfs_file_get() and debugfs_file_put() wrappers to protect the original read and write function calls for the debug attributes. There is no need for any runtime proxy file operations to be managed by the debugfs core. Following coccicheck make command helped identify this change: make coccicheck M=drivers/gpu/drm/i915/ MODE=patch COCCI=./scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci Signed-off-by:
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Deepak R Varma authored
Using DEFINE_SIMPLE_ATTRIBUTE macro with the debugfs_create_file() function adds the overhead of introducing a proxy file operation functions to wrap the original read/write inside file removal protection functions. This adds significant overhead in terms of introducing and managing the proxy factory file operations structure and function wrapping at runtime. As a replacement, a combination of DEFINE_DEBUGFS_ATTRIBUTE macro paired with debugfs_create_file_unsafe() is suggested to be used instead. The DEFINE_DEBUGFS_ATTRIBUTE utilises debugfs_file_get() and debugfs_file_put() wrappers to protect the original read and write function calls for the debug attributes. There is no need for any runtime proxy file operations to be managed by the debugfs core. Following coccicheck make command helped identify this change: make coccicheck M=drivers/gpu/drm/i915/ MODE=patch COCCI=./scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci Signed-off-by:
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Ville Syrjälä authored
Add all the know DSB instruction opcodes. Signed-off-by:
Animesh Manna <animesh.manna@intel.com>
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Ville Syrjälä authored
The caller should more or less know how many DSB commands it wants to emit into the command buffer, so allow it to specify the size of the command buffer rather than having the low level DSB code guess it. Technically we can emit as many as 134+1033 (for adl+ degamma + 10bit gamma) register writes but thanks to the DSB indexed register write command we get significant space savings so the current size estimate of 8KiB (~1024 DSB commands) is sufficient for now. Signed-off-by:
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Ville Syrjälä authored
Move the DSB tail cacheline alignment to a helper. No need to pollute the caller with mundane details like this. Signed-off-by:
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Ville Syrjälä authored
The DSB indexed register write insturction is purely an internal DSB implementation detail, no reason why the caller should have to know about it. So let's just have the caller emit blind register writes let the DSB code convert things to an indexed write if/when multiple writes occur to the same register offset in a row. Signed-off-by:
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Ville Syrjälä authored
Currently intel_dsb_indexed_reg_write() just assumes the previous instructions is also an indexed register write, and thus only checks the register offset. Make the check more robust by actually checking the instruction opcode as well. Signed-off-by:
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Ville Syrjälä authored
Extract a small helper to emit a DSB intstruction. Should become useful if/when we need to start emitting other instructions besides register writes. Signed-off-by:
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Ville Syrjälä authored
Pull the DSB command buffer size checks into a small helper so we don't have repeat the same thing multiple times. Signed-off-by:
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Ville Syrjälä authored
free_pos is in dwords, DSB_BUF_SIZE in bytes. Directly comparing the two is nonsense. Fix it up, and make sure we also account for the 8byte alignment requirement for each instruction, and also assume that each instruction normally eats two dwords. Signed-off-by:
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Ville Syrjälä authored
Every DSB instruction has to be 8byte aligned. Make sure that is the case for the non-indexed register writes as well. The way this could end up unaligned is we emitted an odd number of indexed register writes beforehand. Signed-off-by:
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Ville Syrjälä authored
No point in having these wrappers for a simple DSB_CTRL write. Inline them into intel_dsb_commit(). Signed-off-by:
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Ville Syrjälä authored
We don't want to keep random bits set in DSB_CTRL. Stop the harmful RMW. Also flip the reverse & around to appease my ocd. Signed-off-by:
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- 12 Jan, 2023 3 commits
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Drew Davenport authored
The error message suggests that the height of the src rect must be at least 1. Reject source with height of 0. Cc: stable@vger.kernel.org Signed-off-by:
Drew Davenport <ddavenport@chromium.org> Signed-off-by:
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Ankit Nautiyal authored
Defeature Display Interlace support. Support for interlace modes is removed from Gen 12 onwards. Pruning the interlace modes for HDMI for Display >=12. Bspec: 50490 v2: Add check for both DP and HDMI. (Ville) Get rid of redundant check for interlace mode in modevalid. (Ville) v3: Simplify the condition to avoid interlace modes. (Jani) Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230105124125.1129653-1-ankit.k.nautiyal@intel.com
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Ankit Nautiyal authored
Since the DP/HDMI connector do not set connector->doublescan_allowed, the doublescan modes will get automatically filtered during drm_helper_probe_single_connector_modes(). Therefore check for double scan modes is not required and is dropped from modevalid functions for both DP and HDMI. Signed-off-by:
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- 10 Jan, 2023 2 commits
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Animesh Manna authored
The max source and destination limits for scalers in MTL have changed. Use the new values accordingly. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221223130509.43245-3-luciano.coelho@intel.com
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Luca Coelho authored
In newer hardware versions (i.e. display version >= 14), the second scaler doesn't support vertical scaling. The current implementation of the scaling limits is simplified and only occurs when the planes are created, so we don't know which scaler is being used. In order to handle separate scaling limits for horizontal and vertical scaling, and different limits per scaler, split the checks in two phases. We first do a simple check during plane creation and use the best-case scenario (because we don't know the scaler that may be used at a later point) and then do a more specific check when the scalers are actually being set up. Signed-off-by:
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- 09 Jan, 2023 1 commit
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Stanislav Lisovskiy authored
We now accept timeslots param exactly how the variable sounds: amount of timeslots, but not ratio timeslots/64. So for SST case(when we have all timeslots for use), it should be 64, but not 1. This caused some issues in the tests. v2: Fixed comments References: https://gitlab.freedesktop.org/drm/intel/-/issues/6860 Fixes: 52f14682 ("drm/i915: Bpp/timeslot calculation fixes for DP MST DSC") Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 06 Jan, 2023 1 commit
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Nirmoy Das authored
Fix docs for __intel_wakeref_put() and intel_wakeref_get() to reflect current behaviour. Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
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- 05 Jan, 2023 1 commit
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Rodrigo Vivi authored
There are new cases where we want to block i915 probe, such as when experimenting or developing the new Xe driver. But also, with the new hybrid cards, users or developers might want to use i915 only on integrated and fully block the probe of the i915 for the discrete. Or vice versa. There are even older development and validation reasons, like when you use some distro where the modprobe.blacklist is not present. But in any case, let's introduce a more granular control, but without introducing yet another parameter, but using the existent force_probe one. Just by adding a ! in the begin of the id in the force_probe, like in this case where we would block the probe for Alder Lake: $ insmod i915.ko force_probe='!46a6' v2: Take care of '*' and '!*' cases as pointed out by Gustavo and Jani. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230103194701.1492984-1-rodrigo.vivi@intel.com
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- 04 Jan, 2023 1 commit
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Arun R Murthy authored
The busy timeout logic checks for the AUX BUSY, then waits for the timeout period and then after timeout reads the register for BUSY or Success. Instead replace interrupt with polling so as to read the AUX CTL register often before the timeout period. Looks like there might be some issue with interrupt-on-read. Hence changing the logic to polling read. v2: replace interrupt with polling read v3: use usleep_rang instead of msleep, updated commit msg v4: use intel_wait_for_regiter internal function v5: use __intel_de_wait_for_register with 500us slow and 10ms fast timeout v6: check return value of __intel_de_wait_for_register v7: using default 2us for intel_de_wait_for_register Signed-off-by:
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- 03 Jan, 2023 2 commits
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Gustavo Sousa authored
Currently, i915 interacts with the Hardware and not with any DMC ABI/API, so the API is fixed within the platform, hence no need to get this so-tied version requirement. v2: - Use link to firmware guide from kernel documentation for "References:" instead of mailing list thread. (Rodrigo) - Provide a more elaborate justification in the commit message. (Rodrigo) References: https://www.kernel.org/doc/html/v6.1/driver-api/firmware/firmware-usage-guidelines.htmlSigned-off-by: -
Jonathan Cavitt authored
Add .has_4tile tag to XE_HP_FEATURES set. Remove duplicate entry from DG2_FEATURES. Signed-off-by:
Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Roper Matthew D <matthew.d.roper@intel.com> Cc: Kempczynski Zbigniew <Zbigniew.Kempczynski@intel.com> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com> Acked-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by:
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- 02 Jan, 2023 1 commit
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Jani Nikula authored
Sync up with v6.2-rc1. Signed-off-by:
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- 25 Dec, 2022 1 commit
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Linus Torvalds authored
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