- 16 Jan, 2020 6 commits
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Alex Sierra authored
[Why] TLB flush method has been deprecated using kfd2kgd interface. This implementation is now on the amdgpu_amdkfd API. [How] TLB flush functions now implemented in amdgpu_amdkfd. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Sierra authored
This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Signed-off-by:
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Alex Sierra authored
[Why] There are HW-indpendent functions that enables and disables kcq. These functions use the kiq_pm4_funcs implementation. [How] Local kcq enable and disable functions removed and replace it by the generic kcq enable under amdgpu_gfx Signed-off-by:
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Alex Sierra authored
tlbs invalidate pointer function added to kiq_pm4_funcs struct. This way, tlb flush can be done through kiq member. TLBs invalidatation implemented for gfx9 and gfx10. Signed-off-by:
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Alex Sierra authored
Functions implemented from kiq_pm4_funcs struct members for gfx_v9 version. Signed-off-by:
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Alex Sierra authored
[Why] Avoid reclaim filesystem while eviction lock is held called from MMU notifier. [How] Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked. Using memalloc_nofs_save / memalloc_nofs_restore API. Signed-off-by:
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- 14 Jan, 2020 34 commits
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Alex Deucher authored
If driver debugfs files are accessed, power up the GPU when necessary. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
If power management sysfs or debugfs files are accessed, power up the GPU when necessary. Reviewed-by:
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Flora Cui authored
Fixes: 4dee6e4c ("drm/amdgpu: use linux size macro to simplify ONE_Kib & One_Mib") Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Chen Zhou authored
The conversion to bool is not needed, remove it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Chen Zhou <chenzhou10@huawei.com> Signed-off-by:
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Mario Kleiner authored
read_current_link_settings_on_detect() on eDP 1.4+ may use the edp_supported_link_rates table which is set up by detect_edp_sink_caps(), so that function needs to be called first. Reviewed-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Martin Leung <martin.leung@amd.com> Signed-off-by:
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Alex Deucher authored
So that it gets included in the initrd. At the moment this is optional firmware that contains support for HDCP. Reviewed-by:
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Joseph Greathouse authored
On Arcturus, data fabric hashing is set by the VBIOS, and affects which addresses map to which memory channels. The gfx core's caches also need to know this mapping, but the hash settings for these these caches is set by the driver. This change queries the DF to understand how the VBIOS configured DF, then matches the TC hash configuration bits to do the same thing. v2: squash in warning fix Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
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Joseph Greathouse authored
On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by:
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Joseph Greathouse authored
The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon. Signed-off-by:
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Michael Strauss authored
[WHY] Only a single voltage level should be available to Pollock (min level) Pollock & Dali get misidentified as Renoir, use wrong clk mgr constructor [HOW] Add provided Pollock IDs to ASIC Rev. ID list. Create new Pollock ASIC RID check, fix RV2 & Dali ASIC checks. Check RID and set max voltage level to 0 if Pollock is detected. Work around broken ASICREV_IS_RENOIR, IS_RAVEN2, etc. checks by performing Dali/Pollock checks before they can be misidentified as RN. Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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John Clements authored
between UMC RAS err register access restore previous RSMU UMC index mode state Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
in event of GPU reset, XGMI TA unload causes unrecoverable GPU hang Acked-by:
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Aaron Liu authored
Update mmSDMA0_UTCL1_WATERMK golden setting for renoir. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Aaron Liu authored
This patch updates SMU12_DRIVER_IF_VERSION to 11. Signed-off-by:
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Alex Deucher authored
We don't need to store the pre-OS console memory after the driver has loaded so free it. Reviewed-by:
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Alex Deucher authored
Leftover from bring up. We look up the actual pre-OS memory usage value later in the same function. Reviewed-by:
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Alex Deucher authored
It won't get used unless the driver allows the gtt domain for display buffers which is controlled elsewhere. Reviewed-by:
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Alex Deucher authored
It should work on all Raven variants, but some users have reported issues with original Raven with IOMMU enabled. So far there have been no issues observed with PCO or RV2. v2: split out the dm init and domain changes into separate patches. Acked-by: -
Alex Deucher authored
It won't get used unless the driver allows the gtt domain for display buffers which is controlled elsewhere. Acked-by:
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Alex Deucher authored
All of the sdma stuff these were used for moves to the sdma code, so remove them. Reviewed-by:
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Tom St Denis authored
(v2): Fix preprocessor tag Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Hawking Zhang authored
sdma ras funcs are not supported by ASIC prior to vega20 Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Guchun Chen authored
Hardcoded offset is not friendly. And another benifit of this patch is to keep read and write access to this register be consistent with other similar UMC regsiters in this file. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Both are needed on vega20 and arcturus chip. Signed-off-by:
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Alex Deucher authored
Cast to make min() happy. The values are well within range. Reviewed-by:
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Kenneth Feng authored
change the sw ctf setting to smu_v11_0_set_thermal_range() since software_shutdown_temp shares the same definition and name in all the smu11 project. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Tiecheng Zhou authored
guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. v2. add comment in the code Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] There is a use case that link loss happens accidentally, and we need to recover that link loss as soon as possible. Under this circumstance, we will perform link training, and try to recover the link that's just lost. However, if link PHY is disabled before link training happens, then DP display will never come back again. Also, please note that dropping this disable_phy function call won't break USB-C hotplug functionality. (This line of code was firstly introduced associated with a patch to fix USB-C hotplug issue) [How] Don't disable DP transmitter and its encoder before link training happens, even if link loss is detected. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
SDMA edc counter registers were added in gfx edc counters array. When querying gfx error counter in that array, there is no way to differentiate sdma instance number for different asic and then results to NULL pointer access when trying to read sdma register base address for instances greater than 2 on Vega20. In addition, this also results to wrong gfx error counters since it actually added sdma edc counters. Therefore, sdma edc counter registers should be separated from gfx edc counter regsiter array and only get initialized when driver tries to enable sdma ras. Signed-off-by:
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Hawking Zhang authored
move ras_late_init and ras_fini to sdma_ras_funcs table Signed-off-by:
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Hawking Zhang authored
invoke sdma query_ras_error_count to get sdma single bit error count Signed-off-by:
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Hawking Zhang authored
query_ras_error_count function will be invoked to query single bit error count detected in sdma ip block Signed-off-by:
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Leo Liu authored
With default PSP FW loading Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
ucodes for instances are from different location Signed-off-by:
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