• Archit Taneja's avatar
    mtd: nand: Qualcomm NAND controller driver · c76b78d8
    Archit Taneja authored
    The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
    MDM9x15 series.
    
    It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
    and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
    broader interface for external slow peripheral devices such as LCD and
    NAND/NOR flash memory or SRAM like interfaces.
    
    We add support for the NAND controller found within EBI2. For the SoCs
    of our interest, we only use the NAND controller within EBI2. Therefore,
    it's safe for us to assume that the NAND controller is a standalone block
    within the SoC.
    
    The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
    flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
    16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
    and spare data. The controller contains an internal 512 byte page buffer
    to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
    for register read/write and data transfers. The controller performs page
    reads and writes at a codeword/step level of 512 bytes. It can support up
    to 2 external chips of different configurations.
    
    The driver prepares register read and write configuration descriptors for
    each codeword, followed by data descriptors to read or write data from the
    controller's internal buffer. It uses a single ADM DMA channel that we get
    via dmaengine API. The controller requires 2 ADM CRCIs for command and
    data flow control. These are passed via DT.
    
    The ecc layout used by the controller is syndrome like, but we can't use
    the standard syndrome ecc ops because of several reasons. First, the amount
    of data bytes covered by ecc isn't same in each step. Second, writing to
    free oob space requires us writing to the entire step in which the oob
    lies. This forces us to create our own ecc ops.
    
    One more difference is how the controller accesses the bad block marker.
    The controller ignores reading the marker when ECC is enabled. ECC needs
    to be explicity disabled to read or write to the bad block marker. The
    nand_bbt helpers library hence can't access BBMs for the controller.
    For now, we skip the creation of BBT and populate chip->block_bad and
    chip->block_markbad helpers instead.
    Reviewed-by: default avatarAndy Gross <agross@codeaurora.org>
    Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
    Reviewed-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
    Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
    c76b78d8
Makefile 2.54 KB