• Joseph Lo's avatar
    ARM: tegra30: cpuidle: add powered-down state for CPU0 · d552920a
    Joseph Lo authored
    This is a power gating idle mode. It support power gating vdd_cpu rail
    after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can
    enter this state only when all secondary CPU is offline. We need to take
    care and make sure whole secondary CPUs were offline and checking the
    CPU power gate status. After that, the CPU0 can go into "powered-down"
    state safely. Then shut off the CPU rail.
    
    Be aware of that, you may see the legacy power state "LP2" in the code
    which is exactly the same meaning of "CPU power down".
    
    Base on the work by:
    Scott Williams <scwilliams@nvidia.com>
    Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
    Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
    d552920a
sleep-tegra30.S 4.15 KB