Commit 3745d19b authored by Niklas Cassel's avatar Niklas Cassel Committed by Arnd Bergmann

ARM: dts: artpec: add and utilize artpec6 pin controller

Add node for the pin controller used in the artpec6 SoC,
and start using it for the exising UARTs.
Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent b49de2df
......@@ -180,6 +180,32 @@ pcie: pcie@f8050000 {
status = "disabled";
};
pinctrl: pinctrl@f801d000 {
compatible = "axis,artpec6-pinctrl";
reg = <0xf801d000 0x400>;
pinctrl_uart0: uart0grp {
function = "uart0";
groups = "uart0grp2";
bias-pull-up;
};
pinctrl_uart1: uart1grp {
function = "uart1";
groups = "uart1grp0";
bias-pull-up;
};
pinctrl_uart2: uart2grp {
function = "uart2";
groups = "uart2grp1";
bias-pull-up;
};
pinctrl_uart3: uart3grp {
function = "uart3";
groups = "uart3grp0";
bias-pull-up;
};
};
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
......@@ -238,6 +264,8 @@ uart0: serial@f8036000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
uart1: serial@f8037000 {
......@@ -247,6 +275,8 @@ uart1: serial@f8037000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
uart2: serial@f8038000 {
......@@ -256,6 +286,8 @@ uart2: serial@f8038000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
uart3: serial@f8039000 {
......@@ -265,6 +297,8 @@ uart3: serial@f8039000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
};
......
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