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Commit 791c6fdb authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'qcom-dts-for-5.3' of... 

Merge tag 'qcom-dts-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm Device Tree Changes for v5.3

* Add display support to MSM8974
* Add display, backlight, and touchscreen support to MSM8974 Hammerhead
* Update coresight bindings for MSM8974 and APQ8064

* tag 'qcom-dts-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: msm8974-hammerhead: add support for display
  ARM: dts: msm8974: add display support
  ARM: dts: qcom: msm8974-hammerhead: add support for backlight
  ARM: dts: qcom: msm8974-hammerhead: add touchscreen support
  ARM: dts: qcom-msm8974: Update coresight DT bindings
  ARM: dts: qcom-apq8064: Update coresight DT bindings
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 750ee785 489bacb2
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Showing with 293 additions and 5 deletions
arch/arm/boot/dts/qcom-apq8064.dtsi
View file @ 791c6fdb
......@@ -1603,7 +1603,7 @@ tpiu_in: endpoint {
};
replicator {
compatible = "arm,coresight-replicator";
compatible = "arm,coresight-static-replicator";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
......@@ -1636,7 +1636,7 @@ replicator_in: endpoint {
};
funnel@1a04000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x1a04000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
......
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View file @ 791c6fdb
......@@ -280,6 +280,16 @@ mux {
};
};
i2c2_pins: i2c2 {
mux {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
};
i2c3_pins: i2c3 {
mux {
pins = "gpio10", "gpio11";
......@@ -289,6 +299,16 @@ mux {
};
};
i2c11_pins: i2c11 {
mux {
pins = "gpio83", "gpio84";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
};
i2c12_pins: i2c12 {
mux {
pins = "gpio87", "gpio88";
......@@ -306,6 +326,35 @@ irq {
input-enable;
};
};
touch_pin: touch {
int {
pins = "gpio5";
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
reset {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
panel_pin: panel {
te {
pins = "gpio12";
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
};
};
};
sdhci@f9824900 {
......@@ -369,6 +418,30 @@ volume-down {
};
};
i2c@f9967000 {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&i2c11_pins>;
clock-frequency = <355000>;
qcom,src-freq = <50000000>;
led-controller@38 {
compatible = "ti,lm3630a";
status = "ok";
reg = <0x38>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
led-sources = <0 1>;
label = "lcd-backlight";
default-brightness = <200>;
};
};
};
i2c@f9968000 {
status = "ok";
pinctrl-names = "default";
......@@ -424,6 +497,41 @@ charger: bq24192@6b {
};
};
i2c@f9924000 {
status = "ok";
clock-frequency = <355000>;
qcom,src-freq = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
synaptics@70 {
compatible = "syna,rmi4-i2c";
reg = <0x70>;
interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8941_l22>;
vio-supply = <&pm8941_lvs3>;
pinctrl-names = "default";
pinctrl-0 = <&touch_pin>;
#address-cells = <1>;
#size-cells = <0>;
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
};
};
};
i2c@f9925000 {
status = "ok";
pinctrl-names = "default";
......@@ -466,6 +574,54 @@ phy@a {
};
};
};
mdss@fd900000 {
status = "ok";
mdp@fd900000 {
status = "ok";
};
dsi@fd922800 {
status = "ok";
vdda-supply = <&pm8941_l2>;
vdd-supply = <&pm8941_lvs3>;
vddio-supply = <&pm8941_l12>;
#address-cells = <1>;
#size-cells = <0>;
ports {
port@1 {
endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
panel: panel@0 {
reg = <0>;
compatible = "lg,acx467akm-7";
pinctrl-names = "default";
pinctrl-0 = <&panel_pin>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
dsi-phy@fd922a00 {
status = "ok";
vddio-supply = <&pm8941_l12>;
};
};
};
&spmi_bus {
......
arch/arm/boot/dts/qcom-msm8974.dtsi
View file @ 791c6fdb
......@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -897,7 +898,7 @@ etf_in: endpoint {
};
funnel@fc31b000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc31b000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
......@@ -931,7 +932,7 @@ merger_out: endpoint {
};
funnel@fc31a000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc31a000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
......@@ -969,7 +970,7 @@ funnel1_out: endpoint {
};
funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc345000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
......@@ -1085,6 +1086,137 @@ etm3_out: endpoint {
};
};
};
mdss: mdss@fd900000 {
status = "disabled";
compatible = "qcom,mdss";
reg = <0xfd900000 0x100>,
<0xfd924000 0x1000>;
reg-names = "mdss_phys",
"vbif_phys";
power-domains = <&mmcc MDSS_GDSC>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"vsync";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mdp: mdp@fd900000 {
status = "disabled";
compatible = "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0 0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi0: dsi@fd922800 {
status = "disabled";
compatible = "qcom,mdss-dsi-ctrl";
reg = <0xfd922800 0x1f8>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi_phy0 0>,
<&dsi_phy0 1>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core",
"core_mmss";
phys = <&dsi_phy0>;
phy-names = "dsi-phy";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi_phy0: dsi-phy@fd922a00 {
status = "disabled";
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
<0xfd922d80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
qcom,dsi-phy-index = <0>;
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface";
};
};
};
smd {
......
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