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Commit e3c71eb2 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/gr: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 05c7145d
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Showing with 3175 additions and 3261 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View file @ e3c71eb2
......@@ -250,5 +250,6 @@
#define nouveau_disp nvkm_disp
#define nouveau_fifo_chan nvkm_fifo_chan
#define nouveau_fifo nvkm_fifo
#define nouveau_gr nvkm_gr
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View file @ e3c71eb2
#ifndef __NOUVEAU_GR_H__
#define __NOUVEAU_GR_H__
#include <core/engine.h>
#ifndef __NVKM_GR_H__
#define __NVKM_GR_H__
#include <core/engctx.h>
#include <core/enum.h>
struct nouveau_gr_chan {
struct nouveau_engctx base;
struct nvkm_gr_chan {
struct nvkm_engctx base;
};
#define nouveau_gr_context_create(p,e,c,g,s,a,f,d) \
nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
#define nouveau_gr_context_destroy(d) \
nouveau_engctx_destroy(&(d)->base)
#define nouveau_gr_context_init(d) \
nouveau_engctx_init(&(d)->base)
#define nouveau_gr_context_fini(d,s) \
nouveau_engctx_fini(&(d)->base, (s))
#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \
nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
#define nvkm_gr_context_destroy(d) \
nvkm_engctx_destroy(&(d)->base)
#define nvkm_gr_context_init(d) \
nvkm_engctx_init(&(d)->base)
#define nvkm_gr_context_fini(d,s) \
nvkm_engctx_fini(&(d)->base, (s))
#define _nvkm_gr_context_dtor _nvkm_engctx_dtor
#define _nvkm_gr_context_init _nvkm_engctx_init
#define _nvkm_gr_context_fini _nvkm_engctx_fini
#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32
#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32
#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
#define _nouveau_gr_context_init _nouveau_engctx_init
#define _nouveau_gr_context_fini _nouveau_engctx_fini
#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
#include <core/engine.h>
struct nouveau_gr {
struct nouveau_engine base;
struct nvkm_gr {
struct nvkm_engine base;
/* Returns chipset-specific counts of units packed into an u64.
*/
u64 (*units)(struct nouveau_gr *);
u64 (*units)(struct nvkm_gr *);
};
static inline struct nouveau_gr *
nouveau_gr(void *obj)
static inline struct nvkm_gr *
nvkm_gr(void *obj)
{
return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR);
}
#define nouveau_gr_create(p,e,c,y,d) \
nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
#define nouveau_gr_destroy(d) \
nouveau_engine_destroy(&(d)->base)
#define nouveau_gr_init(d) \
nouveau_engine_init(&(d)->base)
#define nouveau_gr_fini(d,s) \
nouveau_engine_fini(&(d)->base, (s))
#define nvkm_gr_create(p,e,c,y,d) \
nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
#define nvkm_gr_destroy(d) \
nvkm_engine_destroy(&(d)->base)
#define nvkm_gr_init(d) \
nvkm_engine_init(&(d)->base)
#define nvkm_gr_fini(d,s) \
nvkm_engine_fini(&(d)->base, (s))
#define _nouveau_gr_dtor _nouveau_engine_dtor
#define _nouveau_gr_init _nouveau_engine_init
#define _nouveau_gr_fini _nouveau_engine_fini
#define _nvkm_gr_dtor _nvkm_engine_dtor
#define _nvkm_gr_init _nvkm_engine_init
#define _nvkm_gr_fini _nvkm_engine_fini
extern struct nouveau_oclass nv04_gr_oclass;
extern struct nouveau_oclass nv10_gr_oclass;
extern struct nouveau_oclass nv20_gr_oclass;
extern struct nouveau_oclass nv25_gr_oclass;
extern struct nouveau_oclass nv2a_gr_oclass;
extern struct nouveau_oclass nv30_gr_oclass;
extern struct nouveau_oclass nv34_gr_oclass;
extern struct nouveau_oclass nv35_gr_oclass;
extern struct nouveau_oclass nv40_gr_oclass;
extern struct nouveau_oclass nv50_gr_oclass;
extern struct nouveau_oclass *nvc0_gr_oclass;
extern struct nouveau_oclass *nvc1_gr_oclass;
extern struct nouveau_oclass *nvc4_gr_oclass;
extern struct nouveau_oclass *nvc8_gr_oclass;
extern struct nouveau_oclass *nvd7_gr_oclass;
extern struct nouveau_oclass *nvd9_gr_oclass;
extern struct nouveau_oclass *nve4_gr_oclass;
extern struct nouveau_oclass *gk20a_gr_oclass;
extern struct nouveau_oclass *nvf0_gr_oclass;
extern struct nouveau_oclass *gk110b_gr_oclass;
extern struct nouveau_oclass *nv108_gr_oclass;
extern struct nouveau_oclass *gm107_gr_oclass;
extern struct nvkm_oclass nv04_gr_oclass;
extern struct nvkm_oclass nv10_gr_oclass;
extern struct nvkm_oclass nv20_gr_oclass;
extern struct nvkm_oclass nv25_gr_oclass;
extern struct nvkm_oclass nv2a_gr_oclass;
extern struct nvkm_oclass nv30_gr_oclass;
extern struct nvkm_oclass nv34_gr_oclass;
extern struct nvkm_oclass nv35_gr_oclass;
extern struct nvkm_oclass nv40_gr_oclass;
extern struct nvkm_oclass nv50_gr_oclass;
extern struct nvkm_oclass *gf100_gr_oclass;
extern struct nvkm_oclass *gf108_gr_oclass;
extern struct nvkm_oclass *gf104_gr_oclass;
extern struct nvkm_oclass *gf110_gr_oclass;
extern struct nvkm_oclass *gf117_gr_oclass;
extern struct nvkm_oclass *gf119_gr_oclass;
extern struct nvkm_oclass *gk104_gr_oclass;
extern struct nvkm_oclass *gk20a_gr_oclass;
extern struct nvkm_oclass *gk110_gr_oclass;
extern struct nvkm_oclass *gk110b_gr_oclass;
extern struct nvkm_oclass *gk208_gr_oclass;
extern struct nvkm_oclass *gm107_gr_oclass;
extern const struct nouveau_bitfield nv04_gr_nsource[];
extern struct nouveau_ofuncs nv04_gr_ofuncs;
bool nv04_gr_idle(void *obj);
#include <core/enum.h>
extern const struct nouveau_bitfield nv10_gr_intr_name[];
extern const struct nouveau_bitfield nv10_gr_nstatus[];
extern const struct nvkm_bitfield nv04_gr_nsource[];
extern struct nvkm_ofuncs nv04_gr_ofuncs;
bool nv04_gr_idle(void *obj);
extern const struct nouveau_enum nv50_data_error_names[];
extern const struct nvkm_bitfield nv10_gr_intr_name[];
extern const struct nvkm_bitfield nv10_gr_nstatus[];
extern const struct nvkm_enum nv50_data_error_names[];
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ e3c71eb2
......@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ e3c71eb2
......@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
View file @ e3c71eb2
nvkm-y += nvkm/engine/gr/ctxnv40.o
nvkm-y += nvkm/engine/gr/ctxnv50.o
nvkm-y += nvkm/engine/gr/ctxnvc0.o
nvkm-y += nvkm/engine/gr/ctxnvc1.o
nvkm-y += nvkm/engine/gr/ctxnvc4.o
nvkm-y += nvkm/engine/gr/ctxnvc8.o
nvkm-y += nvkm/engine/gr/ctxnvd7.o
nvkm-y += nvkm/engine/gr/ctxnvd9.o
nvkm-y += nvkm/engine/gr/ctxnve4.o
nvkm-y += nvkm/engine/gr/ctxgf100.o
nvkm-y += nvkm/engine/gr/ctxgf108.o
nvkm-y += nvkm/engine/gr/ctxgf104.o
nvkm-y += nvkm/engine/gr/ctxgf110.o
nvkm-y += nvkm/engine/gr/ctxgf117.o
nvkm-y += nvkm/engine/gr/ctxgf119.o
nvkm-y += nvkm/engine/gr/ctxgk104.o
nvkm-y += nvkm/engine/gr/ctxgk20a.o
nvkm-y += nvkm/engine/gr/ctxnvf0.o
nvkm-y += nvkm/engine/gr/ctxgk110.o
nvkm-y += nvkm/engine/gr/ctxgk110b.o
nvkm-y += nvkm/engine/gr/ctxnv108.o
nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
......@@ -22,15 +22,15 @@ nvkm-y += nvkm/engine/gr/nv34.o
nvkm-y += nvkm/engine/gr/nv35.o
nvkm-y += nvkm/engine/gr/nv40.o
nvkm-y += nvkm/engine/gr/nv50.o
nvkm-y += nvkm/engine/gr/nvc0.o
nvkm-y += nvkm/engine/gr/nvc1.o
nvkm-y += nvkm/engine/gr/nvc4.o
nvkm-y += nvkm/engine/gr/nvc8.o
nvkm-y += nvkm/engine/gr/nvd7.o
nvkm-y += nvkm/engine/gr/nvd9.o
nvkm-y += nvkm/engine/gr/nve4.o
nvkm-y += nvkm/engine/gr/gf100.o
nvkm-y += nvkm/engine/gr/gf108.o
nvkm-y += nvkm/engine/gr/gf104.o
nvkm-y += nvkm/engine/gr/gf110.o
nvkm-y += nvkm/engine/gr/gf117.o
nvkm-y += nvkm/engine/gr/gf119.o
nvkm-y += nvkm/engine/gr/gk104.o
nvkm-y += nvkm/engine/gr/gk20a.o
nvkm-y += nvkm/engine/gr/nvf0.o
nvkm-y += nvkm/engine/gr/gk110.o
nvkm-y += nvkm/engine/gr/gk110b.o
nvkm-y += nvkm/engine/gr/nv108.o
nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gm107.o
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h 0 → 100644
View file @ e3c71eb2
#ifndef __NVKM_GRCTX_NVC0_H__
#define __NVKM_GRCTX_NVC0_H__
#include "gf100.h"
struct gf100_grctx {
struct gf100_gr_priv *priv;
struct gf100_gr_data *data;
struct gf100_gr_mmio *mmio;
int buffer_nr;
u64 buffer[4];
u64 addr;
};
int gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, u32 access);
void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int);
#define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d))
#define mmio_refn(a,b,c,d,e) gf100_grctx_mmio_item((a), (b), (c), (d), (e))
#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
struct gf100_grctx_oclass {
struct nvkm_oclass base;
/* main context generation function */
void (*main)(struct gf100_gr_priv *, struct gf100_grctx *);
/* context-specific modify-on-first-load list generation function */
void (*unkn)(struct gf100_gr_priv *);
/* mmio context data */
const struct gf100_gr_pack *hub;
const struct gf100_gr_pack *gpc;
const struct gf100_gr_pack *zcull;
const struct gf100_gr_pack *tpc;
const struct gf100_gr_pack *ppc;
/* indirect context data, generated with icmds/mthds */
const struct gf100_gr_pack *icmd;
const struct gf100_gr_pack *mthd;
/* bundle circular buffer */
void (*bundle)(struct gf100_grctx *);
u32 bundle_size;
u32 bundle_min_gpm_fifo_depth;
u32 bundle_token_limit;
/* pagepool */
void (*pagepool)(struct gf100_grctx *);
u32 pagepool_size;
/* attribute(/alpha) circular buffer */
void (*attrib)(struct gf100_grctx *);
u32 attrib_nr_max;
u32 attrib_nr;
u32 alpha_nr_max;
u32 alpha_nr;
};
static inline const struct gf100_grctx_oclass *
gf100_grctx_impl(struct gf100_gr_priv *priv)
{
return (void *)nv_engine(priv)->cclass;
}
extern struct nvkm_oclass *gf100_grctx_oclass;
int gf100_grctx_generate(struct gf100_gr_priv *);
void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
void gf100_grctx_generate_bundle(struct gf100_grctx *);
void gf100_grctx_generate_pagepool(struct gf100_grctx *);
void gf100_grctx_generate_attrib(struct gf100_grctx *);
void gf100_grctx_generate_unkn(struct gf100_gr_priv *);
void gf100_grctx_generate_tpcid(struct gf100_gr_priv *);
void gf100_grctx_generate_r406028(struct gf100_gr_priv *);
void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *);
void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *);
void gf100_grctx_generate_r406800(struct gf100_gr_priv *);
extern struct nvkm_oclass *gf108_grctx_oclass;
void gf108_grctx_generate_attrib(struct gf100_grctx *);
void gf108_grctx_generate_unkn(struct gf100_gr_priv *);
extern struct nvkm_oclass *gf104_grctx_oclass;
extern struct nvkm_oclass *gf110_grctx_oclass;
extern struct nvkm_oclass *gf117_grctx_oclass;
void gf117_grctx_generate_attrib(struct gf100_grctx *);
extern struct nvkm_oclass *gf119_grctx_oclass;
extern struct nvkm_oclass *gk104_grctx_oclass;
extern struct nvkm_oclass *gk20a_grctx_oclass;
void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *);
void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
extern struct nvkm_oclass *gk110_grctx_oclass;
extern struct nvkm_oclass *gk110b_grctx_oclass;
extern struct nvkm_oclass *gk208_grctx_oclass;
extern struct nvkm_oclass *gm107_grctx_oclass;
/* context init value lists */
extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];
extern const struct gf100_gr_pack gf100_grctx_pack_mthd[];
extern const struct gf100_gr_init gf100_grctx_init_902d_0[];
extern const struct gf100_gr_init gf100_grctx_init_9039_0[];
extern const struct gf100_gr_init gf100_grctx_init_90c0_0[];
extern const struct gf100_gr_pack gf100_grctx_pack_hub[];
extern const struct gf100_gr_init gf100_grctx_init_main_0[];
extern const struct gf100_gr_init gf100_grctx_init_fe_0[];
extern const struct gf100_gr_init gf100_grctx_init_pri_0[];
extern const struct gf100_gr_init gf100_grctx_init_memfmt_0[];
extern const struct gf100_gr_init gf100_grctx_init_rstr2d_0[];
extern const struct gf100_gr_init gf100_grctx_init_scc_0[];
extern const struct gf100_gr_pack gf100_grctx_pack_gpc[];
extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_0[];
extern const struct gf100_gr_init gf100_grctx_init_prop_0[];
extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_1[];
extern const struct gf100_gr_init gf100_grctx_init_zcull_0[];
extern const struct gf100_gr_init gf100_grctx_init_crstr_0[];
extern const struct gf100_gr_init gf100_grctx_init_gpm_0[];
extern const struct gf100_gr_init gf100_grctx_init_gcc_0[];
extern const struct gf100_gr_pack gf100_grctx_pack_zcull[];
extern const struct gf100_gr_pack gf100_grctx_pack_tpc[];
extern const struct gf100_gr_init gf100_grctx_init_pe_0[];
extern const struct gf100_gr_init gf100_grctx_init_wwdx_0[];
extern const struct gf100_gr_init gf100_grctx_init_mpc_0[];
extern const struct gf100_gr_init gf100_grctx_init_tpccs_0[];
extern const struct gf100_gr_init gf104_grctx_init_tex_0[];
extern const struct gf100_gr_init gf104_grctx_init_l1c_0[];
extern const struct gf100_gr_init gf104_grctx_init_sm_0[];
extern const struct gf100_gr_init gf108_grctx_init_9097_0[];
extern const struct gf100_gr_init gf108_grctx_init_gpm_0[];
extern const struct gf100_gr_init gf108_grctx_init_pe_0[];
extern const struct gf100_gr_init gf108_grctx_init_wwdx_0[];
extern const struct gf100_gr_init gf108_grctx_init_tpccs_0[];
extern const struct gf100_gr_init gf110_grctx_init_9197_0[];
extern const struct gf100_gr_init gf110_grctx_init_9297_0[];
extern const struct gf100_gr_pack gf119_grctx_pack_icmd[];
extern const struct gf100_gr_pack gf119_grctx_pack_mthd[];
extern const struct gf100_gr_init gf119_grctx_init_fe_0[];
extern const struct gf100_gr_init gf119_grctx_init_be_0[];
extern const struct gf100_gr_init gf119_grctx_init_prop_0[];
extern const struct gf100_gr_init gf119_grctx_init_gpc_unk_1[];
extern const struct gf100_gr_init gf119_grctx_init_crstr_0[];
extern const struct gf100_gr_init gf119_grctx_init_sm_0[];
extern const struct gf100_gr_init gf117_grctx_init_pe_0[];
extern const struct gf100_gr_init gf117_grctx_init_wwdx_0[];
extern const struct gf100_gr_init gk104_grctx_init_memfmt_0[];
extern const struct gf100_gr_init gk104_grctx_init_ds_0[];
extern const struct gf100_gr_init gk104_grctx_init_scc_0[];
extern const struct gf100_gr_init gk104_grctx_init_gpm_0[];
extern const struct gf100_gr_init gk104_grctx_init_pes_0[];
extern const struct gf100_gr_pack gk104_grctx_pack_hub[];
extern const struct gf100_gr_pack gk104_grctx_pack_gpc[];
extern const struct gf100_gr_pack gk104_grctx_pack_tpc[];
extern const struct gf100_gr_pack gk104_grctx_pack_ppc[];
extern const struct gf100_gr_pack gk104_grctx_pack_icmd[];
extern const struct gf100_gr_init gk104_grctx_init_a097_0[];
extern const struct gf100_gr_pack gk110_grctx_pack_icmd[];
extern const struct gf100_gr_pack gk110_grctx_pack_mthd[];
extern const struct gf100_gr_pack gk110_grctx_pack_hub[];
extern const struct gf100_gr_init gk110_grctx_init_pri_0[];
extern const struct gf100_gr_init gk110_grctx_init_cwd_0[];
extern const struct gf100_gr_pack gk110_grctx_pack_gpc[];
extern const struct gf100_gr_init gk110_grctx_init_gpc_unk_2[];
extern const struct gf100_gr_init gk110_grctx_init_tex_0[];
extern const struct gf100_gr_init gk110_grctx_init_mpc_0[];
extern const struct gf100_gr_init gk110_grctx_init_l1c_0[];
extern const struct gf100_gr_pack gk110_grctx_pack_ppc[];
extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[];
extern const struct gf100_gr_init gk208_grctx_init_prop_0[];
extern const struct gf100_gr_init gk208_grctx_init_crstr_0[];
#endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
View file @ e3c71eb2
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
const struct nvc0_gr_init
nvc4_grctx_init_tex_0[] = {
const struct gf100_gr_init
gf104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
......@@ -42,16 +41,16 @@ nvc4_grctx_init_tex_0[] = {
{}
};
const struct nvc0_gr_init
nvc4_grctx_init_l1c_0[] = {
const struct gf100_gr_init
gf104_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
const struct nvc0_gr_init
nvc4_grctx_init_sm_0[] = {
const struct gf100_gr_init
gf104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
......@@ -64,15 +63,15 @@ nvc4_grctx_init_sm_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc4_grctx_pack_tpc[] = {
{ nvc0_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
{ nvc0_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc0_grctx_init_tpccs_0 },
{ nvc4_grctx_init_sm_0 },
static const struct gf100_gr_pack
gf104_grctx_pack_tpc[] = {
{ gf100_grctx_init_pe_0 },
{ gf104_grctx_init_tex_0 },
{ gf100_grctx_init_wwdx_0 },
{ gf100_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf100_grctx_init_tpccs_0 },
{ gf104_grctx_init_sm_0 },
{}
};
......@@ -80,30 +79,30 @@ nvc4_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gf104_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub,
.gpc = nvc0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc4_grctx_pack_tpc,
.icmd = nvc0_grctx_pack_icmd,
.mthd = nvc0_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.main = gf100_grctx_generate_main,
.unkn = gf100_grctx_generate_unkn,
.hub = gf100_grctx_pack_hub,
.gpc = gf100_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf104_grctx_pack_tpc,
.icmd = gf100_grctx_pack_icmd,
.mthd = gf100_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvc0_grctx_generate_attrib,
.attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
View file @ e3c71eb2
......@@ -21,15 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxgf100.h"
#include "ctxnvc0.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nvc1_grctx_init_icmd_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -267,14 +268,14 @@ nvc1_grctx_init_icmd_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc1_grctx_pack_icmd[] = {
{ nvc1_grctx_init_icmd_0 },
static const struct gf100_gr_pack
gf108_grctx_pack_icmd[] = {
{ gf108_grctx_init_icmd_0 },
{}
};
const struct nvc0_gr_init
nvc1_grctx_init_9097_0[] = {
const struct gf100_gr_init
gf108_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
......@@ -575,25 +576,25 @@ nvc1_grctx_init_9097_0[] = {
{}
};
static const struct nvc0_gr_init
nvc1_grctx_init_9197_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
static const struct nvc0_gr_pack
nvc1_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc1_grctx_init_9197_0, 0x9197 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvc0_grctx_init_90c0_0, 0x90c0 },
static const struct gf100_gr_pack
gf108_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf108_grctx_init_9197_0, 0x9197 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct nvc0_gr_init
nvc1_grctx_init_ds_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 2, 0x04, 0x00000000 },
......@@ -604,8 +605,8 @@ nvc1_grctx_init_ds_0[] = {
{}
};
static const struct nvc0_gr_init
nvc1_grctx_init_pd_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
......@@ -616,8 +617,8 @@ nvc1_grctx_init_pd_0[] = {
{}
};
static const struct nvc0_gr_init
nvc1_grctx_init_be_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
......@@ -628,22 +629,22 @@ nvc1_grctx_init_be_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc1_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvc0_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvc1_grctx_init_ds_0 },
{ nvc1_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvc1_grctx_init_be_0 },
static const struct gf100_gr_pack
gf108_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf100_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf108_grctx_init_ds_0 },
{ gf108_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf108_grctx_init_be_0 },
{}
};
static const struct nvc0_gr_init
nvc1_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gf108_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
......@@ -655,8 +656,8 @@ nvc1_grctx_init_setup_0[] = {
{}
};
const struct nvc0_gr_init
nvc1_grctx_init_gpm_0[] = {
const struct gf100_gr_init
gf108_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c6c, 1, 0x04, 0x00000001 },
......@@ -665,21 +666,21 @@ nvc1_grctx_init_gpm_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc1_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvc0_grctx_init_prop_0 },
{ nvc0_grctx_init_gpc_unk_1 },
{ nvc1_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nvc0_grctx_init_crstr_0 },
{ nvc1_grctx_init_gpm_0 },
{ nvc0_grctx_init_gcc_0 },
static const struct gf100_gr_pack
gf108_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf100_grctx_init_prop_0 },
{ gf100_grctx_init_gpc_unk_1 },
{ gf108_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gf100_grctx_init_crstr_0 },
{ gf108_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct nvc0_gr_init
nvc1_grctx_init_pe_0[] = {
const struct gf100_gr_init
gf108_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
......@@ -688,8 +689,8 @@ nvc1_grctx_init_pe_0[] = {
{}
};
const struct nvc0_gr_init
nvc1_grctx_init_wwdx_0[] = {
const struct gf100_gr_init
gf108_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
......@@ -702,23 +703,23 @@ nvc1_grctx_init_wwdx_0[] = {
{}
};
const struct nvc0_gr_init
nvc1_grctx_init_tpccs_0[] = {
const struct gf100_gr_init
gf108_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{}
};
static const struct nvc0_gr_pack
nvc1_grctx_pack_tpc[] = {
{ nvc1_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
{ nvc1_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc1_grctx_init_tpccs_0 },
{ nvc4_grctx_init_sm_0 },
static const struct gf100_gr_pack
gf108_grctx_pack_tpc[] = {
{ gf108_grctx_init_pe_0 },
{ gf104_grctx_init_tex_0 },
{ gf108_grctx_init_wwdx_0 },
{ gf100_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf108_grctx_init_tpccs_0 },
{ gf104_grctx_init_sm_0 },
{}
};
......@@ -727,10 +728,10 @@ nvc1_grctx_pack_tpc[] = {
******************************************************************************/
void
nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
gf108_grctx_generate_attrib(struct gf100_grctx *info)
{
struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
struct gf100_gr_priv *priv = info->priv;
const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
......@@ -764,7 +765,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
gf108_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
......@@ -774,30 +775,30 @@ nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
}
struct nouveau_oclass *
nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gf108_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc1),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvc1_grctx_pack_hub,
.gpc = nvc1_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc1_grctx_pack_tpc,
.icmd = nvc1_grctx_pack_icmd,
.mthd = nvc1_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.main = gf100_grctx_generate_main,
.unkn = gf108_grctx_generate_unkn,
.hub = gf108_grctx_pack_hub,
.gpc = gf108_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf108_grctx_pack_tpc,
.icmd = gf108_grctx_pack_icmd,
.mthd = gf108_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvc1_grctx_generate_attrib,
.attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
View file @ e3c71eb2
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nvc8_grctx_init_icmd_0[] = {
static const struct gf100_gr_init
gf110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -268,20 +267,20 @@ nvc8_grctx_init_icmd_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc8_grctx_pack_icmd[] = {
{ nvc8_grctx_init_icmd_0 },
static const struct gf100_gr_pack
gf110_grctx_pack_icmd[] = {
{ gf110_grctx_init_icmd_0 },
{}
};
const struct nvc0_gr_init
nvc8_grctx_init_9197_0[] = {
const struct gf100_gr_init
gf110_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
const struct nvc0_gr_init
nvc8_grctx_init_9297_0[] = {
const struct gf100_gr_init
gf110_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
......@@ -290,19 +289,19 @@ nvc8_grctx_init_9297_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc8_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
{ nvc8_grctx_init_9297_0, 0x9297 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvc0_grctx_init_90c0_0, 0x90c0 },
static const struct gf100_gr_pack
gf110_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf110_grctx_init_9197_0, 0x9197 },
{ gf110_grctx_init_9297_0, 0x9297 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct nvc0_gr_init
nvc8_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gf110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
......@@ -314,16 +313,16 @@ nvc8_grctx_init_setup_0[] = {
{}
};
static const struct nvc0_gr_pack
nvc8_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvc0_grctx_init_prop_0 },
{ nvc0_grctx_init_gpc_unk_1 },
{ nvc8_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nvc0_grctx_init_crstr_0 },
{ nvc0_grctx_init_gpm_0 },
{ nvc0_grctx_init_gcc_0 },
static const struct gf100_gr_pack
gf110_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf100_grctx_init_prop_0 },
{ gf100_grctx_init_gpc_unk_1 },
{ gf110_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gf100_grctx_init_crstr_0 },
{ gf100_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
......@@ -331,30 +330,30 @@ nvc8_grctx_pack_gpc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gf110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc8),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub,
.gpc = nvc8_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc0_grctx_pack_tpc,
.icmd = nvc8_grctx_pack_icmd,
.mthd = nvc8_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.main = gf100_grctx_generate_main,
.unkn = gf100_grctx_generate_unkn,
.hub = gf100_grctx_pack_hub,
.gpc = gf110_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf100_grctx_pack_tpc,
.icmd = gf110_grctx_pack_icmd,
.mthd = gf110_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvc0_grctx_generate_attrib,
.attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
View file @ e3c71eb2
......@@ -21,15 +21,17 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxgf100.h"
#include "ctxnvc0.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nvd7_grctx_init_ds_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
......@@ -41,8 +43,8 @@ nvd7_grctx_init_ds_0[] = {
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_pd_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
......@@ -54,22 +56,22 @@ nvd7_grctx_init_pd_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd7_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvd7_grctx_init_ds_0 },
{ nvd7_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvd9_grctx_init_be_0 },
static const struct gf100_gr_pack
gf117_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf119_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf117_grctx_init_ds_0 },
{ gf117_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf119_grctx_init_be_0 },
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
......@@ -81,29 +83,29 @@ nvd7_grctx_init_setup_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd7_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
{ nvd9_grctx_init_gpc_unk_1 },
{ nvd7_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nvd9_grctx_init_crstr_0 },
{ nvc1_grctx_init_gpm_0 },
{ nvc0_grctx_init_gcc_0 },
static const struct gf100_gr_pack
gf117_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gf117_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gf119_grctx_init_crstr_0 },
{ gf108_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct nvc0_gr_init
nvd7_grctx_init_pe_0[] = {
const struct gf100_gr_init
gf117_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_tex_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
......@@ -116,8 +118,8 @@ nvd7_grctx_init_tex_0[] = {
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_mpc_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
......@@ -127,32 +129,32 @@ nvd7_grctx_init_mpc_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd7_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvd7_grctx_init_tex_0 },
{ nvd7_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvd9_grctx_init_sm_0 },
static const struct gf100_gr_pack
gf117_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gf117_grctx_init_tex_0 },
{ gf117_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf119_grctx_init_sm_0 },
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_pes_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{}
};
static const struct nvc0_gr_init
nvd7_grctx_init_cbm_0[] = {
static const struct gf100_gr_init
gf117_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
{ 0x41bee4, 1, 0x04, 0x03240218 },
{}
};
const struct nvc0_gr_init
nvd7_grctx_init_wwdx_0[] = {
const struct gf100_gr_init
gf117_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
......@@ -165,11 +167,11 @@ nvd7_grctx_init_wwdx_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd7_grctx_pack_ppc[] = {
{ nvd7_grctx_init_pes_0 },
{ nvd7_grctx_init_cbm_0 },
{ nvd7_grctx_init_wwdx_0 },
static const struct gf100_gr_pack
gf117_grctx_pack_ppc[] = {
{ gf117_grctx_init_pes_0 },
{ gf117_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
......@@ -178,10 +180,10 @@ nvd7_grctx_pack_ppc[] = {
******************************************************************************/
void
nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
struct gf100_gr_priv *priv = info->priv;
const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
......@@ -215,18 +217,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
nvc0_gr_mmio(priv, oclass->hub);
nvc0_gr_mmio(priv, oclass->gpc);
nvc0_gr_mmio(priv, oclass->zcull);
nvc0_gr_mmio(priv, oclass->tpc);
nvc0_gr_mmio(priv, oclass->ppc);
gf100_gr_mmio(priv, oclass->hub);
gf100_gr_mmio(priv, oclass->gpc);
gf100_gr_mmio(priv, oclass->zcull);
gf100_gr_mmio(priv, oclass->tpc);
gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
......@@ -235,46 +237,46 @@ nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
oclass->attrib(info);
oclass->unkn(priv);
nvc0_grctx_generate_tpcid(priv);
nvc0_grctx_generate_r406028(priv);
nvc0_grctx_generate_r4060a8(priv);
nve4_grctx_generate_r418bb8(priv);
nvc0_grctx_generate_r406800(priv);
gf100_grctx_generate_tpcid(priv);
gf100_grctx_generate_r406028(priv);
gf100_grctx_generate_r4060a8(priv);
gk104_grctx_generate_r418bb8(priv);
gf100_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
nvc0_gr_icmd(priv, oclass->icmd);
gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
nvc0_gr_mthd(priv, oclass->mthd);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
gf100_gr_mthd(priv, oclass->mthd);
nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
}
struct nouveau_oclass *
nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gf117_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nvd7_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nvd7_grctx_pack_hub,
.gpc = nvd7_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvd7_grctx_pack_tpc,
.ppc = nvd7_grctx_pack_ppc,
.icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.main = gf117_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gf117_grctx_pack_hub,
.gpc = gf117_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf117_grctx_pack_tpc,
.ppc = gf117_grctx_pack_ppc,
.icmd = gf119_grctx_pack_icmd,
.mthd = gf119_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvd7_grctx_generate_attrib,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
View file @ e3c71eb2
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nvd9_grctx_init_icmd_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -270,14 +269,14 @@ nvd9_grctx_init_icmd_0[] = {
{}
};
const struct nvc0_gr_pack
nvd9_grctx_pack_icmd[] = {
{ nvd9_grctx_init_icmd_0 },
const struct gf100_gr_pack
gf119_grctx_pack_icmd[] = {
{ gf119_grctx_init_icmd_0 },
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_90c0_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
......@@ -299,19 +298,19 @@ nvd9_grctx_init_90c0_0[] = {
{}
};
const struct nvc0_gr_pack
nvd9_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
{ nvc8_grctx_init_9297_0, 0x9297 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvd9_grctx_init_90c0_0, 0x90c0 },
const struct gf100_gr_pack
gf119_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf110_grctx_init_9197_0, 0x9197 },
{ gf110_grctx_init_9297_0, 0x9297 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf119_grctx_init_90c0_0, 0x90c0 },
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_fe_0[] = {
const struct gf100_gr_init
gf119_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
......@@ -331,8 +330,8 @@ nvd9_grctx_init_fe_0[] = {
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_ds_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 1, 0x04, 0x08000000 },
......@@ -344,8 +343,8 @@ nvd9_grctx_init_ds_0[] = {
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_pd_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
......@@ -356,8 +355,8 @@ nvd9_grctx_init_pd_0[] = {
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_be_0[] = {
const struct gf100_gr_init
gf119_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
......@@ -368,22 +367,22 @@ nvd9_grctx_init_be_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd9_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvd9_grctx_init_ds_0 },
{ nvd9_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvd9_grctx_init_be_0 },
static const struct gf100_gr_pack
gf119_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf119_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf119_grctx_init_ds_0 },
{ gf119_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf119_grctx_init_be_0 },
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_prop_0[] = {
const struct gf100_gr_init
gf119_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
......@@ -395,8 +394,8 @@ nvd9_grctx_init_prop_0[] = {
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_gpc_unk_1[] = {
const struct gf100_gr_init
gf119_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
......@@ -405,8 +404,8 @@ nvd9_grctx_init_gpc_unk_1[] = {
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
......@@ -418,8 +417,8 @@ nvd9_grctx_init_setup_0[] = {
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_crstr_0[] = {
const struct gf100_gr_init
gf119_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
......@@ -431,21 +430,21 @@ nvd9_grctx_init_crstr_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd9_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
{ nvd9_grctx_init_gpc_unk_1 },
{ nvd9_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nvd9_grctx_init_crstr_0 },
{ nvc1_grctx_init_gpm_0 },
{ nvc0_grctx_init_gcc_0 },
static const struct gf100_gr_pack
gf119_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gf119_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gf119_grctx_init_crstr_0 },
{ gf108_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_tex_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
......@@ -458,8 +457,8 @@ nvd9_grctx_init_tex_0[] = {
{}
};
static const struct nvc0_gr_init
nvd9_grctx_init_mpc_0[] = {
static const struct gf100_gr_init
gf119_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
......@@ -469,8 +468,8 @@ nvd9_grctx_init_mpc_0[] = {
{}
};
const struct nvc0_gr_init
nvd9_grctx_init_sm_0[] = {
const struct gf100_gr_init
gf119_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
......@@ -483,15 +482,15 @@ nvd9_grctx_init_sm_0[] = {
{}
};
static const struct nvc0_gr_pack
nvd9_grctx_pack_tpc[] = {
{ nvc1_grctx_init_pe_0 },
{ nvd9_grctx_init_tex_0 },
{ nvc1_grctx_init_wwdx_0 },
{ nvd9_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc1_grctx_init_tpccs_0 },
{ nvd9_grctx_init_sm_0 },
static const struct gf100_gr_pack
gf119_grctx_pack_tpc[] = {
{ gf108_grctx_init_pe_0 },
{ gf119_grctx_init_tex_0 },
{ gf108_grctx_init_wwdx_0 },
{ gf119_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf108_grctx_init_tpccs_0 },
{ gf119_grctx_init_sm_0 },
{}
};
......@@ -499,30 +498,30 @@ nvd9_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gf119_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd9),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvd9_grctx_pack_hub,
.gpc = nvd9_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvd9_grctx_pack_tpc,
.icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.main = gf100_grctx_generate_main,
.unkn = gf108_grctx_generate_unkn,
.hub = gf119_grctx_pack_hub,
.gpc = gf119_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf119_grctx_pack_tpc,
.icmd = gf119_grctx_pack_icmd,
.mthd = gf119_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvc1_grctx_generate_attrib,
.attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
View file @ e3c71eb2
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nvf0_grctx_init_icmd_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
......@@ -279,14 +278,14 @@ nvf0_grctx_init_icmd_0[] = {
{}
};
const struct nvc0_gr_pack
nvf0_grctx_pack_icmd[] = {
{ nvf0_grctx_init_icmd_0 },
const struct gf100_gr_pack
gk110_grctx_pack_icmd[] = {
{ gk110_grctx_init_icmd_0 },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_a197_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_a197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
......@@ -587,15 +586,15 @@ nvf0_grctx_init_a197_0[] = {
{}
};
const struct nvc0_gr_pack
nvf0_grctx_pack_mthd[] = {
{ nvf0_grctx_init_a197_0, 0xa197 },
{ nvc0_grctx_init_902d_0, 0x902d },
const struct gf100_gr_pack
gk110_grctx_pack_mthd[] = {
{ gk110_grctx_init_a197_0, 0xa197 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_fe_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
......@@ -620,8 +619,8 @@ nvf0_grctx_init_fe_0[] = {
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_pri_0[] = {
const struct gf100_gr_init
gk110_grctx_init_pri_0[] = {
{ 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
......@@ -632,16 +631,16 @@ nvf0_grctx_init_pri_0[] = {
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_cwd_0[] = {
const struct gf100_gr_init
gk110_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{ 0x405b20, 1, 0x04, 0x04000000 },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_pd_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
......@@ -655,8 +654,8 @@ nvf0_grctx_init_pd_0[] = {
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_be_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x12802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
......@@ -668,23 +667,23 @@ nvf0_grctx_init_be_0[] = {
{}
};
const struct nvc0_gr_pack
nvf0_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvf0_grctx_init_fe_0 },
{ nvf0_grctx_init_pri_0 },
{ nve4_grctx_init_memfmt_0 },
{ nve4_grctx_init_ds_0 },
{ nvf0_grctx_init_cwd_0 },
{ nvf0_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nve4_grctx_init_scc_0 },
{ nvf0_grctx_init_be_0 },
const struct gf100_gr_pack
gk110_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gk110_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gk104_grctx_init_ds_0 },
{ gk110_grctx_init_cwd_0 },
{ gk110_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gk110_grctx_init_be_0 },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
......@@ -698,28 +697,28 @@ nvf0_grctx_init_setup_0[] = {
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_gpc_unk_2[] = {
const struct gf100_gr_init
gk110_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_gr_pack
nvf0_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
{ nvd9_grctx_init_gpc_unk_1 },
{ nvf0_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nvd9_grctx_init_crstr_0 },
{ nve4_grctx_init_gpm_0 },
{ nvf0_grctx_init_gpc_unk_2 },
{ nvc0_grctx_init_gcc_0 },
const struct gf100_gr_pack
gk110_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gk110_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gf119_grctx_init_crstr_0 },
{ gk104_grctx_init_gpm_0 },
{ gk110_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_tex_0[] = {
const struct gf100_gr_init
gk110_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
......@@ -733,8 +732,8 @@ nvf0_grctx_init_tex_0[] = {
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_mpc_0[] = {
const struct gf100_gr_init
gk110_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
......@@ -744,15 +743,15 @@ nvf0_grctx_init_mpc_0[] = {
{}
};
const struct nvc0_gr_init
nvf0_grctx_init_l1c_0[] = {
const struct gf100_gr_init
gk110_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_sm_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
......@@ -779,29 +778,29 @@ nvf0_grctx_init_sm_0[] = {
{}
};
static const struct nvc0_gr_pack
nvf0_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ nvf0_grctx_init_sm_0 },
static const struct gf100_gr_pack
gk110_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk110_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk110_grctx_init_sm_0 },
{}
};
static const struct nvc0_gr_init
nvf0_grctx_init_cbm_0[] = {
static const struct gf100_gr_init
gk110_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_gr_pack
nvf0_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ nvf0_grctx_init_cbm_0 },
{ nvd7_grctx_init_wwdx_0 },
const struct gf100_gr_pack
gk110_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gk110_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
......@@ -809,33 +808,33 @@ nvf0_grctx_pack_ppc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gk110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nvf0_grctx_pack_hub,
.gpc = nvf0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvf0_grctx_pack_tpc,
.ppc = nvf0_grctx_pack_ppc,
.icmd = nvf0_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.main = gk104_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk110_grctx_pack_hub,
.gpc = gk110_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk110_grctx_pack_tpc,
.ppc = gk110_grctx_pack_ppc,
.icmd = gk110_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvd7_grctx_generate_attrib,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
View file @ e3c71eb2
......@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
static const struct gf100_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
......@@ -56,12 +55,12 @@ gk110b_grctx_init_sm_0[] = {
{}
};
static const struct nvc0_gr_pack
static const struct gf100_gr_pack
gk110b_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ gf117_grctx_init_pe_0 },
{ gk110_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk110b_grctx_init_sm_0 },
{}
};
......@@ -70,33 +69,33 @@ gk110b_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gk110b_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf1),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nvf0_grctx_pack_hub,
.gpc = nvf0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.main = gk104_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk110_grctx_pack_hub,
.gpc = gk110_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk110b_grctx_pack_tpc,
.ppc = nvf0_grctx_pack_ppc,
.icmd = nvf0_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.ppc = gk110_grctx_pack_ppc,
.icmd = gk110_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvd7_grctx_generate_attrib,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
View file @ e3c71eb2
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxnvc0.h"
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_gr_init
nv108_grctx_init_icmd_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
......@@ -278,14 +277,14 @@ nv108_grctx_init_icmd_0[] = {
{}
};
static const struct nvc0_gr_pack
nv108_grctx_pack_icmd[] = {
{ nv108_grctx_init_icmd_0 },
static const struct gf100_gr_pack
gk208_grctx_pack_icmd[] = {
{ gk208_grctx_init_icmd_0 },
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_fe_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
......@@ -311,8 +310,8 @@ nv108_grctx_init_fe_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_ds_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
......@@ -325,8 +324,8 @@ nv108_grctx_init_ds_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_pd_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
......@@ -340,8 +339,8 @@ nv108_grctx_init_pd_0[] = {
{}
};
const struct nvc0_gr_init
nv108_grctx_init_rstr2d_0[] = {
const struct gf100_gr_init
gk208_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000063 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
......@@ -353,8 +352,8 @@ nv108_grctx_init_rstr2d_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_be_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
......@@ -366,23 +365,23 @@ nv108_grctx_init_be_0[] = {
{}
};
static const struct nvc0_gr_pack
nv108_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nv108_grctx_init_fe_0 },
{ nvf0_grctx_init_pri_0 },
{ nve4_grctx_init_memfmt_0 },
{ nv108_grctx_init_ds_0 },
{ nvf0_grctx_init_cwd_0 },
{ nv108_grctx_init_pd_0 },
{ nv108_grctx_init_rstr2d_0 },
{ nve4_grctx_init_scc_0 },
{ nv108_grctx_init_be_0 },
static const struct gf100_gr_pack
gk208_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gk208_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gk208_grctx_init_ds_0 },
{ gk110_grctx_init_cwd_0 },
{ gk208_grctx_init_pd_0 },
{ gk208_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gk208_grctx_init_be_0 },
{}
};
const struct nvc0_gr_init
nv108_grctx_init_prop_0[] = {
const struct gf100_gr_init
gk208_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38005e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
......@@ -394,8 +393,8 @@ nv108_grctx_init_prop_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_gpc_unk_1[] = {
static const struct gf100_gr_init
gk208_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
......@@ -404,8 +403,8 @@ nv108_grctx_init_gpc_unk_1[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_setup_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
......@@ -419,8 +418,8 @@ nv108_grctx_init_setup_0[] = {
{}
};
const struct nvc0_gr_init
nv108_grctx_init_crstr_0[] = {
const struct gf100_gr_init
gk208_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x0000001e },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
......@@ -432,8 +431,8 @@ nv108_grctx_init_crstr_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_gpm_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
......@@ -443,22 +442,22 @@ nv108_grctx_init_gpm_0[] = {
{}
};
static const struct nvc0_gr_pack
nv108_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nv108_grctx_init_prop_0 },
{ nv108_grctx_init_gpc_unk_1 },
{ nv108_grctx_init_setup_0 },
{ nvc0_grctx_init_zcull_0 },
{ nv108_grctx_init_crstr_0 },
{ nv108_grctx_init_gpm_0 },
{ nvf0_grctx_init_gpc_unk_2 },
{ nvc0_grctx_init_gcc_0 },
static const struct gf100_gr_pack
gk208_grctx_pack_gpc[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gk208_grctx_init_prop_0 },
{ gk208_grctx_init_gpc_unk_1 },
{ gk208_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gk208_grctx_init_crstr_0 },
{ gk208_grctx_init_gpm_0 },
{ gk110_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_tex_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000421 },
......@@ -472,8 +471,8 @@ nv108_grctx_init_tex_0[] = {
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_sm_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
......@@ -500,18 +499,18 @@ nv108_grctx_init_sm_0[] = {
{}
};
static const struct nvc0_gr_pack
nv108_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nv108_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ nv108_grctx_init_sm_0 },
static const struct gf100_gr_pack
gk208_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk208_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk208_grctx_init_sm_0 },
{}
};
static const struct nvc0_gr_init
nv108_grctx_init_cbm_0[] = {
static const struct gf100_gr_init
gk208_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
......@@ -519,11 +518,11 @@ nv108_grctx_init_cbm_0[] = {
{}
};
static const struct nvc0_gr_pack
nv108_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ nv108_grctx_init_cbm_0 },
{ nvd7_grctx_init_wwdx_0 },
static const struct gf100_gr_pack
gk208_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gk208_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
......@@ -531,33 +530,33 @@ nv108_grctx_pack_ppc[] = {
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gk208_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nv108_grctx_pack_hub,
.gpc = nv108_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nv108_grctx_pack_tpc,
.ppc = nv108_grctx_pack_ppc,
.icmd = nv108_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.main = gk104_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk208_grctx_pack_hub,
.gpc = gk208_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk208_grctx_pack_tpc,
.ppc = gk208_grctx_pack_ppc,
.icmd = gk208_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvd7_grctx_generate_attrib,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
View file @ e3c71eb2
......@@ -19,43 +19,42 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
#include "ctxnvc0.h"
static const struct nvc0_gr_pack
static const struct gf100_gr_pack
gk20a_grctx_pack_mthd[] = {
{ nve4_grctx_init_a097_0, 0xa297 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ gk104_grctx_init_a097_0, 0xa297 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
struct nouveau_oclass *
gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
struct nvkm_oclass *
gk20a_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_gr_context_ctor,
.dtor = nvc0_gr_context_dtor,
.init = _nouveau_gr_context_init,
.fini = _nouveau_gr_context_fini,
.rd32 = _nouveau_gr_context_rd32,
.wr32 = _nouveau_gr_context_wr32,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nve4_grctx_pack_hub,
.gpc = nve4_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nve4_grctx_pack_tpc,
.ppc = nve4_grctx_pack_ppc,
.icmd = nve4_grctx_pack_icmd,
.main = gk104_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk104_grctx_pack_hub,
.gpc = gk104_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk104_grctx_pack_tpc,
.ppc = gk104_grctx_pack_ppc,
.icmd = gk104_grctx_pack_icmd,
.mthd = gk20a_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib = nvd7_grctx_generate_attrib,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x240,
.attrib_nr = 0x240,
.alpha_nr_max = 0x648 + (0x648 / 2),
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
View file @ e3c71eb2
......@@ -22,8 +22,6 @@
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
/* NVIDIA context programs handle a number of other conditions which are
* not implemented in our versions. It's not clear why NVIDIA context
* programs have this code, nor whether it's strictly necessary for
......@@ -111,15 +109,16 @@
#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
#include "ctxnv40.h"
#include "nv40.h"
#include "ctx.h"
#include <core/device.h>
/* TODO:
* - get vs count from 0x1540
*/
static int
nv40_gr_vs_count(struct nouveau_device *device)
nv40_gr_vs_count(struct nvkm_device *device)
{
switch (device->chipset) {
......@@ -158,9 +157,9 @@ enum cp_label {
};
static void
nv40_gr_construct_general(struct nouveau_grctx *ctx)
nv40_gr_construct_general(struct nvkm_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x4000a4, 1);
......@@ -264,9 +263,9 @@ nv40_gr_construct_general(struct nouveau_grctx *ctx)
}
static void
nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
nv40_gr_construct_state3d(struct nvkm_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
struct nvkm_device *device = ctx->device;
int i;
if (device->chipset == 0x40) {
......@@ -369,9 +368,9 @@ nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
}
static void
nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x402000, 1);
......@@ -533,7 +532,7 @@ nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
}
static void
nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx)
{
int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
......@@ -548,10 +547,10 @@ nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
}
static void
nv40_gr_construct_shader(struct nouveau_grctx *ctx)
nv40_gr_construct_shader(struct nvkm_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
struct nouveau_gpuobj *obj = ctx->data;
struct nvkm_device *device = ctx->device;
struct nvkm_gpuobj *obj = ctx->data;
int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
int offset, i;
......@@ -579,7 +578,7 @@ nv40_gr_construct_shader(struct nouveau_grctx *ctx)
offset = ctx->ctxvals_pos;
ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
if (ctx->mode != NOUVEAU_GRCTX_VALS)
if (ctx->mode != NVKM_GRCTX_VALS)
return;
offset += 0x0280/4;
......@@ -595,7 +594,7 @@ nv40_gr_construct_shader(struct nouveau_grctx *ctx)
}
static void
nv40_grctx_generate(struct nouveau_grctx *ctx)
nv40_grctx_generate(struct nvkm_grctx *ctx)
{
/* decide whether we're loading/unloading the context */
cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
......@@ -660,22 +659,22 @@ nv40_grctx_generate(struct nouveau_grctx *ctx)
}
void
nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
nv40_grctx_generate(&(struct nouveau_grctx) {
nv40_grctx_generate(&(struct nvkm_grctx) {
.device = device,
.mode = NOUVEAU_GRCTX_VALS,
.mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
nv40_grctx_init(struct nouveau_device *device, u32 *size)
nv40_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
struct nouveau_grctx ctx = {
struct nvkm_grctx ctx = {
.device = device,
.mode = NOUVEAU_GRCTX_PROG,
.mode = NVKM_GRCTX_PROG,
.data = ctxprog,
.ctxprog_max = 256,
};
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
View file @ e3c71eb2
#ifndef __NOUVEAU_GRCTX_H__
#define __NOUVEAU_GRCTX_H__
#ifndef __NVKM_GRCTX_H__
#define __NVKM_GRCTX_H__
#include <core/gpuobj.h>
struct nouveau_grctx {
struct nouveau_device *device;
struct nvkm_grctx {
struct nvkm_device *device;
enum {
NOUVEAU_GRCTX_PROG,
NOUVEAU_GRCTX_VALS
NVKM_GRCTX_PROG,
NVKM_GRCTX_VALS
} mode;
void *data;
......@@ -19,11 +20,11 @@ struct nouveau_grctx {
};
static inline void
cp_out(struct nouveau_grctx *ctx, u32 inst)
cp_out(struct nvkm_grctx *ctx, u32 inst)
{
u32 *ctxprog = ctx->data;
if (ctx->mode != NOUVEAU_GRCTX_PROG)
if (ctx->mode != NVKM_GRCTX_PROG)
return;
BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
......@@ -31,13 +32,13 @@ cp_out(struct nouveau_grctx *ctx, u32 inst)
}
static inline void
cp_lsr(struct nouveau_grctx *ctx, u32 val)
cp_lsr(struct nvkm_grctx *ctx, u32 val)
{
cp_out(ctx, CP_LOAD_SR | val);
}
static inline void
cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length)
{
ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
......@@ -53,12 +54,12 @@ cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
}
static inline void
cp_name(struct nouveau_grctx *ctx, int name)
cp_name(struct nvkm_grctx *ctx, int name)
{
u32 *ctxprog = ctx->data;
int i;
if (ctx->mode != NOUVEAU_GRCTX_PROG)
if (ctx->mode != NVKM_GRCTX_PROG)
return;
ctx->ctxprog_label[name] = ctx->ctxprog_len;
......@@ -73,7 +74,7 @@ cp_name(struct nouveau_grctx *ctx, int name)
}
static inline void
_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
_cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name)
{
int ip = 0;
......@@ -91,21 +92,21 @@ _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
static inline void
_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
_cp_wait(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
}
#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
_cp_set(struct nouveau_grctx *ctx, int flag, int state)
_cp_set(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
}
#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
cp_pos(struct nouveau_grctx *ctx, int offset)
cp_pos(struct nvkm_grctx *ctx, int offset)
{
ctx->ctxvals_pos = offset;
ctx->ctxvals_base = ctx->ctxvals_pos;
......@@ -115,9 +116,9 @@ cp_pos(struct nouveau_grctx *ctx, int offset)
}
static inline void
gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val)
{
if (ctx->mode != NOUVEAU_GRCTX_VALS)
if (ctx->mode != NVKM_GRCTX_VALS)
return;
reg = (reg - 0x00400000) / 4;
......@@ -125,5 +126,4 @@ gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
nv_wo32(ctx->data, reg * 4, val);
}
#endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h deleted 100644 → 0
View file @ 05c7145d
#ifndef __NVKM_GRCTX_NVC0_H__
#define __NVKM_GRCTX_NVC0_H__
#include "nvc0.h"
struct nvc0_grctx {
struct nvc0_gr_priv *priv;
struct nvc0_gr_data *data;
struct nvc0_gr_mmio *mmio;
int buffer_nr;
u64 buffer[4];
u64 addr;
};
int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
struct nvc0_grctx_oclass {
struct nouveau_oclass base;
/* main context generation function */
void (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
/* context-specific modify-on-first-load list generation function */
void (*unkn)(struct nvc0_gr_priv *);
/* mmio context data */
const struct nvc0_gr_pack *hub;
const struct nvc0_gr_pack *gpc;
const struct nvc0_gr_pack *zcull;
const struct nvc0_gr_pack *tpc;
const struct nvc0_gr_pack *ppc;
/* indirect context data, generated with icmds/mthds */
const struct nvc0_gr_pack *icmd;
const struct nvc0_gr_pack *mthd;
/* bundle circular buffer */
void (*bundle)(struct nvc0_grctx *);
u32 bundle_size;
u32 bundle_min_gpm_fifo_depth;
u32 bundle_token_limit;
/* pagepool */
void (*pagepool)(struct nvc0_grctx *);
u32 pagepool_size;
/* attribute(/alpha) circular buffer */
void (*attrib)(struct nvc0_grctx *);
u32 attrib_nr_max;
u32 attrib_nr;
u32 alpha_nr_max;
u32 alpha_nr;
};
static inline const struct nvc0_grctx_oclass *
nvc0_grctx_impl(struct nvc0_gr_priv *priv)
{
return (void *)nv_engine(priv)->cclass;
}
extern struct nouveau_oclass *nvc0_grctx_oclass;
int nvc0_grctx_generate(struct nvc0_gr_priv *);
void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
extern struct nouveau_oclass *nvc1_grctx_oclass;
void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
extern struct nouveau_oclass *nvc4_grctx_oclass;
extern struct nouveau_oclass *nvc8_grctx_oclass;
extern struct nouveau_oclass *nvd7_grctx_oclass;
void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
extern struct nouveau_oclass *nvd9_grctx_oclass;
extern struct nouveau_oclass *nve4_grctx_oclass;
extern struct nouveau_oclass *gk20a_grctx_oclass;
void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_bundle(struct nvc0_grctx *);
void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
extern struct nouveau_oclass *nvf0_grctx_oclass;
extern struct nouveau_oclass *gk110b_grctx_oclass;
extern struct nouveau_oclass *nv108_grctx_oclass;
extern struct nouveau_oclass *gm107_grctx_oclass;
/* context init value lists */
extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
#endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
View file @ e3c71eb2
/* fuc microcode util functions for nvc0 PGRAPH
/* fuc microcode util functions for gf100 PGRAPH
*
* Copyright 2011 Red Hat Inc.
*
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
View file @ e3c71eb2
/* fuc microcode for nvc0 PGRAPH/GPC
/* fuc microcode for gf100 PGRAPH/GPC
*
* Copyright 2011 Red Hat Inc.
*
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
View file @ e3c71eb2
......@@ -27,13 +27,13 @@
#define CHIPSET GF100
#include "macros.fuc"
.section #nvc0_grgpc_data
.section #gf100_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nvc0_grgpc_code
.section #gf100_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
View file @ e3c71eb2
uint32_t nvc0_grgpc_data[] = {
uint32_t gf100_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x00000064,
/* 0x0004: gpc_mmio_list_tail */
......@@ -36,7 +36,7 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000,
};
uint32_t nvc0_grgpc_code[] = {
uint32_t gf100_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
View file @ e3c71eb2
......@@ -27,13 +27,13 @@
#define CHIPSET GF117
#include "macros.fuc"
.section #nvd7_grgpc_data
.section #gf117_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nvd7_grgpc_code
.section #gf117_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
View file @ e3c71eb2
uint32_t nve0_grgpc_data[] = {
uint32_t gf117_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
......@@ -40,7 +40,7 @@ uint32_t nve0_grgpc_data[] = {
0x00000000,
};
uint32_t nve0_grgpc_code[] = {
uint32_t gf117_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
View file @ e3c71eb2
......@@ -27,13 +27,13 @@
#define CHIPSET GK100
#include "macros.fuc"
.section #nve0_grgpc_data
.section #gk104_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nve0_grgpc_code
.section #gk104_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
View file @ e3c71eb2
uint32_t nvd7_grgpc_data[] = {
uint32_t gk104_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
......@@ -40,7 +40,7 @@ uint32_t nvd7_grgpc_data[] = {
0x00000000,
};
uint32_t nvd7_grgpc_code[] = {
uint32_t gk104_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
View file @ e3c71eb2
......@@ -27,13 +27,13 @@
#define CHIPSET GK110
#include "macros.fuc"
.section #nvf0_grgpc_data
.section #gk110_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nvf0_grgpc_code
.section #gk110_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
View file @ e3c71eb2
uint32_t nvf0_grgpc_data[] = {
uint32_t gk110_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
......@@ -40,7 +40,7 @@ uint32_t nvf0_grgpc_data[] = {
0x00000000,
};
uint32_t nvf0_grgpc_code[] = {
uint32_t gk110_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
View file @ e3c71eb2
......@@ -27,13 +27,13 @@
#define CHIPSET GK208
#include "macros.fuc"
.section #nv108_grgpc_data
.section #gk208_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nv108_grgpc_code
.section #gk208_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
View file @ e3c71eb2
uint32_t nv108_grgpc_data[] = {
uint32_t gk208_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
......@@ -40,7 +40,7 @@ uint32_t nv108_grgpc_data[] = {
0x00000000,
};
uint32_t nv108_grgpc_code[] = {
uint32_t gk208_grgpc_code[] = {
0x03140ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
View file @ e3c71eb2
/* fuc microcode for nvc0 PGRAPH/HUB
/* fuc microcode for gf100 PGRAPH/HUB
*
* Copyright 2011 Red Hat Inc.
*
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
View file @ e3c71eb2
......@@ -25,13 +25,13 @@
#define CHIPSET GF100
#include "macros.fuc"
.section #nvc0_grhub_data
.section #gf100_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nvc0_grhub_code
.section #gf100_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
View file @ e3c71eb2
uint32_t nvd7_grhub_data[] = {
uint32_t gf100_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
......@@ -205,7 +205,7 @@ uint32_t nvd7_grhub_data[] = {
0x0417e91c,
};
uint32_t nvd7_grhub_code[] = {
uint32_t gf100_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
View file @ e3c71eb2
......@@ -25,13 +25,13 @@
#define CHIPSET GF117
#include "macros.fuc"
.section #nvd7_grhub_data
.section #gf117_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nvd7_grhub_code
.section #gf117_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
View file @ e3c71eb2
uint32_t nvc0_grhub_data[] = {
uint32_t gf117_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
......@@ -205,7 +205,7 @@ uint32_t nvc0_grhub_data[] = {
0x0417e91c,
};
uint32_t nvc0_grhub_code[] = {
uint32_t gf117_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
View file @ e3c71eb2
......@@ -25,13 +25,13 @@
#define CHIPSET GK100
#include "macros.fuc"
.section #nve0_grhub_data
.section #gk104_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nve0_grhub_code
.section #gk104_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
View file @ e3c71eb2
uint32_t nve0_grhub_data[] = {
uint32_t gk104_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
......@@ -205,7 +205,7 @@ uint32_t nve0_grhub_data[] = {
0x0417e91c,
};
uint32_t nve0_grhub_code[] = {
uint32_t gk104_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
View file @ e3c71eb2
......@@ -25,13 +25,13 @@
#define CHIPSET GK110
#include "macros.fuc"
.section #nvf0_grhub_data
.section #gk110_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nvf0_grhub_code
.section #gk110_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
View file @ e3c71eb2
uint32_t nvf0_grhub_data[] = {
uint32_t gk110_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
......@@ -205,7 +205,7 @@ uint32_t nvf0_grhub_data[] = {
0x0417e91c,
};
uint32_t nvf0_grhub_code[] = {
uint32_t gk110_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
View file @ e3c71eb2
......@@ -25,13 +25,13 @@
#define CHIPSET GK208
#include "macros.fuc"
.section #nv108_grhub_data
.section #gk208_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nv108_grhub_code
.section #gk208_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
View file @ e3c71eb2
uint32_t nv108_grhub_data[] = {
uint32_t gk208_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
......@@ -205,7 +205,7 @@ uint32_t nv108_grhub_data[] = {
0x0417e91c,
};
uint32_t nv108_grhub_code[] = {
uint32_t gk208_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h 0 → 100644
View file @ e3c71eb2
This diff is collapsed.
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
View file @ e3c71eb2
#ifndef __NV50_GR_H__
#define __NV50_GR_H__
#include <engine/gr.h>
struct nvkm_device;
struct nvkm_gpuobj;
int nv50_grctx_init(struct nouveau_device *, u32 *size);
void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
int nv50_grctx_init(struct nvkm_device *, u32 *size);
void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h deleted 100644 → 0
View file @ 05c7145d
This diff is collapsed.
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