Skip to content

L
linux
Commit fb2de489 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Manual merge of ARM assembly code clash. 

I must be crazy, but it looked obvious enough. Check with rmk.
parents 57cf7297 accf94a1
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1861 additions and 375 deletions
arch/arm/boot/compressed/head-xscale.S
View file @ fb2de489
......@@ -42,3 +42,8 @@ __XScale_start:
mov r7, #MACH_TYPE_COTULLA_IDP
#endif
#ifdef CONFIG_MACH_GTWX5715
mov r7, #(MACH_TYPE_GTWX5715 & 0xff)
orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
#endif
arch/arm/configs/omap_h2_1610_defconfig 0 → 100644
View file @ fb2de489
This diff is collapsed.
arch/arm/kernel/asm-offsets.c
View file @ fb2de489
......@@ -59,6 +59,7 @@ int main(void)
DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp));
DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
DEFINE(TI_IWMMXT_STATE, (offsetof(struct thread_info, fpstate)+4)&~7);
......
arch/arm/kernel/calls.S
View file @ fb2de489
......@@ -270,7 +270,7 @@ __syscall_start:
.long sys_remap_file_pages
.long sys_ni_syscall /* sys_set_thread_area */
/* 255 */ .long sys_ni_syscall /* sys_get_thread_area */
.long sys_ni_syscall /* sys_set_tid_address */
.long sys_set_tid_address
.long sys_timer_create
.long sys_timer_settime
.long sys_timer_gettime
......
arch/arm/kernel/entry-armv.S
View file @ fb2de489
This diff is collapsed.
arch/arm/kernel/entry-common.S
View file @ fb2de489
......@@ -137,7 +137,7 @@ ENTRY(vector_swi)
tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
bne __sys_trace
adrsvc al, lr, ret_fast_syscall @ return address
adr lr, ret_fast_syscall @ return address
cmp scno, #NR_syscalls @ check upper syscall limit
ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
......@@ -157,7 +157,7 @@ __sys_trace:
mov r0, #0 @ trace entry [IP = 0]
bl syscall_trace
adrsvc al, lr, __sys_trace_return @ return address
adr lr, __sys_trace_return @ return address
add r1, sp, #S_R0 + S_OFF @ pointer to regs
cmp scno, #NR_syscalls @ check upper syscall limit
ldmccia r1, {r0 - r3} @ have to reload r0 - r3
......@@ -212,7 +212,8 @@ sys_execve_wrapper:
b sys_execve
sys_clone_wapper:
add r2, sp, #S_OFF
add ip, sp, #S_OFF
str ip, [sp, #4]
b sys_clone
sys_sigsuspend_wrapper:
......
arch/arm/kernel/entry-header.S
View file @ fb2de489
......@@ -141,13 +141,6 @@
mov \rd, \rd, lsl #13
.endm
/*
* Like adr, but force SVC mode (if required)
*/
.macro adrsvc, cond, reg, label
adr\cond \reg, \label
.endm
.macro alignment_trap, rbase, rtemp, sym
#ifdef CONFIG_ALIGNMENT_TRAP
#define OFF_CR_ALIGNMENT(x) cr_alignment - x
......
arch/arm/kernel/process.c
View file @ fb2de489
......@@ -352,6 +352,9 @@ copy_thread(int nr, unsigned long clone_flags, unsigned long stack_start,
thread->cpu_context.sp = (unsigned long)childregs;
thread->cpu_context.pc = (unsigned long)ret_from_fork;
if (clone_flags & CLONE_SETTLS)
thread->tp_value = regs->ARM_r3;
return 0;
}
......
arch/arm/kernel/ptrace.c
View file @ fb2de489
......@@ -719,6 +719,11 @@ static int do_ptrace(int request, struct task_struct *child, long addr, long dat
ret = ptrace_setfpregs(child, (void __user *)data);
break;
case PTRACE_GET_THREAD_AREA:
ret = put_user(child->thread_info->tp_value,
(unsigned long __user *) data);
break;
default:
ret = ptrace_request(child, request, addr, data);
break;
......
arch/arm/kernel/sys_arm.c
View file @ fb2de489
......@@ -241,18 +241,14 @@ asmlinkage int sys_fork(struct pt_regs *regs)
/* Clone a task - this clones the calling program thread.
* This is called indirectly via a small wrapper
*/
asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp, struct pt_regs *regs)
asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
int *parent_tidptr, int tls_val, int *child_tidptr,
struct pt_regs *regs)
{
/*
* We don't support SETTID / CLEARTID
*/
if (clone_flags & (CLONE_PARENT_SETTID | CLONE_CHILD_CLEARTID))
return -EINVAL;
if (!newsp)
newsp = regs->ARM_sp;
return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
return do_fork(clone_flags, newsp, regs, 0, parent_tidptr, child_tidptr);
}
asmlinkage int sys_vfork(struct pt_regs *regs)
......
arch/arm/kernel/traps.c
View file @ fb2de489
......@@ -393,6 +393,7 @@ do_cache_op(unsigned long start, unsigned long end, int flags)
#define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE)
asmlinkage int arm_syscall(int no, struct pt_regs *regs)
{
struct thread_info *thread = current_thread_info();
siginfo_t info;
if ((no >> 16) != 0x9f)
......@@ -445,6 +446,17 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
regs->ARM_cpsr |= MODE32_BIT;
return regs->ARM_r0;
case NR(set_tls):
thread->tp_value = regs->ARM_r0;
/*
* Our user accessible TLS ptr is located at 0xffff0ffc.
* On SMP read access to this address must raise a fault
* and be emulated from the data abort handler.
* m
*/
*((unsigned long *)0xffff0ffc) = thread->tp_value;
return 0;
default:
/* Calls 9f00xx..9f07ff are defined to return -ENOSYS
if not implemented, rather than raising SIGILL. This
......
arch/arm/mach-iop3xx/iop321-pci.c
View file @ fb2de489
......@@ -198,22 +198,23 @@ struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
void iop321_init(void)
{
DBG("PCI: Intel 80321 PCI init code.\n");
DBG("\tATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
DBG("\tATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
*IOP321_OMWTVR0,
*IOP321_OIOWTVR);
DBG("\tATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
DBG("\tATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
DBG("\tATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
DBG("\tATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
DBG("\tATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
#if 0
hook_fault_code(4, iop321_pci_abort, SIGBUS, "external abort on linefetch");
hook_fault_code(6, iop321_pci_abort, SIGBUS, "external abort on linefetch");
hook_fault_code(8, iop321_pci_abort, SIGBUS, "external abort on non-linefetch");
hook_fault_code(10, iop321_pci_abort, SIGBUS, "external abort on non-linefetch");
#endif
DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n",
*IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0);
DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n",
*IOP321_IABAR1, *IOP321_IALR1);
DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n",
*IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n",
*IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n",
*IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");
}
arch/arm/mach-iop3xx/iq31244-pci.c
View file @ fb2de489
......@@ -78,13 +78,13 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
res[0].end = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
res[0].start = IOP321_PCI_LOWER_IO_VA;
res[0].end = IOP321_PCI_UPPER_IO_VA;
res[0].name = "IQ31244 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
res[1].end = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
res[1].start = IOP321_PCI_LOWER_MEM_PA;
res[1].end = IOP321_PCI_UPPER_MEM_PA;
res[1].name = "IQ31244 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
......@@ -98,9 +98,6 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
return 1;
}
......
arch/arm/mach-iop3xx/iq80321-pci.c
View file @ fb2de489
......@@ -72,13 +72,13 @@ static int iq80321_setup(int nr, struct pci_sys_data *sys)
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
res[0].end = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
res[0].start = IOP321_PCI_LOWER_IO_VA;
res[0].end = IOP321_PCI_UPPER_IO_VA;
res[0].name = "IQ80321 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
res[1].end = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
res[1].start = IOP321_PCI_LOWER_MEM_PA;
res[1].end = IOP321_PCI_UPPER_MEM_PA;
res[1].name = "IQ80321 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
......@@ -92,9 +92,6 @@ static int iq80321_setup(int nr, struct pci_sys_data *sys)
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
return 1;
}
......
arch/arm/mach-iop3xx/iq80331-pci.c
View file @ fb2de489
......@@ -68,13 +68,13 @@ static int iq80331_setup(int nr, struct pci_sys_data *sys)
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].end = IOP331_PCI_UPPER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].start = IOP331_PCI_LOWER_IO_VA;
res[0].end = IOP331_PCI_UPPER_IO_VA;
res[0].name = "IQ80331 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].end = IOP331_PCI_UPPER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].start = IOP331_PCI_LOWER_MEM_PA;
res[1].end = IOP331_PCI_UPPER_MEM_PA;
res[1].name = "IQ80331 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
......@@ -88,9 +88,6 @@ static int iq80331_setup(int nr, struct pci_sys_data *sys)
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
iop3xx_pcibios_min_io = IOP331_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP331_PCI_LOWER_MEM_VA;
return 1;
}
......
arch/arm/mach-iop3xx/iq80332-pci.c
View file @ fb2de489
......@@ -74,13 +74,13 @@ static int iq80332_setup(int nr, struct pci_sys_data *sys)
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].end = IOP331_PCI_UPPER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].start = IOP331_PCI_LOWER_IO_VA;
res[0].end = IOP331_PCI_UPPER_IO_VA;
res[0].name = "IQ80332 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].end = IOP331_PCI_UPPER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].start = IOP331_PCI_LOWER_MEM_PA;
res[1].end = IOP331_PCI_UPPER_MEM_PA;
res[1].name = "IQ80332 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
......@@ -94,9 +94,6 @@ static int iq80332_setup(int nr, struct pci_sys_data *sys)
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
iop3xx_pcibios_min_io = IOP331_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP331_PCI_LOWER_MEM_VA;
return 1;
}
......
arch/arm/mach-ixp4xx/Kconfig
View file @ fb2de489
......@@ -77,6 +77,24 @@ config CPU_IXP46X
depends on MACH_IXDP465
default y
config MACH_GTWX5715
bool "Gemtek WX5715 (Linksys WRV54G)"
depends on ARCH_IXP4XX
help
This board is currently inside the Linksys WRV54G Gateways.
IXP425 - 266mhz
32mb SDRAM
8mb Flash
miniPCI slot 0 does not have a card connector soldered to the board
miniPCI slot 1 has an ISL3880 802.11g card (Prism54)
npe0 is connected to a Kendin KS8995M Switch (4 ports)
npe1 is the "wan" port
"Console" UART is available on J11 as console
"High Speed" UART is n/c (as far as I can tell)
20 Pin ARM/Xscale JTAG interface on J2
comment "IXP4xx Options"
config IXP4XX_INDIRECT_PCI
......
arch/arm/mach-ixp4xx/Makefile
View file @ fb2de489
......@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o ixdp425-setup.o
obj-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o
obj-$(CONFIG_ARCH_PRPMC1100) += prpmc1100-pci.o prpmc1100-setup.o
obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o gtwx5715-setup.o
arch/arm/mach-ixp4xx/gtwx5715-pci.c 0 → 100644
View file @ fb2de489
/*
* arch/arm/mach-ixp4xx/gtwx5715-pci.c
*
* Gemtek GTWX5715 (Linksys WRV54G) board setup
*
* Copyright (C) 2004 George T. Joseph
* Derived from Coyote
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/gtwx5715.h>
#include <asm/mach/pci.h>
extern void ixp4xx_pci_preinit(void);
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
/*
* The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
* Slot 0 isn't actually populated with a card connector but
* we initialize it anyway in case a future version has the
* slot populated or someone with good soldering skills has
* some free time.
*/
static void gtwx5715_init_gpio(u8 pin, u32 style)
{
gpio_line_config(pin, style | IXP4XX_GPIO_ACTIVE_LOW);
if (style & IXP4XX_GPIO_IN) gpio_line_isr_clear(pin);
}
void __init gtwx5715_pci_preinit(void)
{
gtwx5715_init_gpio(GTWX5715_PCI_SLOT0_INTA_GPIO, IXP4XX_GPIO_IN);
gtwx5715_init_gpio(GTWX5715_PCI_SLOT1_INTA_GPIO, IXP4XX_GPIO_IN);
ixp4xx_pci_preinit();
}
static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int rc;
static int gtwx5715_irqmap
[GTWX5715_PCI_SLOT_COUNT]
[GTWX5715_PCI_INT_PIN_COUNT] = {
{GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ},
{GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ},
};
if (slot >= GTWX5715_PCI_SLOT_COUNT ||
pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1;
else
rc = gtwx5715_irqmap[slot][pin-1];
printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, rc);
return(rc);
}
struct hw_pci gtwx5715_pci __initdata = {
.nr_controllers = 1,
.preinit = gtwx5715_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = gtwx5715_map_irq,
};
int __init gtwx5715_pci_init(void)
{
if (machine_is_gtwx5715())
{
pci_common_init(&gtwx5715_pci);
}
return 0;
}
subsys_initcall(gtwx5715_pci_init);
arch/arm/mach-ixp4xx/gtwx5715-setup.c 0 → 100644
View file @ fb2de489
/*
* arch/arm/mach-ixp4xx/gtwx5715-setup.c
*
* Gemtek GTWX5715 (Linksys WRV54G) board settup
*
* Copyright (C) 2004 George T. Joseph
* Derived from Coyote
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/arch/gtwx5715.h>
/*
* Xscale UART registers are 32 bits wide with only the least
* significant 8 bits having any meaning. From a configuration
* perspective, this means 2 things...
*
* Setting .regshift = 2 so that the standard 16550 registers
* line up on every 4th byte.
*
* Shifting the register start virtual address +3 bytes when
* compiled big-endian. Since register writes are done on a
* single byte basis, if the shift isn't done the driver will
* write the value into the most significant byte of the register,
* which is ignored, instead of the least significant.
*/
#ifdef __ARMEB__
#define REG_OFFSET 3
#else
#define REG_OFFSET 0
#endif
/*
* Only the second or "console" uart is connected on the gtwx5715.
*/
static struct resource gtwx5715_uart_resources[] = {
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IXP4XX_UART2,
.end = IRQ_IXP4XX_UART2,
.flags = IORESOURCE_IRQ,
},
{ },
};
static struct plat_serial8250_port gtwx5715_uart_platform_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device gtwx5715_uart_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = gtwx5715_uart_platform_data,
},
.num_resources = 2,
.resource = gtwx5715_uart_resources,
};
void __init gtwx5715_map_io(void)
{
ixp4xx_map_io();
}
static struct flash_platform_data gtwx5715_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource gtwx5715_flash_resource = {
.start = GTWX5715_FLASH_BASE,
.end = GTWX5715_FLASH_BASE + GTWX5715_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device gtwx5715_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &gtwx5715_flash_data,
},
.num_resources = 1,
.resource = &gtwx5715_flash_resource,
};
static struct platform_device *gtwx5715_devices[] __initdata = {
&gtwx5715_uart_device,
&gtwx5715_flash,
};
static void __init gtwx5715_init(void)
{
platform_add_devices(gtwx5715_devices, ARRAY_SIZE(gtwx5715_devices));
}
MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
MAINTAINER("George Joseph")
BOOT_MEM(PHYS_OFFSET, IXP4XX_UART2_BASE_PHYS,
IXP4XX_UART2_BASE_VIRT)
MAPIO(gtwx5715_map_io)
INITIRQ(ixp4xx_init_irq)
.timer = &ixp4xx_timer,
BOOT_PARAMS(0x0100)
INIT_MACHINE(gtwx5715_init)
MACHINE_END
arch/arm/mach-pxa/corgi.c
View file @ fb2de489
......@@ -77,8 +77,6 @@ static struct platform_device corgiscoop_device = {
* also use scoop functions and this makes the power up/down order
* work correctly.
*/
extern void corgi_ssp_lcdtg_send (u8 adrs, u8 data);
static struct platform_device corgissp_device = {
.name = "corgi-ssp",
.dev = {
......@@ -117,6 +115,18 @@ static struct platform_device corgifb_device = {
};
/*
* Corgi Backlight Device
*/
static struct platform_device corgibl_device = {
.name = "corgi-bl",
.dev = {
.parent = &corgifb_device.dev,
},
.id = -1,
};
/*
* MMC/SD Device
*
......@@ -150,6 +160,10 @@ static int corgi_mci_init(struct device *dev, irqreturn_t (*unused_detect_int)(i
pxa_gpio_mode(CORGI_GPIO_nSD_DETECT | GPIO_IN);
pxa_gpio_mode(CORGI_GPIO_SD_PWR | GPIO_OUT);
init_timer(&mmc_detect.detect_timer);
mmc_detect.detect_timer.function = mmc_detect_callback;
mmc_detect.detect_timer.data = (unsigned long) &mmc_detect;
err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_mmc_detect_int, SA_INTERRUPT,
"MMC card detect", data);
if (err) {
......@@ -157,10 +171,6 @@ static int corgi_mci_init(struct device *dev, irqreturn_t (*unused_detect_int)(i
return -1;
}
init_timer(&mmc_detect.detect_timer);
mmc_detect.detect_timer.function = mmc_detect_callback;
mmc_detect.detect_timer.data = (unsigned long) &mmc_detect;
set_irq_type(CORGI_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE);
return 0;
......@@ -218,6 +228,7 @@ static struct platform_device *devices[] __initdata = {
&corgiscoop_device,
&corgissp_device,
&corgifb_device,
&corgibl_device,
};
static struct sharpsl_flash_param_info sharpsl_flash_param;
......
include/asm-arm/arch-iop3xx/iop321.h
View file @ fb2de489
......@@ -31,7 +31,7 @@
/*
* IOP321 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP321_PCI_IO_WINDOW_SIZE 0x10000
#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP321_PCI_LOWER_IO_PA 0x90000000
#define IOP321_PCI_LOWER_IO_VA 0xfe000000
#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
......@@ -40,14 +40,13 @@
#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1)
//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1)
#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
#define IOP321_PCI_LOWER_MEM_PA 0x80000000
#define IOP321_PCI_LOWER_MEM_VA 0x80000000
#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
#define IOP321_PCI_UPPER_MEM_VA (IOP321_PCI_LOWER_MEM_VA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_VA - IOP321_PCI_LOWER_MEM_BA)
#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
/*
......
include/asm-arm/arch-iop3xx/iop331.h
View file @ fb2de489
......@@ -31,7 +31,7 @@
/*
* IOP331 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP331_PCI_IO_WINDOW_SIZE 0x10000
#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP331_PCI_LOWER_IO_PA 0x90000000
#define IOP331_PCI_LOWER_IO_VA 0xfe000000
#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
......@@ -40,14 +40,14 @@
#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1)
/* this can be 128M if OMWTVR1 is set */
#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
//#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1)
#define IOP331_PCI_LOWER_MEM_PA 0x80000000
#define IOP331_PCI_LOWER_MEM_VA 0x80000000
#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_VA (IOP331_PCI_LOWER_MEM_VA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_VA - IOP331_PCI_LOWER_MEM_BA)
#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
/*
* IOP331 chipset registers
......
include/asm-arm/arch-ixp4xx/gtwx5715.h 0 → 100644
View file @ fb2de489
/*
* include/asm-arm/arch-ixp4xx/gtwx5715.h
*
* Gemtek GTWX5715 Gateway (Linksys WRV54G)
*
* Copyright 2004 (c) George T. Joseph
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#include "irqs.h"
#define GTWX5715_GPIO0 0
#define GTWX5715_GPIO1 1
#define GTWX5715_GPIO2 2
#define GTWX5715_GPIO3 3
#define GTWX5715_GPIO4 4
#define GTWX5715_GPIO5 5
#define GTWX5715_GPIO6 6
#define GTWX5715_GPIO7 7
#define GTWX5715_GPIO8 8
#define GTWX5715_GPIO9 9
#define GTWX5715_GPIO10 10
#define GTWX5715_GPIO11 11
#define GTWX5715_GPIO12 12
#define GTWX5715_GPIO13 13
#define GTWX5715_GPIO14 14
#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0
#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1
#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2
#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3
#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4
#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5
#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6
#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7
#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8
#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9
#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10
#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11
#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12
#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
#define GTWX5715_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define GTWX5715_FLASH_SIZE (0x00800000)
/* PCI controller GPIO to IRQ pin mappings
INTA INTB
SLOT 0 10 11
SLOT 1 11 10
*/
#define GTWX5715_PCI_SLOT0_DEVID 0
#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10
#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11
#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ
#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ
#define GTWX5715_PCI_SLOT1_DEVID 1
#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11
#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10
#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ
#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ
#define GTWX5715_PCI_SLOT_COUNT 2
#define GTWX5715_PCI_INT_PIN_COUNT 2
/*
* GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
* and operate as an SPI type interface. The details of the interface
* are available on Kendin/Micrel's web site.
*/
#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5
#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6
#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7
#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12
/*
* The "reset" button is wired to GPIO 3.
* The GPIO is brought "low" when the button is pushed.
*/
#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3
#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ
/*
* Board Label Front Label
* LED1 Power
* LED2 Wireless-G
* LED3 not populated but could be
* LED4 Internet
* LED5 - LED8 Controlled by KS8995M Switch
* LED9 DMZ
*/
#define GTWX5715_LED1_GPIO GTWX5715_GPIO2
#define GTWX5715_LED2_GPIO GTWX5715_GPIO9
#define GTWX5715_LED3_GPIO GTWX5715_GPIO8
#define GTWX5715_LED4_GPIO GTWX5715_GPIO1
#define GTWX5715_LED9_GPIO GTWX5715_GPIO4
include/asm-arm/arch-ixp4xx/uncompress.h
View file @ fb2de489
......@@ -46,9 +46,9 @@ static void putstr(const char *s)
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
/*
* Coyote only has UART2 connected
* Coyote and gtwx5715 only have UART2 connected
*/
if (machine_is_adi_coyote())
if (machine_is_adi_coyote() || machine_is_gtwx5715())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
......
include/asm-arm/arch-pxa/corgi.h
View file @ fb2de489
......@@ -18,29 +18,30 @@
* Corgi (Non Standard) GPIO Definitions
*/
#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */
#define CORGI_GPIO_AC_IN (1)
#define CORGI_GPIO_WAKEUP (3)
#define CORGI_GPIO_AK_INT (4) /* IR Controller Interrupt */
#define CORGI_GPIO_AC_IN (1) /* Charger Detection */
#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */
#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */
#define CORGI_GPIO_nSD_WP (7)
#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */
#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */
#define CORGI_GPIO_nSD_INT (10)
#define CORGI_GPIO_MAIN_BAT_LOW (11)
#define CORGI_GPIO_BAT_COVER (11)
#define CORGI_GPIO_LED_ORANGE (13)
#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */
#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */
#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */
#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */
#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */
#define CORGI_GPIO_CHRG_FULL (16)
#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */
#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */
#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
#define CORGI_GPIO_MAX1111_CS (20) /* MAX111 Chip Select */
#define CORGI_GPIO_ADC_TEMP_ON (21)
#define CORGI_GPIO_IR_ON (22)
#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */
#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
#define CORGI_GPIO_CHRG_ON (38)
#define CORGI_GPIO_DISCHARGE_ON (42)
#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */
#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */
#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */
#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */
#define CORGI_GPIO_USB_PULLUP (45)
#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */
/*
......@@ -97,6 +98,7 @@
CORGI_SCP_MIC_BIAS )
#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
/*
* Corgi Parameter Area Definitions
*/
......@@ -131,5 +133,18 @@ struct sharpsl_flash_param_info {
unsigned int phadadj;
};
/*
* External Functions
*/
extern unsigned long corgi_ssp_ads7846_putget(unsigned long);
extern unsigned long corgi_ssp_ads7846_get(void);
extern void corgi_ssp_ads7846_put(ulong data);
extern void corgi_ssp_ads7846_lock(void);
extern void corgi_ssp_ads7846_unlock(void);
extern void corgi_ssp_lcdtg_send (u8 adrs, u8 data);
extern void corgi_ssp_blduty_set(int duty);
extern int corgi_ssp_max1111_get(ulong data);
#endif /* __ASM_ARCH_CORGI_H */
include/asm-arm/arch-pxa/pxa-regs.h
View file @ fb2de489
......@@ -1337,7 +1337,7 @@
#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
......
include/asm-arm/elf.h
View file @ fb2de489
......@@ -17,6 +17,7 @@ typedef unsigned long elf_freg_t[3];
#define EM_ARM 40
#define EF_ARM_APCS26 0x08
#define EF_ARM_SOFT_FLOAT 0x200
#define EF_ARM_EABI_MASK 0xFF000000
#define R_ARM_NONE 0
#define R_ARM_PC24 1
......@@ -120,7 +121,8 @@ extern char elf_platform[];
#define SET_PERSONALITY(ex,ibcs2) \
do { \
set_personality(PER_LINUX_32BIT); \
if ((ex).e_flags & EF_ARM_SOFT_FLOAT) \
if (((ex).e_flags & EF_ARM_EABI_MASK) || \
((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
set_thread_flag(TIF_USING_IWMMXT); \
} while (0)
......
include/asm-arm/ptrace.h
View file @ fb2de489
......@@ -19,6 +19,7 @@
#define PTRACE_OLDSETOPTIONS 21
#define PTRACE_GET_THREAD_AREA 22
/*
* PSR bits
*/
......
include/asm-arm/thread_info.h
View file @ fb2de489
......@@ -53,6 +53,7 @@ struct thread_info {
__u32 cpu_domain; /* cpu domain */
struct cpu_context_save cpu_context; /* cpu context */
__u8 used_cp[16]; /* thread used copro */
unsigned long tp_value;
union fp_state fpstate;
union vfp_state vfpstate;
struct restart_block restart_block;
......
include/asm-arm/unistd.h
View file @ fb2de489
......@@ -281,7 +281,7 @@
#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253)
/* 254 for set_thread_area */
/* 255 for get_thread_area */
/* 256 for set_tid_address */
#define __NR_set_tid_address (__NR_SYSCALL_BASE+256)
#define __NR_timer_create (__NR_SYSCALL_BASE+257)
#define __NR_timer_settime (__NR_SYSCALL_BASE+258)
#define __NR_timer_gettime (__NR_SYSCALL_BASE+259)
......@@ -316,6 +316,8 @@
#define __ARM_NR_usr26 (__ARM_NR_BASE+3)
#define __ARM_NR_usr32 (__ARM_NR_BASE+4)
#define __ARM_NR_set_tls (__ARM_NR_BASE+0x800)
#define __sys2(x) #x
#define __sys1(x) __sys2(x)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7