1. 20 Sep, 2019 2 commits
    • Paul Burton's avatar
      MIPS: Detect bad _PFN_SHIFT values · 05d013a0
      Paul Burton authored
      2 recent commits have fixed issues where _PFN_SHIFT grew too large due
      to the introduction of too many pgprot bits in our PTEs for some MIPS32
      kernel configurations. Tracking down such issues can be tricky, so add a
      BUILD_BUG_ON() to help.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      05d013a0
    • Paul Burton's avatar
      MIPS: Disable pte_special() for MIPS32 with RiXi · d1af2ab3
      Paul Burton authored
      Commit 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
      added a _PAGE_SPECIAL bit to the pgprot bits of our PTEs. Unfortunately
      for MIPS32 configurations with RiXi support this pushed the number of
      pgprot bits to 13. Since the PFN field in EntryLo begins at bit 12 this
      results in us shifting the most significant bit of the physical address
      beyond the end of the PTE, leading any mapped access to a physical
      address above 2GB to incorrectly access an address 2GB lower than
      intended.
      
      For now, disable the pte_special() support for MIPS32 configurations
      that support RiXi.
      
      Fixes: 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Dmitry Korotin <dkorotin@wavecomp.com>
      Cc: linux-mips@vger.kernel.org
      d1af2ab3
  2. 06 Sep, 2019 1 commit
  3. 03 Sep, 2019 5 commits
    • Vincenzo Frascino's avatar
      mips: compat: vdso: Use legacy syscalls as fallback · 932bb934
      Vincenzo Frascino authored
      The generic VDSO implementation uses the Y2038 safe clock_gettime64() and
      clock_getres_time64() syscalls as fallback for 32bit VDSO. This breaks
      seccomp setups because these syscalls might be not (yet) allowed.
      
      Implement the 32bit variants which use the legacy syscalls and select the
      variant in the core library.
      
      The 64bit time variants are not removed because they are required for the
      time64 based vdso accessors.
      
      Cc: Paul Burton <paul.burton@mips.com>
      Fixes: 00b26474 ("lib/vdso: Provide generic VDSO implementation")
      Signed-off-by: default avatarVincenzo Frascino <vincenzo.frascino@arm.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-arch@vger.kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kselftest@vger.kernel.org
      Cc: catalin.marinas@arm.com
      Cc: will@kernel.org
      Cc: tglx@linutronix.de
      Cc: salyzyn@android.com
      Cc: 0x7f454c46@gmail.com
      Cc: luto@kernel.org
      932bb934
    • Paul Burton's avatar
      MIPS: Drop Loongson _CACHE_* definitions · 3d77a95f
      Paul Burton authored
      _CACHE_CACHABLE_NONCOHERENT is defined as 3<<_CACHE_SHIFT by default, so
      there's no need to define it as such specifically for Loongson.
      
      _CACHE_CACHABLE_COHERENT is not used anywhere in the kernel, so there's
      no need to define it at all.
      
      Finally the comment found alongside these definitions seems incorrect -
      it suggests that we're defining _CACHE_CACHABLE_NONCOHERENT such that it
      actually provides coherence, but the opposite seems to be true & instead
      the unused _CACHE_CACHABLE_COHERENT is defined as the typically
      incoherent value.
      
      Delete the whole thing, which will have no effect on the compiled code
      anyway.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@vger.kernel.org
      3d77a95f
    • Paul Burton's avatar
      MIPS: tlbex: Remove cpu_has_local_ebase · 775b089a
      Paul Burton authored
      The cpu_has_local_ebase macro is, confusingly, not used to indicate
      whether the EBase register is local to a CPU or not. Instead it
      indicates whether we want to generate the TLB refill exception vector
      each time a CPU is brought online. Doing this makes little sense on any
      system, since we always use the same value for EBase & thus we cannot
      have different TLB refill exception handlers per CPU.
      
      Regenerating the code is not only pointless but also can be actively
      harmful, as commit 8759934e ("MIPS: Build uasm-generated code only
      once to avoid CPU Hotplug problem") described. That commit introduced
      cpu_has_local_ebase to disable the handler regeneration for Loongson
      machines, but this is by no means a Loongson-specific problem.
      
      Remove cpu_has_local_ebase & simply generate the TLB refill handler once
      during boot, just like the rest of the TLB exception handlers.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Cc: linux-mips@vger.kernel.org
      775b089a
    • Paul Burton's avatar
      MIPS: tlbex: Simplify r3k check · 54e8d9f0
      Paul Burton authored
      We already know whether a CPU has r3k style exceptions, including TLB
      exceptions, by checking cpu_has_3kex. Remove the list of CPU types in
      build_tlb_refill_handler() & check cpu_has_3kex instead.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      54e8d9f0
    • Paul Burton's avatar
      MIPS: Select R3k-style TLB in Kconfig · 54746829
      Paul Burton authored
      Currently areas where we need to determine whether the TLB is R3k-style
      need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX.
      
      Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above,
      allowing us to simplify checks for R3k-style TLBs by only checking for
      this new Kconfig option.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Cc: linux-mips@vger.kernel.org
      54746829
  4. 31 Aug, 2019 5 commits
    • Thomas Bogendoerfer's avatar
      MIPS: PCI: refactor ioc3 special handling · 813cafc4
      Thomas Bogendoerfer authored
      Refactored code to only have one ioc3 special handling for read
      access and one for write access.
      Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
      Cc: Lee Jones <lee.jones@linaro.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Cc: Alessandro Zummo <a.zummo@towertech.it>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Evgeniy Polyakov <zbr@ioremap.net>
      Cc: linux-doc@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-input@vger.kernel.org
      Cc: netdev@vger.kernel.org
      Cc: linux-rtc@vger.kernel.org
      Cc: linux-serial@vger.kernel.org
      813cafc4
    • Christoph Hellwig's avatar
      mips: remove ioremap_cachable · 60af0d94
      Christoph Hellwig authored
      Just define ioremap_cache directly.
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Guo Ren <guoren@kernel.org>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Greentime Hu <green.hu@gmail.com>
      Cc: Vincent Chen <deanbo422@gmail.com>
      Cc: Guan Xuetao <gxt@pku.edu.cn>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-arch@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      60af0d94
    • Peter Zijlstra's avatar
      mips/atomic: Fix smp_mb__{before,after}_atomic() · 42344113
      Peter Zijlstra authored
      Recent probing at the Linux Kernel Memory Model uncovered a
      'surprise'. Strongly ordered architectures where the atomic RmW
      primitive implies full memory ordering and
      smp_mb__{before,after}_atomic() are a simple barrier() (such as MIPS
      without WEAK_REORDERING_BEYOND_LLSC) fail for:
      
      	*x = 1;
      	atomic_inc(u);
      	smp_mb__after_atomic();
      	r0 = *y;
      
      Because, while the atomic_inc() implies memory order, it
      (surprisingly) does not provide a compiler barrier. This then allows
      the compiler to re-order like so:
      
      	atomic_inc(u);
      	*x = 1;
      	smp_mb__after_atomic();
      	r0 = *y;
      
      Which the CPU is then allowed to re-order (under TSO rules) like:
      
      	atomic_inc(u);
      	r0 = *y;
      	*x = 1;
      
      And this very much was not intended. Therefore strengthen the atomic
      RmW ops to include a compiler barrier.
      Reported-by: default avatarAndrea Parri <andrea.parri@amarulasolutions.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      42344113
    • Peter Zijlstra's avatar
      mips/atomic: Fix loongson_llsc_mb() wreckage · 1c6c1ca3
      Peter Zijlstra authored
      The comment describing the loongson_llsc_mb() reorder case doesn't
      make any sense what so ever. Instruction re-ordering is not an SMP
      artifact, but rather a CPU local phenomenon. Clarify the comment by
      explaining that these issue cause a coherence fail.
      
      For the branch speculation case; if futex_atomic_cmpxchg_inatomic()
      needs one at the bne branch target, then surely the normal
      __cmpxch_asm() implementation does too. We cannot rely on the
      barriers from cmpxchg() because cmpxchg_local() is implemented with
      the same macro, and branch prediction and speculation are, too, CPU
      local.
      
      Fixes: e02e07e3 ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Huang Pei <huangpei@loongson.cn>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      1c6c1ca3
    • Peter Zijlstra's avatar
      mips/atomic: Fix cmpxchg64 barriers · dfc8d8de
      Peter Zijlstra authored
      There were no memory barriers on the 32bit implementation of
      cmpxchg64(). Fix this.
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      dfc8d8de
  5. 27 Aug, 2019 1 commit
  6. 26 Aug, 2019 4 commits
    • Florian Fainelli's avatar
      firmware: bcm47xx_nvram: Allow COMPILE_TEST · 5699ad0a
      Florian Fainelli authored
      Allow building building the BCM47xx NVRAM and SPROM drivers using
      COMPILE_TEST.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: joe@perches.com
      Cc: Rafał Miłecki <zajec5@gmail.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      5699ad0a
    • Florian Fainelli's avatar
      firmware: bcm47xx_nvram: Correct size_t printf format · feb4eb06
      Florian Fainelli authored
      When building on a 64-bit host, we will get warnings like those:
      
      drivers/firmware/broadcom/bcm47xx_nvram.c:103:3: note: in expansion of macro 'pr_err'
         pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
         ^~~~~~
      drivers/firmware/broadcom/bcm47xx_nvram.c:103:28: note: format string is defined here
         pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
                                 ~^
                                 %li
      
      Use %zu instead for that purpose.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: joe@perches.com
      Cc: Rafał Miłecki <zajec5@gmail.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      feb4eb06
    • Jiaxun Yang's avatar
      MIPS: Treat Loongson Extensions as ASEs · d2f96554
      Jiaxun Yang authored
      Recently, binutils had split Loongson-3 Extensions into four ASEs:
      MMI, CAM, EXT, EXT2. This patch do the samething in kernel and expose
      them in cpuinfo so applications can probe supported ASEs at runtime.
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Yunqiang Su <ysu@wavecomp.com>
      Cc: stable@vger.kernel.org # v4.14+
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      d2f96554
    • Stephen Boyd's avatar
      MIPS: Remove dev_err() usage after platform_get_irq() · 322e577b
      Stephen Boyd authored
      We don't need dev_err() messages when platform_get_irq() fails now that
      platform_get_irq() prints an error message itself when something goes
      wrong. Let's remove these prints with a simple semantic patch.
      
      // <smpl>
      @@
      expression ret;
      struct platform_device *E;
      @@
      
      ret =
      (
      platform_get_irq(E, ...)
      |
      platform_get_irq_byname(E, ...)
      );
      
      if ( \( ret < 0 \| ret <= 0 \) )
      {
      (
      -if (ret != -EPROBE_DEFER)
      -{ ...
      -dev_err(...);
      -... }
      |
      ...
      -dev_err(...);
      )
      ...
      }
      // </smpl>
      
      While we're here, remove braces on if statements that only have one
      statement (manually).
      
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@vger.kernel.org
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-kernel@vger.kernel.org
      322e577b
  7. 24 Aug, 2019 4 commits
    • Antoine Tenart's avatar
      MIPS: dts: mscc: describe the PTP ready interrupt · b4742e66
      Antoine Tenart authored
      This patch adds a description of the PTP ready interrupt, which can be
      triggered when a PTP timestamp is available on an hardware FIFO.
      Signed-off-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: davem@davemloft.net
      Cc: richardcochran@gmail.com
      Cc: alexandre.belloni@bootlin.com
      Cc: UNGLinuxDriver@microchip.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: netdev@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: thomas.petazzoni@bootlin.com
      Cc: allan.nielsen@microchip.com
      b4742e66
    • Antoine Tenart's avatar
      MIPS: dts: mscc: describe the PTP register range · 048dc3ab
      Antoine Tenart authored
      This patch adds one register range within the mscc,vsc7514-switch node,
      to describe the PTP registers.
      Signed-off-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: davem@davemloft.net
      Cc: richardcochran@gmail.com
      Cc: alexandre.belloni@bootlin.com
      Cc: UNGLinuxDriver@microchip.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: netdev@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: thomas.petazzoni@bootlin.com
      Cc: allan.nielsen@microchip.com
      048dc3ab
    • Martin Blumenstingl's avatar
      MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver · ed90302b
      Martin Blumenstingl authored
      The mainline PCIe PHY driver has it's own devicetree node. Update the
      clock alias so the mainline driver finds the clocks.
      
      The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
      and GRX390.
      The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
      GRX390.
      The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
      Lantiq's board support package (called "UGW") names these registers
      "PDI".
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      Cc: john@phrozen.org
      Cc: kishon@ti.com
      Cc: ralf@linux-mips.org
      Cc: robh+dt@kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: hauke@hauke-m.de
      Cc: mark.rutland@arm.com
      Cc: ms@dev.tdt.de
      ed90302b
    • Nick Desaulniers's avatar
      mips: avoid explicit UB in assignment of mips_io_port_base · 12051b31
      Nick Desaulniers authored
      The code in question is modifying a variable declared const through
      pointer manipulation.  Such code is explicitly undefined behavior, and
      is the lone issue preventing malta_defconfig from booting when built
      with Clang:
      
      If an attempt is made to modify an object defined with a const-qualified
      type through use of an lvalue with non-const-qualified type, the
      behavior is undefined.
      
      LLVM is removing such assignments. A simple fix is to not declare
      variables const that you plan on modifying.  Limiting the scope would be
      a better method of preventing unwanted writes to such a variable.
      
      Further, the code in question mentions "compiler bugs" without any links
      to bug reports, so it is difficult to know if the issue is resolved in
      GCC. The patch was authored in 2006, which would have been GCC 4.0.3 or
      4.1.1. The minimal supported version of GCC in the Linux kernel is
      currently 4.6.
      
      For what its worth, there was UB before the commit in question, it just
      added a barrier and got lucky IRT codegen. I don't think there's any
      actual compiler bugs related, just runtime bugs due to UB.
      
      Link: https://github.com/ClangBuiltLinux/linux/issues/610
      Fixes: 966f4406 ("[MIPS] Work around bad code generation for <asm/io.h>.")
      Reported-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Debugged-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Suggested-by: default avatarEli Friedman <efriedma@quicinc.com>
      Signed-off-by: default avatarNick Desaulniers <ndesaulniers@google.com>
      Reviewed-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Tested-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Hassan Naveed <hnaveed@wavecomp.com>
      Cc: Stephen Kitt <steve@sk2.org>
      Cc: Serge Semin <fancer.lancer@gmail.com>
      Cc: Mike Rapoport <rppt@linux.ibm.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Michal Hocko <mhocko@suse.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: clang-built-linux@googlegroups.com
      12051b31
  8. 23 Aug, 2019 10 commits
  9. 19 Aug, 2019 2 commits
  10. 12 Aug, 2019 3 commits
    • Nathan Chancellor's avatar
      MIPS: tlbex: Explicitly cast _PAGE_NO_EXEC to a boolean · c59ae0a1
      Nathan Chancellor authored
      clang warns:
      
      arch/mips/mm/tlbex.c:634:19: error: use of logical '&&' with constant
      operand [-Werror,-Wconstant-logical-operand]
              if (cpu_has_rixi && _PAGE_NO_EXEC) {
                               ^  ~~~~~~~~~~~~~
      arch/mips/mm/tlbex.c:634:19: note: use '&' for a bitwise operation
              if (cpu_has_rixi && _PAGE_NO_EXEC) {
                               ^~
                               &
      arch/mips/mm/tlbex.c:634:19: note: remove constant to silence this
      warning
              if (cpu_has_rixi && _PAGE_NO_EXEC) {
                              ~^~~~~~~~~~~~~~~~
      1 error generated.
      
      Explicitly cast this value to a boolean so that clang understands we
      intend for this to be a non-zero value.
      
      Fixes: 00bf1c69 ("MIPS: tlbex: Avoid placing software PTE bits in Entry* PFN fields")
      Link: https://github.com/ClangBuiltLinux/linux/issues/609Signed-off-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Nick Desaulniers <ndesaulniers@google.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: clang-built-linux@googlegroups.com
      c59ae0a1
    • Nathan Chancellor's avatar
      MIPS/ptrace: Update mips_get_syscall_arg's return type · 077ff3be
      Nathan Chancellor authored
      clang warns:
      
      arch/mips/include/asm/syscall.h:136:3: error: variable 'ret' is
      uninitialized when used here [-Werror,-Wuninitialized]
                      ret |= mips_get_syscall_arg(args++, task, regs, i++);
                      ^~~
      arch/mips/include/asm/syscall.h:129:9: note: initialize the variable
      'ret' to silence this warning
              int ret;
                     ^
                      = 0
      1 error generated.
      
      It's not wrong; however, it's not an issue in practice because ret is
      only assigned to, not read from. ret could just be initialized to zero
      but looking into it further, ret has been unused since it was first
      added in 2012 so just get rid of it and update mips_get_syscall_arg's
      return type since none of the return values are ever checked. If it is
      ever needed again, this commit can be reverted and ret can be properly
      initialized.
      
      Fixes: c0ff3c53 ("MIPS: Enable HAVE_ARCH_TRACEHOOK.")
      Link: https://github.com/ClangBuiltLinux/linux/issues/604Signed-off-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Nick Desaulniers <ndesaulniers@google.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: clang-built-linux@googlegroups.com
      077ff3be
    • Nathan Chancellor's avatar
      MIPS: Don't use bc_false uninitialized in __mm_isBranchInstr · c2869aaf
      Nathan Chancellor authored
      clang warns:
      
      arch/mips/kernel/branch.c:148:8: error: variable 'bc_false' is used
      uninitialized whenever switch case is taken
      [-Werror,-Wsometimes-uninitialized]
                      case mm_bc2t_op:
                           ^~~~~~~~~~
      arch/mips/kernel/branch.c:157:8: note: uninitialized use occurs here
                              if (bc_false)
                                  ^~~~~~~~
      arch/mips/kernel/branch.c:149:8: error: variable 'bc_false' is used
      uninitialized whenever switch case is taken
      [-Werror,-Wsometimes-uninitialized]
                      case mm_bc1t_op:
                           ^~~~~~~~~~
      arch/mips/kernel/branch.c:157:8: note: uninitialized use occurs here
                              if (bc_false)
                                  ^~~~~~~~
      arch/mips/kernel/branch.c:142:4: note: variable 'bc_false' is declared
      here
                              int bc_false = 0;
                              ^
      2 errors generated.
      
      When mm_bc1t_op and mm_bc2t_op are taken, the bc_false initialization
      does not happen, which leads to a garbage value upon use, as illustrated
      below with a small sample program.
      
      $ mipsel-linux-gnu-gcc --version | head -n1
      mipsel-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0
      
      $ clang --version | head -n1
      ClangBuiltLinux clang version 9.0.0 (git://github.com/llvm/llvm-project
      544315b4197034a3be8acd12cba56a75fb1f08dc) (based on LLVM 9.0.0svn)
      
      $ cat test.c
       #include <stdio.h>
      
       static void switch_scoped(int opcode)
       {
      	 switch (opcode) {
      	 case 1:
      	 case 2: {
      		 int bc_false = 0;
      
      		 bc_false = 4;
      	 case 3:
      	 case 4:
      		 printf("\t* switch scoped bc_false = %d\n", bc_false);
      	 }
      	 }
       }
      
       static void function_scoped(int opcode)
       {
      	 int bc_false = 0;
      
      	 switch (opcode) {
      	 case 1:
      	 case 2: {
      		 bc_false = 4;
      	 case 3:
      	 case 4:
      		 printf("\t* function scoped bc_false = %d\n", bc_false);
      	 }
      	 }
       }
      
       int main(void)
       {
      	 int opcode;
      
      	 for (opcode = 1; opcode < 5; opcode++) {
      		 printf("opcode = %d:\n", opcode);
      		 switch_scoped(opcode);
      		 function_scoped(opcode);
      		 printf("\n");
      	 }
      
      	 return 0;
       }
      
      $ mipsel-linux-gnu-gcc -std=gnu89 -static test.c && \
        qemu-mipsel a.out
      opcode = 1:
              * switch scoped bc_false = 4
              * function scoped bc_false = 4
      
      opcode = 2:
              * switch scoped bc_false = 4
              * function scoped bc_false = 4
      
      opcode = 3:
              * switch scoped bc_false = 2147483004
              * function scoped bc_false = 0
      
      opcode = 4:
              * switch scoped bc_false = 2147483004
              * function scoped bc_false = 0
      
      $ clang -std=gnu89 --target=mipsel-linux-gnu -m32 -static test.c && \
        qemu-mipsel a.out
      opcode = 1:
              * switch scoped bc_false = 4
              * function scoped bc_false = 4
      
      opcode = 2:
              * switch scoped bc_false = 4
              * function scoped bc_false = 4
      
      opcode = 3:
              * switch scoped bc_false = 2147483004
              * function scoped bc_false = 0
      
      opcode = 4:
              * switch scoped bc_false = 2147483004
              * function scoped bc_false = 0
      
      Move the definition up so that we get the right behavior and mark it
      __maybe_unused as it will not be used when CONFIG_MIPS_FP_SUPPORT
      isn't enabled.
      
      Fixes: 6a1cc218 ("MIPS: branch: Remove FP branch handling when CONFIG_MIPS_FP_SUPPORT=n")
      Link: https://github.com/ClangBuiltLinux/linux/issues/603Signed-off-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Nick Desaulniers <ndesaulniers@google.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: clang-built-linux@googlegroups.com
      c2869aaf
  11. 08 Aug, 2019 3 commits
    • Paul Burton's avatar
      Merge branch 'ingenic-tcu-v5.4' into mips-next · 75b7329a
      Paul Burton authored
      Merge the Ingenic TCU patchset from the ingenic-tcu-v5.4 branch which
      was created to enable follow-on changes in other subsystems.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      75b7329a
    • Paul Cercueil's avatar
      MIPS: jz4740: Drop obsolete code · abc55228
      Paul Cercueil authored
      The old clocksource/timer platform code is now obsoleted by the newly
      introduced TCU drivers.
      Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
      Tested-by: default avatarMathieu Malaterre <malat@debian.org>
      Tested-by: default avatarArtur Rojek <contact@artur-rojek.eu>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Lee Jones <lee.jones@linaro.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michael Turquette <mturquette@baylibre.com>
      Cc: Stephen Boyd <sboyd@kernel.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-clk@vger.kernel.org
      Cc: od@zcrc.me
      abc55228
    • Paul Cercueil's avatar
      MIPS: GCW0: Reduce system timer and clocksource to 750 kHz · 967a7100
      Paul Cercueil authored
      The default clock (12 MHz) is too fast for the system timer.
      Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
      Tested-by: default avatarMathieu Malaterre <malat@debian.org>
      Tested-by: default avatarArtur Rojek <contact@artur-rojek.eu>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Lee Jones <lee.jones@linaro.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michael Turquette <mturquette@baylibre.com>
      Cc: Stephen Boyd <sboyd@kernel.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-clk@vger.kernel.org
      Cc: od@zcrc.me
      967a7100