- 03 Jan, 2018 39 commits
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Dirk van der Merwe authored
Just before a repr is cleaned up, we give the app a chance to perform some preclean configuration while the reprs pointer is still configured for the app. Signed-off-by:
Dirk van der Merwe <dirk.vandermerwe@netronome.com> Reviewed-by:
Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Dirk van der Merwe authored
Instead of starting up reprs assuming that there is link, only respond to the link state reported by firmware. Furthermore, ensure link is down after repr netdevs are created. Signed-off-by:
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Andrew Lunn authored
Ethernet switch on the MDIO bus have historically performed their own handling of the GPIO reset line. The resent patch to have the MDIO core handle the reset has broken the switch drivers, in that they cannot claim the GPIO. Some switch drivers need more control over the GPIO line than what the MDIO core provides. So restore the historical behaviour by only performing a reset of PHYs, not switches. Fixes: bafbdd52 ("phylib: Add device reset GPIO support") Reported-by:
Sean Wang <sean.wang@mediatek.com> Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:
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David S. Miller authored
Russell King says: ==================== Resolve races in phy accessors This series resolves races with various accesses to PHY registers. The first five patches are necessary before we add phylink support to mvneta, the remaining three are merely cleanups for unobserved races, and hence are less critical. There are two possible classes of races that can occur: where we write to a page register that changes the meaning of a group of other registers, and where we read-modify-write a register. Resolve these races by performing the accesses under the mdio bus lock, ensuring that no other user can access the bus while the series of atomic operations are being performed. These patches have been posted before, and have been modified along the lines of previous feedback: - The third patch was originally reviewed by Florian, but as I've added __phy_modify() to it, I've removed that attributation. - Included generic page-based accessors as suggested last time around. - Since we have the unlocked __phy_modify() in this patch series, it is sensible to include the changes for this to marvell.c - these accessors have to change anyway to avoid deadlocks on the mdio bus lock. I haven't been able to test the at803x.c changes yet beyond compile testing - although I do have systems with an ar8035 PHY. However, they should be straight forward to review. This is targetted for net-next because the races have not been found in existing drivers, but have been observed with phylink integrated into mvneta - that's not to say that the races do not exist today, they are just unobserved (probably through lack of rigorous enough testing.) The race provoking condition is detailed in patch 5. ==================== Signed-off-by: -
Russell King authored
Convert read-modify-write sequences in at803x, Marvell and core phylib to use phy_modify() to ensure safety. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by:
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Russell King authored
Add phy_modify() convenience accessor to complement the mdiobus counterpart. Signed-off-by:
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Russell King authored
For paged accesses to be truely safe, we need to hold the bus lock to prevent anyone else gaining access to the registers while we modify them. The phydev->lock mutex does not do this: userspace via the MII ioctl can still sneak in and read or write any register while we are on a different page, and the suspend/resume methods can be called by a thread different to the thread polling the phy status. Races have been observed with mvneta on SolidRun Clearfog with phylink, particularly between the phylib worker reading the PHYs status, and the thread resuming mvneta, calling phy_start() which then calls through to m88e1121_config_aneg_rgmii_delays(), which tries to read-modify-write the MSCR register: CPU0 CPU1 marvell_read_status_page() marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE) ... m88e1121_config_aneg_rgmii_delays() set_page(MII_MARVELL_MSCR_PAGE) phy_read(phydev, MII_88E1121_PHY_MSCR_REG) marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE); ... phy_write(phydev, MII_88E1121_PHY_MSCR_REG) The result of this is we end up writing the copper page register 21, which causes the copper PHY to be disabled, and the link partner sees the link immediately go down. Solve this by taking the bus lock instead of the PHY lock, thereby preventing other accesses to the PHY while we are accessing other PHY pages. Signed-off-by:
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Russell King authored
Add a set of paged phy register accessors which are inherently safe in their design against other accesses interfering with the paged access. Signed-off-by:
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Russell King authored
Add unlocked versions of the bus accessors, which allows access to the bus with all the tracing. These accessors validate that the bus mutex is held, which is a basic requirement for all mii bus accesses. Also added is a read-modify-write unlocked accessor with the same locking requirements. Signed-off-by:
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Russell King authored
Use unlocked accessors for indirect MMD accesses to clause 22 PHYs. This permits tracing of these accesses. Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Russell King authored
Add unlocked versions of the bus accessors, which allows access to the bus with all the tracing. These accessors validate that the bus mutex is held, which is a basic requirement for all mii bus accesses. Reviewed-by:
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Rahul Lakkireddy authored
Collect TX rate limiting related information in UP CIM logs. Signed-off-by:
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by:
Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by:
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David S. Miller authored
Russell King says: ==================== Convert mvneta to phylink This series converts mvneta to use phylink, which is necessary to support the SFP cages on SolidRun's Clearfog platform. This series just converts mvneta without adding the DT parts - having discussed with Andrew, we believe we're too close to the merge window to submit that patch. I've split the "net: mvneta: convert to phylink" patch up to make it easier to review, and in doing so, spotted some minor corner cases that needed to be fixed along the way. This series depends on the previously merged phylink patches in netdev, along with the recently reviewed 7 patch series "Resolve races in phy accessors" without which, the race described in patch 5 of that series is very evident when triggering a dummy hibernate cycle. This series also illustrates how to convert mvpp2 to phylink. mvneta is the only user of the fixed_phy_update_state() API, and this becomes redundant with the conversion. It would be good to get this series not only reviewed, but also independently tested to ensure that I haven't missed anything - I only have the Clearfog platform to test on, and that doesn't support all the different interface modes that mvneta supports. A particularly interesting side effect of this series is that DSA switches no longer need the "CPU" port and DSA facing MAC ethernet instance to be marked as a fixed link anymore with mvneta - we can use 1000BaseX mode, and the DSA to CPU link will use the 802.3z negotiation to determine the link properties without needing the link parameters to be explicitly stated in DT - that is a subject of a future patch. ==================== Signed-off-by: -
Russell King authored
mvneta is the only user of fixed_phy_update_state(), which has been converted to use phylink instead. Remove fixed_phy_update_state(). Reviewed-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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Russell King authored
Add support for reading the SFF module's EEPROM via the ethtool API. Signed-off-by:
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Russell King authored
The PSC sync change interrupt can fire multiple times while the link is down, which is caused by noise on the serdes lines. As this isn't information we make use of, it's pointless having the interrupt enabled. Signed-off-by:
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Russell King authored
Add support for EEE to mvneta. Signed-off-by:
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Russell King authored
Add support for flow control to mvneta. Signed-off-by:
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Russell King authored
Add support for 1000BaseX link modes. Signed-off-by:
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Russell King authored
Move the port configuration and release of reset to mvneta_mac_config() along side the rest of the port mode configuration. Signed-off-by:
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Russell King authored
Convert mvneta to use phylink, which models the MAC to PHY link in a generic, reusable form. Signed-off-by:
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Russell King authored
Prepare to convert mvneta to phylink by splitting the adjust_link function into its consituent parts. Signed-off-by:
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Russell King authored
The netdev core always ensures that the rtnl lock is held while calling the ndo_open() and ndo_stop() methods. However, the suspend/resume paths do not hold the rtnl lock. phylink will expect the rtnl lock to be held when the MAC driver calls it, so we end up with kernel warnings. Take the lock to ensure that these functions are called in a consistent manner. Signed-off-by:
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David S. Miller authored
Sergei Shtylyov says: ==================== Kill redundant checks in the Renesas Ethernet drivers Here's a set of 2 patches against DaveM's 'net-next.git' repo removing redundant checks in the driver probe() methods. ==================== Signed-off-by: -
Sergei Shtylyov authored
Browsing thru the driver disassembly, I noticed that gcc was able to figure out that the 'ndev' pointer is always non-NULL when calling free_netdev() on the probe() method's error path and thus skip that redundant NULL check... gcc is smart, be like gcc! :-) Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by:
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Sergei Shtylyov authored
Browsing thru the driver disassembly, I noticed that gcc was able to figure out that the 'ndev' pointer is always non-NULL when calling free_netdev() on the probe() method's error path and thus skip that redundant NULL check... gcc is smart, be like gcc! :-) Signed-off-by:
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Himanshu Jha authored
Use vzalloc for allocating zeroed memory and remove unnecessary memset function. Done using Coccinelle. Generated-by: scripts/coccinelle/api/alloc/kzalloc-simple.cocci 0-day tested with no failures. Suggested-by:
Luis R. Rodriguez <mcgrof@kernel.org> Signed-off-by:
Himanshu Jha <himanshujha199640@gmail.com> Signed-off-by:
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Himanshu Jha authored
Use dma_zalloc_coherent for allocating zeroed memory and remove unnecessary memset function. Done using Coccinelle. Generated-by: scripts/coccinelle/api/alloc/kzalloc-simple.cocci 0-day tested with no failures. Suggested-by:
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Himanshu Jha authored
Use dma_zalloc_coherent and vzalloc for allocating zeroed memory and remove unnecessary memset function. Done using Coccinelle. Generated-by: scripts/coccinelle/api/alloc/kzalloc-simple.cocci 0-day tested with no failures. Suggested-by:
Tomer Tayar <Tomer.Tayar@cavium.com> Signed-off-by:
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David S. Miller authored
Florian Fainelli says: ==================== net: stmmac: Couple of debug prints improvements While working on a particular problem, I had to turn on debug prints and found them to be useful, but could deserve some improvements in order to help debug situations. ==================== Signed-off-by: -
Florian Fainelli authored
There is no reason not to allow printing the frame_len/COE value and put that under a check for ETH_FRAME_LEN, drop it so we can see what the descriptor reports. Signed-off-by:
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Florian Fainelli authored
Make the printing of the ring number consistent and properly aligned by padding the ring number with up to 3 zeroes, which covers the maximum ring size. This makes it a lot easier to see outliers in debug prints. Signed-off-by:
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Florian Fainelli authored
We need to make the dsa_legacy_register() stub return 0 in order for dsa_init_module() to successfully register and continue registering the ETH_P_XDSA packet handler. Fixes: 2a93c1a3 ("net: dsa: Allow compiling out legacy support") Reported-by:
Egil Hjelmeland <privat@egil-hjelmeland.no> Signed-off-by:
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David S. Miller authored
Russell King says: ==================== further sfp/phylink updates This series: - cleans up printing of module information - improves the transceiver capability decoding, getting rid of the guessing by connector type, improves direct-attach cable support and adds support for 1G Base-PX and Base-BX10 modules. - cleans up phylink_sfp_module_insert() ==================== Signed-off-by: -
Russell King authored
'mode' is actually constant through phylink_sfp_module_insert(), so remove it and replace it with the enumerated constant. Signed-off-by:
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Russell King authored
Improve the support for direct-attach copper so that we avoid kernel warning messages, and report the appropriate PORT_DA type to userspace. Direct Attach cables can use a number of protocols depending on their range of speeds. Signed-off-by:
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Russell King authored
Add support for decoding the transceiver information for 1000Base-PX and 1000Base-BX10. These use 1000BASE-X protocol. Signed-off-by:
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Russell King authored
Don't try to guess the support mask from the connector type - this is mostly irrelevant to the speeds that the transceiver supports. Signed-off-by:
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Russell King authored
Rather than memcpy()'ing the strings and null terminate them, printf allows non-NULL terminated strings provided the precision is not more than the size of the buffer. Use this form to print the basic module information rather than copying and terminating the strings. Signed-off-by:
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- 02 Jan, 2018 1 commit
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David S. Miller authored
Russell King says: ==================== marvell10g updates This series: - adds MDI/MDIX reporting - adds support for 10/100Mbps half-duplex link modes - adds a comment describing the setup on VF610 ZII boards (where the phy interface mode doesn't change.) - cleans up the phy interace mode switching ==================== Signed-off-by:
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