SOCFPGA has a system manager register block can be accessed by using
the syscon driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: <linux@arm.linux.org.uk>
Signed-off-by: Olof Johansson <olof@lixom.net>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v4:
- Add Acked-by: Mike Turquette

v3:
- Addressed comments from Pavel

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
Signed-off-by: Olof Johansson <olof@lixom.net>

From Alexander Shiyan, this is a series of cleanups of clps711x, movig it
closer to multiplatform and cleans up a bunch of old code.

* clps711x/soc:
  ARM: clps711x: Update defconfig
  ARM: clps711x: Add support for SYSCON driver
  ARM: clps711x: edb7211: Control LCD backlight via PWM
  ARM: clps711x: edb7211: Add support for I2C
  ARM: clps711x: Optimize interrupt handling
  ARM: clps711x: Add clocksource framework
  ARM: clps711x: Replace "arch_initcall" in common code with ".init_early"
  ARM: clps711x: Move specific definitions from hardware.h to boards files
  ARM: clps711x: p720t: Define PLD registers as GPIOs
  ARM: clps711x: autcpu12: Move remaining specific definitions to board file
  ARM: clps711x: autcpu12: Special driver for handling memory is removed
  ARM: clps711x: autcpu12: Add support for NOR flash
  ARM: clps711x: autcpu12: Move LCD DPOT definitions to board file
  ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source
  ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency
  ARM: clps711x: Re-add GPIO support
  GPIO: clps711x: Add DT support
  GPIO: clps711x: Rewrite driver for using generic GPIO code
  + Linux 3.10-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch adds support for SYSCON driver for CLPS711X targets.
At this time there are no users for this driver, but it is will
be used as start point to use in CLPS711X drivers and remove
<mach/xx> dependencies.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch provide control LCD backlight via PWM. GPIO is used
only for switch backlight ON and OFF.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch modify interrupt handler for processing all penging interrupts
at once.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch provide migration to using "mtd-ram" driver instead of using
special driver for handling NVRAM memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

We do not have driver for Up/Down digital potentiometer (DPOT), so
just define pins as GPIOs and export these pins to user.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This clock will be used in audio subsystem. Since audio cannot work
without PLL we should indicate this.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch removes dependency of NEED_MACH_MEMORY_H for CLPS711X-target.
Since some board may have memory holes, define ARCH_HAS_HOLES_MEMORYMODEL
for these boards.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

arch_initcall was been removed from GPIO driver, so this patch
re-add support for GPIO into boards as platform_device.
Since some drivers (spi, nand, etc.) is not support deferred probe,
separate machine init calls is used in board code to make proper
loading sequence.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

Add DT support to the CLPS711X GPIO driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch provides rewritten driver for CLPS711X GPIO which uses
generic GPIO code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-soc-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Renesas ARM-based SoC updates for v3.11

* Increased clock coverage for r8a7740, r8a73a4, r8a7778 and r8a7790
* Use fixed clock ratio for r8a7778
* Always use shmobile_setup_delay for sh73a0
* Add add CPUFreq support for sh73a0
* Check kick bit before changing rate on sh73a0
* Do not overwrite all div4 clock operations on sh73a0

* Cleanup SH_FIXED_RATIO_CLK and SH_FIXED_RATIO_CLK macros
* sh73a0: Use DEFINE_RES_MEM*() everywhere
* r8a7740: Make private clock arrays static
* r8a7778: Correct model number

The last four changes listed above are cleanups. I have included them
in this series as all bar the last one are dependencies of non-cleanup
patches.

* tag 'renesas-soc-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (27 commits)
  ARM: shmobile: sh73a0: div4 clocks must check the kick bit before changing rate
  ARM: shmobile: sh73a0: do not overwrite all div4 clock operations
  ARM: shmobile: sh73a0: Always use shmobile_setup_delay()
  ARM: shmobile: sh73a0: add CPUFreq support
  ARM: shmobile: sh73a0: add support for adjusting CPU frequency
  ARM: shmobile: r8a7790: add TPU PWM support
  ARM: shmobile: r8a7790: Make private clock arrays static
  ARM: shmobile: r8a7790: add div6 clocks
  ARM: shmobile: r8a7790: add div4 clocks
  ARM: shmobile: r8a7790: add main clock
  ARM: shmobile: r8a7778: Register SDHI device
  ARM: shmobile: r8a7778: add SDHI clock support
  ARM: shmobile: r8a7778: use fixed ratio clock
  ARM: shmobile: r8a7779: Add PCIe clocks
  ARM: shmobile: r8a73a4: add div6 clocks
  ARM: shmobile: r8a73a4: add div4 clocks
  ARM: shmobile: r8a73a4: add pll clocks
  ARM: shmobile: r8a73a4: add main clock
  ARM: shmobile: r8a7740: add TPU PWM support
  ARM: shmobile: r8a7740: Add I2C DT clock names
  ...

Conflicts:
	arch/arm/mach-shmobile/Kconfig
	arch/arm/mach-shmobile/include/mach/r8a7778.h
	arch/arm/mach-shmobile/setup-r8a7778.c

Merge tag 'renesas-pinmux-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Renesas ARM based SoC pinmux and GPIO update for v3.11

SH-PFC:
* Entries for INTC external IRQs
* Remove dependency on GPIOLIB
* PFC support for r8a7790 SoC
* Pinmux support for r8a7778 SoC
* Increase pin group and function coverage for sh7372, r8a7740,
  r8a7778, r8a7779 and r8a7790 SoCs
* Use pinctrl mapping on mackerel, ap4evb, armadillo800eva,
  bonito, bockw, lager boards
* Use RCAR_GP_PIN macro in marzen board
* Remove unused GPIOs for sh7372, sh73a0, r8a7740 and r8a7790 SoCs
* Add bias (pull-up/down) pinconf support for r8a7740 SoC
* Add VCCQ support for sh73a0

GPIO car:
* Add RCAR_GP_PIN macro
* Add support for IRQ_TYPE_EDGE_BOTH
* Make the platform data gpio_base field signed

The GPIO changes have been included as the RCAR_GP_PIN and
IRQ_TYPE_EDGE_BOTH changes are depended on by SH-PFC changes.

* tag 'renesas-pinmux-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (132 commits)
  ARM: shmobile: marzen: Use RCAR_GP_PIN macro
  ARM: shmobile: lager: Initialize pinmux
  ARM: shmobile: bockw: add pinctrl support
  ARM: shmobile: kzm9g: tidyup FSI pinctrl
  ARM: shmobile: r8a7740 pinmux platform device cleanup
  ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH
  pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entry
  Revert "ARM: shmobile: Disallow PINCTRL without GPIOLIB"
  pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfaces
  sh-pfc: r8a7778: add MMCIF pin groups
  sh-pfc: r8a7778: add HSPI pin groups
  sh-pfc: r8a7778: add I2C pin groups
  pinctrl: sh-pfc: fix a typo in pfc-r8a7790
  pinctrl: sh-pfc: fix r8a7790 Function Select register tables
  sh-pfc: r8a7778: fixup IRQ1A settings
  sh-pfc: r8a7779: add Ether pin groups
  sh-pfc: r8a7778: add Ether pin groups
  sh-pfc: r8a7778: add VIN pin groups
  sh-pfc: sh73a0: Remove function GPIOs
  sh-pfc: r8a7790: Add TPU pin groups and functions
  ...

From Jason Cooper:
mvebu pcie driver (kirkwood) for v3.11 (round 2)
 - kirkwood
    - migrate Netgear ReadyNAS Duo v2 to pcie DT init

* tag 'pcie_kw-3.11-2' of git://git.infradead.org/users/jcooper/linux:
  arm: kirkwood: NETGEAR ReadyNAS Duo v2 init PCIe via DT
Signed-off-by: Olof Johansson <olof@lixom.net>

From Michal Simek:
arm: Xilinx Zynq clock changes for v3.11

Change Xilinx Zynq DT clock description which reflects logical abstraction
of Zynq's clock tree.

- Refactor PLL driver
- Use new clock controller driver
- Change timer and uart drivers

* tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx:
  clk: zynq: Remove deprecated clock code
  arm: zynq: Migrate platform to clock controller
  clk: zynq: Add clock controller driver
  clk: zynq: Factor out PLL driver
Signed-off-by: Olof Johansson <olof@lixom.net>

According to the datasheet, it is not allowed to change div4 clock rates
if an earlier rate change operation is still in progress, as indicated by
a set kick bit.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU
frequency" intended to replace some clock operations only for the Z-clock,
instead it replaced them for all div4 clocks, since all div4 clocks share
the same copy of clock operations. Fix this by using a separate clock
operations structure for Z-clock.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Break out the function sh73a0_init_delay() that now
gets called both for the C version of the code and
the DT -reference boards. This way we handle both
cases in the same way.

Allows us to boot with TWD only in the kernel configuration
for C board code. TWD is not yet enabled in the case of
DT -reference - this due to a dependency on CCF.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0.
Providing a regulator, a list of OPPs in DT, combined with a virtual
cpufreq-cpu0 platform device and a clock, attached to it is everything,
the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing
such CPUFreq support is kzm9g-reference.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to
the CPU core and SGX. Lower CPU frequencies allow the use of lower supply
voltages and thus reduce power consumption.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as
non-static. Compiling support for both SoCs thus result in a symbol
redefinition. Fix it by defining the arrays as static.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

DIV6 clocks control SD*/MMC* core clocks.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

DIV4 clocks control SD* core clocks.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Almost all clock needs main clock which is basis clock on r8a7790.
This patch adds it, and, set its parent/ratio via MD pin.
It is based on v0.05 datasheet
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This patch adds SDHI register function which needs id number (= 0/1/2)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

R-Car M1 has many clocks, and it is possible to
read/use clock ratio of these clocks from FRQMRx.
But, these ratio are fixed value and
these are decided by MD pin status.

This patch reads MD pin status,
and used fixed ratio clock for other clocks.
It was tesed on bock-w board.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

DIV6 clocks control each core clocks.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>