- 24 Nov, 2014 40 commits
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Sergey Ryazanov authored
Signed-off-by:
Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8242/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Sergey Ryazanov authored
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Sergey Ryazanov authored
Add interrupts initialization and handling routines, also add AHB bus error interrupt handlers for both SoCs families. Signed-off-by:
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Sergey Ryazanov authored
Add basic support for Atheros AR2315+ SoCs: registers definition file and initial setup code. Signed-off-by:
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Sergey Ryazanov authored
Add basic support for Atheros AR5312/AR2312 SoCs: registers definition file and initial setup code. Signed-off-by:
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Sergey Ryazanov authored
Add common code for Atheros AR5312 and Atheros AR2315 SoCs families. Signed-off-by:
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Alban Bedel authored
Fix some value corruptions with values that can't be represented in a signed long. Signed-off-by:
Alban Bedel <albeu@free.fr> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8358/Signed-off-by:
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Alban Bedel authored
When reading u-boot's key=value pairs it should skip the '=' and not use the next argument. Signed-off-by:
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Maciej W. Rozycki authored
Rewrite TURBOchannel error handling to use a common failure path, making sure put_device is called for devices that failed initialization. While at it update printk calls to use pr_err rather than KERN_ERR. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6701/Signed-off-by:
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John Crispin authored
Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8034/Signed-off-by:
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John Crispin authored
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John Crispin authored
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John Crispin authored
This is the small version of MT7620a. Signed-off-by:
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John Crispin authored
Add support for the new MT7621/8 SoC and kill ifdefs. Cleanup some whitespace error while we are at it. Signed-off-by:
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John Crispin authored
Before we had a pinctrl driver we used a custom OF api. This patch converts the soc specific pinmux data to a new set of structs. We also add some new pinmux setings. Signed-off-by:
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John Crispin authored
This is a regression caused by: commit afb46f79 Author: Rob Herring <robh@kernel.org> Date: Wed Apr 2 19:07:24 2014 -0500 mips: ralink: convert to use unflatten_and_copy_device_tree Make the of init code reuse the cmdline defined inside the dts. Signed-off-by:
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John Crispin authored
This patch adds a trivial driver that allows userland to extract the bootrom of a SoC via debugfs. Signed-off-by:
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John Crispin authored
Register the wireless mac clock on rti3883. This is required by the wifi driver. Signed-off-by:
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John Crispin authored
Register the wireleass mac clock on rt2880. This is required by the wifi driver. Signed-off-by:
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John Crispin authored
This function was missing causing make allmod to fail. Signed-off-by:
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John Crispin authored
RT5350 relies on the bootloader setting up the memc correctly. On some boards the setup is incorrect leading to 32 MB being available but only 16 MB being recognized. Allow these boards to manually override the memory range. Signed-off-by:
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John Crispin authored
These SoCs have a special irq that fires upon an illegal memmory access. Signed-off-by:
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John Crispin authored
We already have a read and write wrapper. This adds the missing mask wrapper. Signed-off-by:
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John Crispin authored
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John Crispin authored
Print the PMU and LDO settings on boot. Signed-off-by:
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John Crispin authored
Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Signed-off-by:
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John Crispin authored
The code to detect unfused SoCs was broken due to missing register masking. Signed-off-by:
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John Crispin authored
This is a regression caused by: commit afb46f79 Author: Rob Herring <robh@kernel.org> Date: Wed Apr 2 19:07:24 2014 -0500 mips: ralink: convert to use unflatten_and_copy_device_tree Make the of init code reuse the cmdline defined inside the dts. Signed-off-by:
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John Crispin authored
The eiu init failed as the irq_domain was not yet available. Signed-off-by:
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John Crispin authored
The voice and dsl drivers need to know which SoC we are running on. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/8046/Signed-off-by:
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John Crispin authored
VR9 needs different firmware files for the various phy/soc revisions. Some boards are ship with older and newer SoC revisions. To be able to boot a single image on all versions we need to define both firmware files inside the devicetree. Signed-off-by:
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John Crispin authored
A reboot sometimes lead to a none working phy. An explicit reboot fixes the problem. Signed-off-by:
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John Crispin authored
Add a reset-controller binding for the reset registers found on the lantiq SoC. Signed-off-by:
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John Crispin authored
The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)" which is used to run the voice firmware. This driver allows us to register a chunk of memory that the voice driver can later use for the 2nd core. Signed-off-by:
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Tomeu Vizoso authored
Replacing it with a call to __clk_is_prepared(), which isn't entirely equivalent but in practice shouldn't matter. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8120/Signed-off-by:
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Andrew Bresticker authored
Bump up the rating of the GIC timer so that it gets prioritized over the CP0 timer. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8141/Signed-off-by:
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Andrew Bresticker authored
Use clockevents_config_and_register to setup the clock_event_device based on frequency and min/max ticks instead of doing it ourselves. Signed-off-by:
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Andrew Bresticker authored
Instead of requiring an explicit call to gic_clockevent_init in the SMP startup path, use CPU notifiers to register and enable the GIC timer on CPU startup. Signed-off-by:
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Andrew Bresticker authored
Since the GIC timer IRQ is a percpu IRQ, we can use percpu_dev_id to pass the IRQ handler the correct clock_event_device. Signed-off-by:
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Andrew Bresticker authored
Remove gic_event_handler since it is completely unnecessary. Signed-off-by:
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