- 10 Apr, 2017 2 commits
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Dave Airlie authored
Merge tag 'drm-intel-testing-2017-04-03' of git://anongit.freedesktop.org/git/drm-intel into drm-next Last 4.12 feature pile: GVT updates: - Add mdev attribute group for per-vgpu info - Time slice based vGPU scheduling QoS support (Gao Ping) - Initial KBL support for E3 server (Han Xu) - other misc. i915: - lots and lots of small fixes and improvements all over - refactor fw_domain code (Chris Wilson) - improve guc code (Oscar Mateo) - refactor cursor/sprite code, precompute more for less overhead in the critical path (Ville) - refactor guc/huc fw loading code a bit (Michal Wajdeczko) * tag 'drm-intel-testing-2017-04-03' of git://anongit.freedesktop.org/git/drm-intel: (121 commits) drm/i915: Update DRIVER_DATE to 20170403 drm/i915: Clear gt.active_requests before checking idle status drm/i915/uc: Drop use of MISSING_CASE on trivial enums drm/i915: make a few DDI functions static drm/i915: Combine reset_all_global_seqno() loops into one drm/i915: Remove redudant wait for each engine to idle from seqno wrap drm/i915: Wait for all engines to be idle as part of i915_gem_wait_for_idle() drm/i915: Move retire-requests into i915_gem_wait_for_idle() drm/i915/uc: Move fw path check to fetch_uc_fw() drm/i915/huc: Remove unused intel_huc_fini() drm/i915/uc: Add intel_uc_fw_fini() drm/i915/uc: Add intel_uc_fw_type_repr() drm/i915/uc: Move intel_uc_fw_status_repr() to intel_uc.h drivers: gpu: drm: i915L intel_lpe_audio: Fix kerneldoc comments drm/i915: Suppress busy status for engines if wedged drm/i915: Do request retirement before marking engines as wedged drm/i915: Drop verbose and archaic "ring" from our internal engine names drm/i915: Use a dummy timeline name for a signaled fence drm/i915: Ironlake do_idle_maps w/a may be called w/o struct_mutex drm/i915/guc: Take enable_guc_loading check out of GEM core code ...
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https://github.com/ckhu-mediatek/linux.git-tagsDave Airlie authored
This series is MT2701 DRM support. * 'drm-next-4.12' of https://github.com/ckhu-mediatek/linux.git-tags: drm/mediatek: add support for Mediatek SoC MT2701 drm/mediatek: update DSI sub driver flow for sending commands to panel drm/mediatek: add non-continuous clock mode and EOT packet control drm/mediatek: add dsi transfer function drm/mediatek: add dsi interrupt control drm/mediatek: cleaning up and refine drm/mediatek: update display module connections drm/mediatek: add BLS component drm/mediatek: add shadow register support drm/mediatek: add *driver_data for different hardware settings drm/mediatek: add helpers for coverting from the generic components dt-bindings: display: mediatek: update supported chips
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- 07 Apr, 2017 12 commits
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yt.shen@mediatek.com authored
This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by:
YT Shen <yt.shen@mediatek.com> Acked-by:
CK Hu <ck.hu@mediatek.com>
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yt.shen@mediatek.com authored
This patch update enable/disable flow of DSI module. Original flow works on there is a bridge chip: DSI -> bridge -> panel. In this case: DSI -> panel, the DSI sub driver flow should be updated. We need to initialize DSI first so that we can send commands to panel. Signed-off-by:
shaoming chen <shaoming.chen@mediatek.com> Signed-off-by:
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yt.shen@mediatek.com authored
This patch will update dsi clock control method. 1. dsi non-continue clock mode will enhance antistatic effect for panel 2. EOT packet control will judge whether dsi send end of packet or not by customize Signed-off-by:
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shaoming chen authored
add dsi read/write commands for transfer function Signed-off-by:
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shaoming chen authored
add dsi interrupt control Signed-off-by:
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yt.shen@mediatek.com authored
cleaning up unused define and refine function name and variable Signed-off-by:
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yt.shen@mediatek.com authored
update connections for OVL, RDMA, BLS, DSI Signed-off-by:
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yt.shen@mediatek.com authored
Add BLS component for PWM + GAMMA function Signed-off-by:
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yt.shen@mediatek.com authored
We need to acquire mutex before using the resources, and need to release it after finished. So we don't need to write registers in the blanking period. Signed-off-by:
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yt.shen@mediatek.com authored
There are some hardware settings changed, between MT8173 & MT2701: DISP_OVL address offset changed, color format definition changed. DISP_RDMA fifo size changed. DISP_COLOR offset changed. MIPI_TX pll setting changed. And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod. Signed-off-by:
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yt.shen@mediatek.com authored
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl' define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma' Signed-off-by:
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yt.shen@mediatek.com authored
Add decriptions about supported chips, including MT2701 & MT8173 Signed-off-by:
Rob Herring <robh@kernel.org>
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- 06 Apr, 2017 26 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
A few more things for 4.12: - ttm and amdgpu support for non-contiguous vram CPU mappings - lots of bug fixes and cleanups for vega10 - misc bug fixes and code cleanups [airlied: fix do_div error on 32-bit arm, not sure it's 100% correct] * 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (58 commits) drm/amdgpu: use uintptr_t instead of unsigned long to store pointer drm/amdgpu: Avoid using signed integer to store pointer value drm/amdgpu:invoke new implemented AI MB func drm/amdgpu/vega10:timeout set to equal with VI drm/amdgpu:implement the reset MB func for vega10 drm/amdgpu:fix typo for mxgpu_ai drm/amdgpu:no need to involv HDP in KIQ drm/amdgpu:add PSP block only load_type=PSP (v2) drm/amdgpu/smu9: update to latest driver interface drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start() drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable() drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register() drm/amd/amdgpu: Drop gfx_v9_0_print_status() drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() drm/amdgpu: Move function amdgpu_has_atpx near other similar functions ...
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
Highlights: - Cooling device support from Russell, to allow GPU throttling on system thermal overload. - Explicit fencing support from Philipp, implemented in a similar way to drm/msm. * 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux: drm/etnaviv: submit support for out-fences drm/etnaviv: return GPU fence through the submit structure drm/etnaviv: submit support for in-fences drm/etnaviv: add etnaviv cooling device drm/etnaviv: switch to postclose drm/etnaviv: add lockdep assert to fence allocation
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
imx-drm module/dependency changes - The PRE/PRG drivers added an unwanted DRM dependency to the ipu-v3 driver. Remove the dependency by conditionally disabling PRE/PRG support depending on CONFIG_DRM. - Merge the imx-ipuv3-crtc module into the imxdrm module. There is no reason anymore for a separation between core drm driver and crtc/plane drivers, especially since commit eb8c8880 ("drm/imx: add deferred plane disabling"), which added a dependency on imx-ipuv3-crtc to the imxdrm module. * tag 'imx-drm-next-2017-04-04' of git://git.pengutronix.de/git/pza/linux: drm/imx: merge imx-drm-core and ipuv3-crtc in one module gpu: ipu-v3: don't depend on DRM being enabled
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git://github.com/skeggsb/linuxDave Airlie authored
A bit more for 4.12: - GP10B support - GP107 acceleration support * 'linux-4.12' of git://github.com/skeggsb/linux: (23 commits) drm/nouveau/gpio: enable interrupts on cards with 32 gpio lines drm/nouveau/gr/gp107: initial support drm/nouveau/core: recognise GP10B chipset drm/nouveau/platform: support for probing GP10B drm/nouveau/platform: make VDD regulator optional drm/nouveau/gr: support for GP10B drm/nouveau/ibus: add GP10B support drm/nouveau/mc: add GP10B support drm/nouveau/fb: add GP10B support drm/nouveau/fifo: add GP10B support drm/nouveau/msgqueue: support for GP10B PMU firmware drm/nouveau/secboot: add GP10B support drm/nouveau/secboot/gm20b: specify MC base address as argument drm/nouveau/secboot: start LS firmware in post-run hook drm/nouveau/secboot: let LS post_run hooks return error drm/nouveau/secboot: pass instance to LS firmware loaders drm/nouveau/secboot: allow to boot multiple falcons drm/nouveau/imem/gk20a: Turn instmem lock into mutex drm/nouveau: initial support (display-only) for GP107 drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane state ...
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Xie authored
Signed-off-by:
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Monk Liu authored
Implement the sr-iov mailbox for soc15 asics. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Monk Liu authored
they are lack in the bringup stage, we need them for GPU reset feature. Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Monk Liu authored
1,KIQ won't touch VRAM so no need to involv HDP flush/invalidate at all. 2,According to CP hw designer KIQ better not use any PM4 package lead to wait behave. Signed-off-by:
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Monk Liu authored
SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD macro Signed-off-by:
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Tom St Denis authored
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by:
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Alex Xie authored
Signed-off-by:
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Christian König authored
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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