- 26 Apr, 2016 1 commit
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Jan Glauber authored
Zero-length message support (SMBUS QUICK or i2c) never worked with the Octeon hardware. Disable SMBUS QUICK support and bail out in case of a zero-length i2c request. After this change 'i2c-detect -q' will return an error on Octeon but the previously reported results were wrong anyway. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 25 Apr, 2016 10 commits
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Javier Martinez Canillas authored
The clk_prepare_enable() function can fail so check the return value and propagate the error in case of a failure. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Javier Martinez Canillas authored
The driver not always prints the error code in case of a failure but this information can be very useful for debugging. So let's print if available. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Krzysztof Kozlowski authored
Improve the readability by: - fixing indentation, - switching to proper block comments, - removing spurious blank lines, - checkpatch: void function return statements are not generally useful, - checkpatch: braces {} are not necessary for any arm of this statement, - checkpatch: missing a blank line after declarations. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Krzysztof Kozlowski authored
Cleanup the weird function-level comments and remove obvious documentation for probe/remove. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Krzysztof Kozlowski authored
If during probe() the s3c24xx_i2c_init() failed, the clock was left in disabled but prepared state. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
cn78xx has a different interrupt architecture, so we have to manage the interrupts differently. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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David Daney authored
Use High-Level Controller (HLC) when possible. The HLC can read/write up to 8 bytes and is completely optional. The most important difference of the HLC is that it only requires one interrupt for a transfer (up to 8 bytes) where the low-level read/write requires 2 interrupts plus one interrupt per transferred byte. Since the interrupts are costly using the HLC improves the performance. Also, the HLC provides improved error handling. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> Signed-off-by:
Jan Glauber <jglauber@cavium.com> [wsa: fixed trivial checkpatch warnings] Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Swain authored
Add helper function that reads back a value after writing to make sure the write is finished and use it in octeon_i2c_write_int(). Signed-off-by:
Peter Swain <pswain@cavium.com> Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Switch to the i2c bus recovery framework using generic SCL recovery. If this fails try to reset the hardware. The recovery is triggered during START on timeout of the interrupt or failure to reach the START / repeated-START condition. The START function is moved to xfer and while at it remove the xfer debug message (i2c core already provides a debug message for this). Signed-off-by:
Jan Glauber <jglauber@cavium.com> [wsa: removed one empty line] Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Introduce a function that checks for valid status codes depending on the phase of a transmit or receive. Also add all existing status codes and improve error handling for various states. The Octeon TWSI has an "assert acknowledge" bit (TWSI_CTL_AAK) that is required to be set in master receive mode until the last byte is requested. The state check needs to consider if this bit was set. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 24 Apr, 2016 5 commits
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Axel Lin authored
Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS to simplify the code. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Axel Lin authored
Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS to simplify the code. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Wolfram Sang authored
smatch rightfully says: drivers/i2c/muxes/i2c-mux-pinctrl.c:175 i2c_mux_pinctrl_probe() warn: inconsistent indenting Signed-off-by:
Wolfram Sang <wsa@the-dreams.de> Acked-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Sebastian Andrzej Siewior authored
The lock is taken while reading two registers. On RT the first lock is taken in hard irq where it might sleep and in the threaded irq. The threaded irq runs in oneshot mode so the hard irq does not run until the thread the completes so there is no reason to grab the lock. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> [grygorii.strashko@ti.com: drop locking from isr completely and remove lock field from struct omap_i2c_dev] Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Irina Tirdea authored
Share the ACPI companion for the platform device with the i2c adapter, so that the adapter has access to the properties defined in ACPI tables. Signed-off-by:
Irina Tirdea <irina.tirdea@intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 22 Apr, 2016 15 commits
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Peter Rosin authored
All i2c mux users are using an explicit i2c mux core, drop support for implicit i2c mux cores. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select op to be in terms of the i2c mux core instead of the child adapter. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select op to be in terms of the i2c mux core instead of the child adapter. Tested-by:
Antti Palosaari <crope@iki.fi> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Tested-by:
Antti Palosaari <crope@iki.fi> Reviewed-by:
Antti Palosaari <crope@iki.fi> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Tested-by:
Antti Palosaari <crope@iki.fi> Reviewed-by:
Antti Palosaari <crope@iki.fi> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select op to be in terms of the i2c mux core instead of the child adapter. Tested-by:
Antti Palosaari <crope@iki.fi> Reviewed-by:
Antti Palosaari <crope@iki.fi> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select op to be in terms of the i2c mux core instead of the child adapter. Tested-by:
Antti Palosaari <crope@iki.fi> Reviewed-by:
Antti Palosaari <crope@iki.fi> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Acked-by:
Jonathan Cameron <jic23@kernel.org> Tested-by:
Crestez Dan Leonard <leonard.crestez@intel.com> Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Add a mask to handle the case where not all child adapters should cause a mux deselect to happen, now that there is a common deselect op for all child adapters. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
Allocate an explicit i2c mux core to handle parent and child adapters etc. Update the select/deselect ops to be in terms of the i2c mux core instead of the child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Peter Rosin authored
All i2c-muxes have a parent adapter and one or many child adapters. A mux also has some means of selection. Previously, this was stored per child adapter, but it is only needed to keep track of this per mux. Add an i2c mux core, that keeps track of this consistently. Also add some glue for users of the old interface, which will create one implicit mux core per child adapter. Signed-off-by:
Peter Rosin <peda@axentia.se> Tested-by:
Antti Palosaari <crope@iki.fi> Tested-by:
Crestez Dan Leonard <leonard.crestez@intel.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 16 Apr, 2016 2 commits
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Bartosz Golaszewski authored
We cannot expect msleep(1) to actually sleep for a period shorter than 20 ms. Replace all calls to msleep() with usleep_range(). Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Bartosz Golaszewski authored
The second check for I2C_FUNC_I2C is reduntant, so remove it. Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> [wsa: reworded commit message] Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 14 Apr, 2016 4 commits
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David Wu authored
Switch to the new generic functions: i2c_parse_fw_timings(). Signed-off-by:
David Wu <david.wu@rock-chips.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Remove superfluous check and stray newline. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Add helper functions for control, data and status register access. This simplifies the code and makes the purpose of the register access clearer. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Rename the [read|write]_sw functions to make it clearer they access the TWSI registers. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 13 Apr, 2016 2 commits
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Jan Glauber authored
No functional change, just moving the functions upward in preparation of improving the recovery. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Jan Glauber authored
Convert the adapter timeout to 2 ms independently of depending on CONFIG_HZ. CONFIG_HZ is 100 for MIPS Cavium-Octeon so the timeout value is not changed. Also set retries to 5 to improve robustness. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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- 12 Apr, 2016 1 commit
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Shardar Shariff Md authored
Enable multi-master mode in I2C_CNFG reg based on hw features. Using single/multi-master mode bit introduced for Tegra210, whereas multi-master mode is enabled by default in HW for T124 and earlier Tegra SOC. Enabling this bit doesn't explicitly start treating the bus has having multiple masters, but will start checking for arbitration lost and reporting when it occurs. The Tegra210 I2C controller supports single/multi master mode. Add chipdata for Tegra210 and its compatibility string so that Tegra210 will select data that enables multi master mode correctly. Do below prerequisites for multi-master bus if "multi-master" dt property entry is added. 1. Enable 1st level clock always set. 2. Disable 2nd level clock gating (slcg which is supported from T124 SOC and later chips) Signed-off-by:
Shardar Shariff Md <smohammed@nvidia.com> Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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