- 07 Nov, 2014 40 commits
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Ville Syrjälä authored
We need the HPLL frequency when calculating cdclk. Currently we read that out from the hardware every single time, which isn't going to fly very well if the device is runtime suspended. So cache the HPLL frequency in dev_priv and use the cached value. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Mika Kuoppala authored
This reverts commit 5cb13c07. While the relevance for WaRsDontPollForAckOnClearingFWBits is under investigation, revert this as regression. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684Tested-by:
Tested-by: lu hua <huax.lu@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: S, Deepak <deepak.s@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
This simplifies the code quite a bit compared to iterating over all rings during the ring interrupt. Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip struct is only accessed in two places. The first is when the flip is queued and the other when the mmio writes are done. Since a flip cannot be queued while there is a pending flip, the two paths shouldn't ever run in parallel. We might need to revisit that if support for replacing flips is implemented though. v2: Don't hold dev->struct_mutext while waiting (Chris) v3: Make the wait uninterruptable (Chris) Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ander Conselvan de Oliveira authored
So that it can be used by the flip code to wait for rendering without holding any locks. Signed-off-by:
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Ville Syrjälä authored
We may need to access various hardware bits in the .global_resources() hook, so move the call to occur after enabling all the newly required power wells, but before disabling all the now unneeded wells. This should guarantee that we have all the sufficient hardware resources available during the .global_resources() call. And if not, any additional resources must be explicitly acquired by the .global_resorces() hook. For instance on VLV/CHV we need to access the gunit mailbox so that we can talk to punit/cck over sideband. In addition some PFI credit reprogramming may need to be addes as well, which may require the disp2d well. This should also make the power domain refcounts consistent on platforms which don't have a .global_resource() hook since now they too will call modeset_update_crtc_power_domains() which will drop the init power. Previously init power was just left enabled for such platforms. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
v2: include the section in the drm docbook. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Jani Nikula authored
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Jani Nikula authored
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Jani Nikula authored
This not based on any documentation... Signed-off-by:
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Jani Nikula authored
As per spec, and similar to DDI. Signed-off-by:
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Jani Nikula authored
Add support for disabling the audio codec on vlv/chv/gen5-7, similar to hsw/bdw. Signed-off-by:
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Jani Nikula authored
Similar to the hsw/bdw enable sequence rewrite. v3: replace vblank wait with a comment v4: expand the comment on what should be done with the vblank wait Signed-off-by:
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Zhe Wang authored
Configure and enable RC6 for Gen9. v2: Rebase on top of BDW rc6 support (Damien) Reviewed-by:
Zhe Wang <zhe1.wang@intel.com> Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Zhe Wang authored
Implement common forcewake functions shared by Gen9 features. v2: Make the focewake_{get,put} functions static (Mika) Small coding style fix in the function definition (Damien) Reviewed-by: -
Damien Lespiau authored
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Damien Lespiau authored
When we write new values for the DDB allocation and WM parameters, we now need to trigger the double buffer update for the pipe to take the new configuration into account. As the DDB is a global resource shared between planes, enabling or disabling one plane will result in changes for all planes that are currently in use, thus the need write PLANE_SURF/CUR_BASE for more than the plane we're touching. v2: Don't wait for pipes that are off v3: Split the staging results structure to not exceed the 1Kb stack allocation in skl_update_wm() v4: Rework and document the algorithm after Ville found that it was all wrong. Reviewed-by: -
Damien Lespiau authored
To correctly flush the new DDB allocation we need to know about the pipe allocation layout inside the DDB in order to sequence the re-allocation to not cause a newly allocated pipe to fetch from a space that was previously allocated to another pipe. This patch preserves the per-pipe (start,end) allocation to be used in the flush. Reviewed-by:
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Damien Lespiau authored
We can reduce the indentation level by continuing early. Reviewed-by:
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Damien Lespiau authored
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Damien Lespiau authored
The transition WMs code was doing a shortcut and the values were copied from the WM0 ones at compute_wm_results() time. Going forward, we want to compute them like the other WMs and resolve their final register values in the same way as well. This patch does just that and isolate the transtion WM compute code in skl_compute_transition_wm() while skl_compute_wm_results() takes care of the register values. We also take the opportunity to disable the transition WMs for now. We've noticed underruns and they seem to be the culprit. Reviewed-by:
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Damien Lespiau authored
The DDB allocation code managed to split in two the compute functions. Bring back skl_compute_transition_wm() and skl_compute_linetime_wm() with their little friends. Reviewed-by:
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Damien Lespiau authored
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Damien Lespiau authored
To align with the ilk WM code and because it makes sense to test against the upper bounds as soon as possible on variables that are bigger than the number of bits in the register, let's move the maximum checks from skl_compute_wm_results() to skl_compute_plane_wm(). v2: Leave the result values to 0 when overflowing the limits (Ville) Use 32 bits intermediate variables (Damien) Instead of using the 16 and 8 bits space we have in the result structure, use 32 bits local variables until we're sure they fit into the constraints. Suggested-by: -
Damien Lespiau authored
What we're talking about here is the DDB allocation (in blocks). That's more descriptive than 'max_page_buff_alloc'. Reviewed-by:
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Damien Lespiau authored
Ville suggested that we should use the same semantics as C arrays to reduce the number of those pesky +1/-1 in the allocation code. This patch leaves the debugfs file as is, showing the internal DDB allocation structure, not the values written in the registers. v2: Remove the test on ->end in skl_ddb_entry_size() (Ville) Reviewed-by:
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Damien Lespiau authored
v2: Don't check DDB on pre-SKL platforms Don't check DDB state on disabled pipes v3: Squash "Expose skl_ddb_get_hw_state()" Reviewed-by: -
Damien Lespiau authored
v2: minor conflict in i915_debugfs.c v3: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v4: minor conflict in the i915_debugfs_files array v5: minor conflict in the i915_debugfs_files array Reviewed-by: -
Damien Lespiau authored
v2: Use the gen >= 9 in the debugfs file condition (Ville) Reviewed-by:
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Damien Lespiau authored
This logically belongs to the WM state, so do it there. Reviewed-by:
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Damien Lespiau authored
We're going to add a new step, let's not hide the copy of the new WM state inside one inner function, but as a 1st level operation in the WM update. v2: Split the staging results structure to not exceed the 1Kb stack allocation in skl_update_wm() Reviewed-by: -
Vandana Kannan authored
According to updated BSpec, If level 1 or any higher level has a value of 0x00, that level and any higher levels are unused and the associated watermark registers must not be enabled. This patch checks for latency 0 for level >=1 and does not enable WM corresponding to level m | m>=n, if level n (n != 0) has a 0us latency. v2: Satheesh's review comments - zero-out latency values (for all higher levels if latency of given level is zero ) in read_wm_latency() function itself v3: removed redundant check as per Satheesh's observation. v4: rebase on top before merging (Damien) v5: Rebase on top of the default value removal (Ville) Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3) Reviewed-by:
Vandana Kannan <vandana.kannan@intel.com> Signed-off-by:
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Vandana Kannan authored
According to the updated Bspec, The mailbox response data is not currently accounting for memory read latency. Add 2 microseconds to the result for each level. This patch adds 2us to latency of level 0 for all cases and for all other levels (1-7) only if latency[level] > 0. v2: Slightly rework the patch and add a big comment (Damien) v3: Rebase on top of the renames of the memory latency defines Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1) Signed-off-by:
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Pradeep Bhat authored
This patch provides the implementation for reading the pipe wm HW state. v2: Incorporated Damien's review comments and also made modifications to incorporate the plane/cursor split. v3: No need to ident a line that was fitting 80 chars Return early instead of indenting the remaining of a function (Damien) v4: Rebase on top of nightly (minor conflict in intel_drv.h) v5: Rebase on top of nightly (minor conflict in intel_drv.h) v6: Rebase on top of nightly (minor conflict in intel_drv.h) Reviewed-by:Pradeep Bhat <pradeep.bhat@intel.com> Signed-off-by:
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Damien Lespiau authored
v2: Adapt to the planes/cursor split Reviewed-by:
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Damien Lespiau authored
v2: Fix the 3rd plane/cursor logic (Pradeep Bhat) v3: Fix one-by-one error in the DDB allocation code v4: Rebase on top of the skl_pipe_pixel_rate() argument change v5: Replace the available/start/end output parameters of skl_ddb_get_pipe_allocation_limits() by a single ddb entry constify a few arguments Make nth_active_pipe 0 indexed Use sizeof(variable) instead of sizeof(type) (Ville) v6: Use the for_each_crtc() macro instead of list_for_each_entry() Reviewed-by: -
Pradeep Bhat authored
This patch implements the watermark algorithm and its necessary functions. Two function pointers skl_update_wm and skl_update_sprite_wm are provided. The skl_update_wm will update the watermarks for the crtc provided as an argument and then checks for change in DDB allocation for other active pipes and recomputes the watermarks for those Pipes and planes as well. Finally it does the register programming for all dirty pipes. The trigger of the Watermark double buffer registers will have to be once the plane configurations are done by the caller. v2: fixed the divide-by-0 error in the results computation func. Also reworked the PLANE_WM register values computation func to make it more compact. Incorporated all other review comments from Damien. v3: Changed the skl_compute_plane_wm function to now return success or failure. Also the result blocks and lines are computed here instead of in skl_compute_wm_results function. v4: Adjust skl_ddb_alloc_changed() to the new planes/cursor split (Damien) v5: Reworked the affected functions to implement new plane/cursor split. v6: Rework the logic that triggers the DDB allocation and WM computation of skl_update_other_pipe_wm() to not depend on non-computed DDB values. Always give a valid cursor_width (at boot it's 0) to keep the invariant that we consider the cursor plane always enabled. Otherwise we end up dividing by 0 in skl_compute_plane_wm() (Damien Lespiau) v7: Spell out allocation skl_ddb_ functions should have the ddb as first argument Make the skl_ddb_alloc_changed() parameters const (Damien) v8: Rebase on top of the crtc->primary changes v9: Split the staging results structure to not exceed the 1Kb stack allocation in skl_update_wm() v10: Make skl_pipe_pixel_rate() take a pointer to the pipe config Add a comment about overflow considerations for skl_wm_method1() Various additions of const Various use of sizeof(variable) instead of sizeof(type) Various move of variable definitons to a narrower scope Zero initialize some stack allocated structures to make sure we don't have garbage in case we don't write all the values (Ville) v11: Remove non-necessary default number of blocks/lines when the plane is disabled (Ville) Reviewed-by: -
Damien Lespiau authored
We now need to allocate space in the DDB for planes being scanned out ourselves. The data structure to represent an allocation mirrors what we'll need to write in the registers later on: (start, end). We add that allocation datat to the skl_wm_values structure as part of the values to program the hardware with. v2: Split planes and cursor for consistency. v3: Make the skl_ddb_entry_size() parameter const Reviewed-by:
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Pradeep Bhat authored
This patch defines the structures needed for computation of watermarks of pipes and planes for SKL. v2: Incorporated Damien's review comments and removed unused fields in structs for future features like rotation, drrs and scaling. The skl_wm_values struct is now made more generic across planes and cursor planes for all pipes. v3: implemented the plane/cursor split. v4: Change the wm union back to a structure (Ville, Daniel) Reviewed-by: -
Pradeep Bhat authored
This patch defines SKL specific PLANE_WM Watermark registers. It also defines macros to get the addresses of different LP levels within a pipe. v2: Reworked the register definitions and associated macros to make it more generic and be able to use for_each_pipe in values computation. Incorporated Damien's review comments and indentation. v3: Added default values for lines and blocks. Provided mask for blocks. v4: Prefix intermedidate (internal-only) macros with _ (Ville) v5: Remove the lines and block defaults value (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v4) Signed-off-by: -
Pradeep Bhat authored
This patch reads the memory latency values for all the 8 levels for SKL. These values are needed for the Watermark computation. v2: Incorporated the review comments from Damien on register indentation. v3: Updated the code to use the sandybridge_pcode_read for reading memory latencies for GEN9. v4: Don't put gen 9 in the middle of an ordered list of ifs (Damien) v5: take the rps.hw_lock around sandybridge_pcode_read() (Damien) v6: Use gen >= 9 in the pcode_read() function for data1. Move the defines near the gen6 ones and prefix them with PCODE. Remove unused timeout define (the pcode_read() code has a larger timeout already). Reviewed-by:
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