- 11 Feb, 2007 22 commits
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki <yoshfuji@linux-ipv6.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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YOSHIFUJI Hideaki authored
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- 09 Feb, 2007 18 commits
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Jeff Garzik authored
The ATA_ENABLE_PATA define was never meant to be permanent, and in recent kernels, it's already been unconditionally enabled. Remove. Signed-off-by:Jeff Garzik <jeff@garzik.org>
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Jeff Garzik authored
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Alan authored
If we are doing a PIO setup for a CFA card and it blows up with a device error then assume it is an older CFA card which doesn't support this rather than failing the device out of existance. Stands seperate to the quieting patch but that is obviously useful with this change. Signed-off-by:
Alan Cox <alan@redhat.com> Signed-off-by:
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Robert Hancock authored
ata_pci_device_do_resume can fail if the PCI device couldn't be re-enabled. Update sata_nv to propagate the return value from this call and to not try to do any other resume activities if it fails. Fixes a compile warning. Signed-off-by:
Robert Hancock <hancockr@shaw.ca> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Robert Hancock authored
Update sata_nv to wait for the controller to indicate via the status register that it has entered the requested state when switching between ADMA mode and register mode. This issue came up recently when debugging some problems with cache flush command timeouts and while it didn't appear to fix that problem, this is something we should likely be doing in any case. Signed-off-by:
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Robert Hancock authored
Some problems showed up recently with cache flush commands timing out on sata_nv. Previously these commands were always handled by transitioning to legacy mode from ADMA mode first. The timeout problem was worked around already by a change to the interrupt handling code for legacy mode, but for non-data commands like these it appears we can handle them in ADMA mode, so the switch to legacy mode is not needed. This patch changes the behavior so that we use ADMA mode to submit interrupt-driven commands with ATA_PROT_NODATA protocol. In addition to avoiding the problem mentioned above entirely, this avoids the overhead of switching to legacy mode and back to ADMA mode for handling cache flushes. When handling non-DMA-mapped commands, we leave the APRD blank and clear the NV_CPB_CTL_APRD_VALID field in the CPB so the controller does not attempt to read it. Signed-off-by:
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Robert Hancock authored
This cleans up a few issues with the error handling in sata_nv in ADMA mode to make it more consistent with other NCQ-capable drivers like ahci and sata_sil24: - When a command failed, we would effectively set AC_ERR_DEV on the queued command always. In the case of NCQ commands this prevents libata from doing a log page query to determine the details of the failed command, since it thinks we've already analyzed. Just set flags in the port ehi->err_mask, then freeze or abort and let libata figure out what went wrong. - The code handled NV_ADMA_STAT_CPBERR as a "really bad error" which caused it to set error flags on every queued command. I don't know exactly what this flag means (no docs, grr!) but from what I can guess from the standard ADMA spec, it just means that one or more of the CPBs had an error, so we just need to go through and do our normal checks in this case. - In the error_handler function the code would always dump the state of all the CPBs. This output seems redundant at this point since libata already dumps the state of all active commands on errors (and it also triggers at times when it shouldn't, like when suspending). Take this out. [akpm@osdl.org: many coding-style fixes] Signed-off-by:
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Sergei Shtylyov authored
MPIIX has only single channel IDE which can be configured for either primary or secondary legacy I/O ports and IRQ. So, get rid of the unneeded second probe entry in mpiix_init_one() and of the invalid (but unused anyway) enable bits in mpiix_pre_reset(). Warning: this cleanup has only been compile-tested... Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
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Sergei Shtylyov authored
Fix clearing/setting the wrong TIME/IE/PPE bits for a slave drive caused by a wrong shift count. Fix the PIO mode 1 being overclocked by wrongly selecting the fast timing bank. Also, fix/rephrase some comments while at it. Signed-off-by:
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Sergei Shtylyov authored
Fix the PIO mode 2 using mode 0 timings -- this driver should enable the fast timing bank starting with PIO2, just like the ata_piix driver does. Also, fix/rephrase some comments while at it. Signed-off-by:
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Alan authored
IORDY and IORDY enable/disable flags. Signed-off-by:
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Alan authored
People are getting confused about which drivers to enable for PATA PIIX type devices. Change the ATA_PIIX line and help to make it clearer. Signed-off-by:
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Tejun Heo authored
* Hardreset must not exit without actually performing reset regardless of link status. We're resetting the link after all. * Minor message update. * 150ms delay is meaningful iff link is online after reset is complete. Signed-off-by:
Tejun Heo <htejun@gmail.com> Signed-off-by:
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Tejun Heo authored
Follow the old SRST rule and delay 150ms between completion of hardreset and status checking. Debouncing delay should usually cover this but debounce duration could be shorter than 150ms under certain circumstances. Usefulness depends on host controller implementation but it can't hurt and serves as a reminder that 2s delay for GoVault should also be added here. Signed-off-by:
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Eric D. Mudama authored
Per Jeff's suggestion, this patch rearranges the info printed for ATA drives into dmesg to add the full ATA firmware revision and model information, while keeping the output to 2 lines. Signed-off-by:
Eric D. Mudama <edmudama@gmail.com> Signed-off-by:
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Sergei Shtylyov authored
Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1 only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly. Signed-off-by: -
Akira Iguchi authored
This patch is against each libata driver. Two IRQ calls are added in ata_port_operations. - irq_on() is used to enable interrupts. - irq_ack() is used to acknowledge a device interrupt. In most drivers, ata_irq_on() and ata_irq_ack() are used for irq_on and irq_ack respectively. In some drivers (ex: ahci, sata_sil24) which cannot use them as is, ata_dummy_irq_on() and ata_dummy_irq_ack() are used. Signed-off-by:
Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Signed-off-by:
Akira Iguchi <akira2.iguchi@toshiba.co.jp> Signed-off-by:
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Akira Iguchi authored
This patch is against the libata core and headers. Two IRQ calls are added in ata_port_operations. - irq_on() is used to enable interrupts. - irq_ack() is used to acknowledge a device interrupt. In most drivers, ata_irq_on() and ata_irq_ack() are used for irq_on and irq_ack respectively. In some drivers (ex: ahci, sata_sil24) which cannot use them as is, ata_dummy_irq_on() and ata_dummy_irq_ack() are used. Signed-off-by:
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