1. 15 May, 2019 36 commits
  2. 10 May, 2019 1 commit
    • Stephane Eranian's avatar
      perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking · 6b89d4c1
      Stephane Eranian authored
      On Intel Westmere, a cmdline as follows:
      
        $ perf record -e cpu/event=0xc4,umask=0x2,name=br_inst_retired.near_call/p ....
      
      was failing. Yet the event+ umask support PEBS.
      
      It turns out this is due to a bug in the the PEBS event constraint table for
      westmere. All forms of BR_INST_RETIRED.* support PEBS. Therefore the constraint
      mask should ignore the umask. The name of the macro INTEL_FLAGS_EVENT_CONSTRAINT()
      hint that this is the case but it was not. That macros was checking both the
      event code and event umask. Therefore, it was only matching on 0x00c4.
      There are code+umask macros, they all have *UEVENT*.
      
      This bug fixes the issue by checking only the event code in the mask.
      Both single and range version are modified.
      Signed-off-by: default avatarStephane Eranian <eranian@google.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: kan.liang@intel.com
      Link: http://lkml.kernel.org/r/20190509214556.123493-1-eranian@google.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      6b89d4c1
  3. 08 May, 2019 1 commit
  4. 07 May, 2019 2 commits
    • Linus Torvalds's avatar
      Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · ffa6f55e
      Linus Torvalds authored
      Pull RAS updates from Borislav Petkov:
      
       - Support for varying MCA bank numbers per CPU: this is in preparation
         for future CPU enablement (Yazen Ghannam)
      
       - MCA banks read race fix (Tony Luck)
      
       - Facility to filter MCEs which should not be logged (Yazen Ghannam)
      
       - The usual round of cleanups and fixes
      
      * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        x86/MCE/AMD: Don't report L1 BTB MCA errors on some family 17h models
        x86/MCE: Add an MCE-record filtering function
        RAS/CEC: Increment cec_entered under the mutex lock
        x86/mce: Fix debugfs_simple_attr.cocci warnings
        x86/mce: Remove mce_report_event()
        x86/mce: Handle varying MCA bank counts
        x86/mce: Fix machine_check_poll() tests for error types
        MAINTAINERS: Fix file pattern for X86 MCE INFRASTRUCTURE
        x86/MCE: Group AMD function prototypes in <asm/mce.h>
      ffa6f55e
    • Linus Torvalds's avatar
      Merge tag 'edac_for_5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp · 275b103a
      Linus Torvalds authored
      Pull EDAC updates from Borislav Petkov:
      
       - amd64_edac: Family 0x17, models 0x30-.. enablement (Yazen Ghannam)
      
       - skx_*: Librarize it so that it can be shared between drivers (Qiuxu Zhuo)
      
       - altera: Stratix10 improvements (Thor Thayer)
      
       - The usual round of fixes, fixlets and cleanups
      
      * tag 'edac_for_5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
        Revert "EDAC/amd64: Support more than two controllers for chip select handling"
        arm64: dts: stratix10: Use new Stratix10 EDAC bindings
        Documentation: dt: edac: Add Stratix10 Peripheral bindings
        Documentation: dt: edac: Fix Stratix10 IRQ bindings
        EDAC/altera, firmware/intel: Add Stratix10 ECC DBE SMC call
        EDAC/altera: Initialize peripheral FIFOs in probe()
        EDAC/altera: Do less intrusive error injection
        EDAC/amd64: Adjust printed chip select sizes when interleaved
        EDAC/amd64: Support more than two controllers for chip select handling
        EDAC/amd64: Recognize x16 symbol size
        EDAC/amd64: Set maximum channel layer size depending on family
        EDAC/amd64: Support more than two Unified Memory Controllers
        EDAC/amd64: Use a macro for iterating over Unified Memory Controllers
        EDAC/amd64: Add Family 17h Model 30h PCI IDs
        MAINTAINERS: Add entry for EDAC-I10NM
        MAINTAINERS: Update entry for EDAC-SKYLAKE
        EDAC, altera: Fix S10 Double Bit Error Notification
        EDAC, skx, i10nm: Make skx_common.c a pure library
      275b103a