- 06 Aug, 2019 3 commits
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Chris Wilson authored
To maintain a fast lookup from a GT centric irq handler, we want the engine lookup tables on the intel_gt. To avoid having multiple copies of the same multi-dimension lookup table, move the generic user engine lookup into an rbtree (for fast and flexible indexing). v2: Split uabi_instance cf uabi_class v3: Set uabi_class/uabi_instance after collating all engines to provide a stable uabi across parallel unordered construction. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20190806124300.24945-2-chris@chris-wilson.co.uk
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Chris Wilson authored
We do not notify userspace when the scheduler capabilities are changed (due to wedging the driver) and as such userspace will expect the caps to be static and unchanging. Make it so, and so we only need to compute our caps once during driver registration. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190806124300.24945-1-chris@chris-wilson.co.uk
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Chris Wilson authored
As we store a pointer to i915 in the drvdata field (as the pointer is both an alias to the drm_device and drm_i915_private), we can use the stored pointer directly as the i915 device. v2: Store and use i915 inside drv_get_drvdata() v3: Only expect i915 inside drv_get_drvdata() so drop the assumed i915/drm equivalence. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190806074219.11043-1-chris@chris-wilson.co.uk
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- 05 Aug, 2019 6 commits
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Chris Wilson authored
The kerneldoc were stale, generating mismatching parameters warning, but furthermore they were for internal routines, not part of the MOCS interface so the instructions were superfluous. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190803102221.21344-1-chris@chris-wilson.co.uk
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Michal Wajdeczko authored
Since commit 301efe96 ("drm/i915/uc: Don't fail on HuC firmware failure") we can continue driver load after error during HuC firmware load or authentication, but we could still fail on any error during early HuC initialization. Change that by ignoring HuC related errors until hardware initialization phase where we can decide about next steps. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Michal Wajdeczko authored
Since commit db81bc6e ("drm/i915/uc: Consider enable_guc modparam during fw selection") we have started using firmware status as main indicator of the GuC support. No need to use same checks twice. Signed-off-by:
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Michal Wajdeczko authored
No need to dance with intel_uc_supports_huc(uc) as we can directly use intel_huc_is_supported(huc) Signed-off-by:
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Michal Wajdeczko authored
No need to use intel_uc_supports_guc_submission(uc) as we can directly use intel_guc_is_submission_supported(guc) Signed-off-by:
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Stanislav Lisovskiy authored
According to Bspec clock divisor registers in GeminiLake should be initialized by shifting 1(<<) to amount of correspondent divisor. While i915 was writing all this time that value as is. Surprisingly that it by accident worked, until we met some issues with Microtech Etab. v2: Added Fixes tag and cc v3: Added stable to cc as well. Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826 Fixes: bcc65700 ("drm/i915/glk: Program txesc clock divider for GLK") Cc: Deepak M <m.deepak@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712081938.14185-1-stanislav.lisovskiy@intel.com
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- 04 Aug, 2019 2 commits
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Chris Wilson authored
Switch to tracking activity via i915_active on individual nodes, only keeping a list of retired objects in the cache, and reaping the cache when the engine itself idles. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190804124826.30272-2-chris@chris-wilson.co.uk
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Chris Wilson authored
In the next patch, we would like to couple into the engine wakeref to free the batch pool on idling. The caveat here is that we therefore want to track the engine wakeref more precisely and to hold it instead of the broader GT wakeref as we process the ioctl. v2: Avoid introducing odd semantics for a shortlived timeline->mutex acquisition interface. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190804124826.30272-1-chris@chris-wilson.co.uk
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- 02 Aug, 2019 14 commits
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Chris Wilson authored
As we increase the number of RCU objects, it becomes easier for us to have several hundred thousand objects in the deferred RCU free queues. An example is gem_ctx_create/files which continually creates active contexts, which are not immediately freed upon close as they are kept alive by outstanding requests. This lack of backpressure allows the context objects to persist until they overwhelm and starve the system. We can increase our backpressure by flushing the freed object queue upon closing the device fd which should then not impact other clients. Testcase: igt/gem_ctx_create/*files Signed-off-by:
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Chris Wilson authored
The shrinker cannot touch objects used by the contexts (logical state and ring). Currently we mark those as "pin_global" to let the shrinker skip over them, however, if we remove them from the shrinker lists entirely, we don't event have to include them in our shrink accounting. By keeping the unshrinkable objects in our shrinker tracking, we report a large number of objects available to be shrunk, and leave the shrinker deeply unsatisfied when we fail to reclaim those. The shrinker will persist in trying to reclaim the unavailable objects, forcing the system into a livelock (not even hitting the dread oomkiller). v2: Extend unshrinkable protection for perma-pinned scratch and guc allocations (Tvrtko) v3: Notice that we should be pinned when marking unshrinkable and so the link cannot be empty; merge duplicate paths. Signed-off-by:
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Michal Wajdeczko authored
We don't have to immediately fail on WOPCM partitioning, we can wait until we will start programming WOPCM registers. This should give us more options if we decide to restore fallback in case of GuC failures. v3: rebased Signed-off-by:
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Michal Wajdeczko authored
Inject probe errors into intel_uc_init_hw to make sure we correctly handle any uC initialization failure. To avoid complains from CI about injected errors use i915_probe_error to lower message level. v4: rebased after moving hot fixes moved to separate patches Signed-off-by:
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Michal Wajdeczko authored
When we fail to load GuC and want to abort probe, we hit: <7> [229.915779] i915 0000:00:02.0: [drm:intel_uc_init_hw [i915]] GuC initialization failed -6 <7> [229.915813] i915 0000:00:02.0: [drm:i915_gem_init_hw [i915]] Enabling uc failed (-6) <4> [229.953354] ------------[ cut here ]------------ <4> [229.953355] WARN_ON(dev_priv->mm.shrink_count) <4> [229.953406] WARNING: CPU: 9 PID: 3287 at drivers/gpu/drm/i915/i915_gem.c:1684 i915_gem_cleanup_early+0xfc/0x110 [i915] <4> [229.953464] Call Trace: <4> [229.953489] i915_driver_late_release+0x19/0x60 [i915] <4> [229.953514] i915_driver_probe+0xb82/0x18a0 [i915] <4> [229.953519] ? __pm_runtime_resume+0x4f/0x80 <4> [229.953545] i915_pci_probe+0x43/0x1b0 [i915] ... <4> [229.962951] ------------[ cut here ]------------ <4> [229.962956] DEBUG_LOCKS_WARN_ON(lock->magic != lock) <4> [229.962959] WARNING: CPU: 8 PID: 2395 at kernel/locking/mutex.c:912 __mutex_lock+0x750/0x9b0 <4> [229.963091] Call Trace: <4> [229.963129] ? i915_vma_destroy+0x86/0x350 [i915] <4> [229.963166] ? i915_vma_destroy+0x86/0x350 [i915] <4> [229.963201] i915_vma_destroy+0x86/0x350 [i915] <4> [229.963236] __i915_gem_free_objects+0xb8/0x510 [i915] <4> [229.963270] __i915_gem_free_work+0x5a/0x90 [i915] <4> [229.963275] process_one_work+0x245/0x610 as since commit 6f76098f ("drm/i915/uc: Move uC early functions inside the GT ones") we cleanup uc after gem. Move captured GuC load error log to uc struct and release it in intel_uc_fini() instead of intel_uc_driver_late_release() Note that intel_uc_driver_late_release() is now empty, but we can leave it as a placeholder for future code. Signed-off-by:
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Michal Wajdeczko authored
On Gen9 when we try to reload HuC due to GuC upload error, we hit: <7> [232.025927] [drm:intel_uc_init_hw [i915]] GuC fw load failed: -8; will reset and retry 2 more time(s) <7> [232.026004] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <7> [232.026686] [drm:intel_uc_fw_upload [i915]] HuC fw xfer completed <6> [232.026688] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0) <3> [232.026703] intel_uc_fw_copy_rsa:541 GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)) as firmware that previously failed to load was wrongly treated as unavailable since its status code was not matching status check logic. Signed-off-by:
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Michal Wajdeczko authored
On Gen9 when we try to reload HuC due to GuC upload error, we hit: <7> [229.656688] [drm:intel_uc_init_hw [i915]] GuC fw load failed: -8; will reset and retry 2 more time(s) <7> [229.656739] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <3> [229.656740] intel_uc_fw_upload:425 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)) as we performed only pure reset and didn't sanitized HuC fw status. Signed-off-by:
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Michal Wajdeczko authored
With i915 added to i915_inject_probe_failure we can use dedicated printk when injecting artificial load failure. Also make this function look like other i915 functions that return error code and make it more flexible to return any provided error code instead of previously assumed -ENODEV. Signed-off-by:
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Chris Wilson authored
Since commit 64d6c500 ("drm/i915: Generalise GPU activity tracking"), we have been prepared for i915_vma_move_to_active() to fail. We can take advantage of this to report the failure for allocating the shared-fence slot in the reservation_object. Signed-off-by:
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Michal Wajdeczko authored
Use section name "Return" and proper error code -ETIMEDOUT Signed-off-by:
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Jani Nikula authored
Update the generated files to make the headers self-contained, switch to the kernel preferred SPDX comment format, and update the copyright year. Also add the Makefile stanza to run header tests on the files. Other changes produced by gputop i915-perf-kernelgen.py were manually stripped out, and left to the folks who actually know something about the OA stuff. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
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Chris Wilson authored
By placing our idle-barriers in the i915_active fence tree, we expose those for reuse by other components that are issuing requests along the kernel_context. Reusing the proto-barrier active_node is perfectly fine as the new request implies a context-switch, and so an opportune point to run the idle-barrier. However, the proto-barrier is not equivalent to a normal active_node and care must be taken to avoid dereferencing the ERR_PTR used as its request marker. v2: Comment the more egregious cheek v3: A glossary! Reported-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: ce476c80 ("drm/i915: Keep contexts pinned until after the next kernel context switch") Fixes: a9877da2 ("drm/i915/oa: Reconfigure contexts on the fly") Signed-off-by:
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Chris Wilson authored
Recently discovered in commit bdae33b8 ("drm/i915: Use maximum write flush for pwrite_gtt") was that we needed to our full write barrier before changing the GGTT PTE to ensure that our indirect writes through the GTT landed before the PTE changed (and the writes end up in a different page). That also applies to our GGTT relocation path. Signed-off-by:
Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730112151.5633-4-chris@chris-wilson.co.uk
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Chris Wilson authored
Currently, we only sample if the intel_gt is awake, but we acquire our own runtime_pm wakeref. Since intel_gt has transitioned to tracking its own wakeref, we can atomically test and acquire that wakeref instead. v2: Take engine->wakeref for engine sampling Signed-off-by:
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- 01 Aug, 2019 15 commits
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Tvrtko Ursulin authored
RC6 is a GT state so make the function parameter reflect that. Signed-off-by:
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Tvrtko Ursulin authored
Engines and frequencies are a GT thing so adjust sampling routines to match. Signed-off-by:
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Tvrtko Ursulin authored
Drops one macro using implicit dev_priv. v2: * Use ENGINE_READ_FW. (Chris) Signed-off-by:
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Tvrtko Ursulin authored
Just tidy the code a bit by removing a sea of overly verbose i915->pmu.*. Signed-off-by:
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Jordan Justen authored
This enables the Mesa driver to advertise support for ARB_timer_query, and thus an OpenGL version higher than 3.2. Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jordan Justen <jordan.l.justen@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190726002412.5827-3-lucas.demarchi@intel.com
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José Roberto de Souza authored
Tiger Lake has a new register offset for DC5 and DC6 residency counters. v2: - Rename registers since they are not in the CSR memory range (requested by Anshuman) - Fix type (requested by Matthew) Signed-off-by:José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190726002412.5827-2-lucas.demarchi@intel.com
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Michal Wajdeczko authored
As we already track GuC/HuC uses by other means than modparam there is no point in sanitizing it. Just scan modparam for major discrepancies between what was requested vs actual. v2: rebased, reworded info messages v3: oops Signed-off-by:
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Michal Wajdeczko authored
Instead of relying on enable_guc modparam to represent actual GuC submission mode, use dedicated flag and look at modparam only to check if submission was explicitly disabled by the user. v2: rebased, simplified condition (Chris) Signed-off-by:
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Michal Wajdeczko authored
We can use value of enable_guc modparam during firmware path selection and start using firmware status to see if GuC/HuC is being used. This is first step to make enable_guc modparam read-only. v2: rebased, don't care about <0 (Chris) v3: oops Signed-off-by:
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Michal Wajdeczko authored
Rename intel_uc_is_using* into intel_uc_supports* to make clear distinction from actual state (compare intel_uc_fw_is_running) Suggested-by:
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Daniele Ceraolo Spurio authored
To be called from the top level runtime functions, to hide the gt-specific bits (mainly related to intel_uc). v2: rebased Signed-off-by:
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Daniele Ceraolo Spurio authored
uC is a subcomponent of GT, so initialize/clean it as part of it. The wopcm_init_early doesn't have to be happen before the uC one, but since in other parts of the code we consider WOPCM first do the same for consistency. v2: s/cleanup_early/late_release to match the caller v3: s/late_release/driver_late_release/ (Chris) Signed-off-by:
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Daniele Ceraolo Spurio authored
We don't call the init_early function from within the gem code, so we shouldn't do it for the cleanup either. v2: while at it, s/gt_cleanup_early/gt_late_release (Chris) v3: s/late_release/driver_late_release/ (Chris) Signed-off-by:
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Chris Wilson authored
We only compute the lrc_descriptor() on pinning the context, i.e. infrequently, so we do not benefit from storing the template as the addressing mode is also fixed for the lifetime of the intel_context. Signed-off-by:
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Matt Roper authored
We're mostly re-using ICL's interrupt handling on EHL, but we still need to remember to account for the extra combo port that EHL has. Use TGP's mask (which includes combo port C) rather than ICP's mask when appropriate. Let's also skip reading TC-specific registers on this platform since EHL doesn't have any TC ports. v2: Base setup of SHOTPLUG_CTL_TC on whether the tc pin mask is non-zero rather than performing another PCH type check. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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