- 16 Jun, 2009 16 commits
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Heiko Schocher authored
The following series implements basic board support for the kmeter1 board from keymile, based on a MPC8360. This series provides the following functionality: - The board can boot with a serial console on UART1 - Ethernet: UCC1 in RGMII mode UCC2 in RGMII mode UCC4 in RMII mode UCC5 in RMII mode UCC6 in RMII mode UCC7 in RMII mode UCC8 in RMII mode following patch is necessary for working UCC in RMII mode: http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070804.html - Flash accessed via MTD layer On this hardware there is an Intel P30 flash, following patch series is necessary for working with this hardware: http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070624.html - I2C using I2C Bus 1 from the MPC8360 cpu Signed-off-by:Heiko Schocher <hs@denx.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kevin Hao authored
Add 4 partitions in nor flash. Also fix nor flash bank width bug. The flash is capable of x8/x16 width but is configured for x8. Signed-off-by:
Kevin Hao <kexin.hao@windriver.com> Signed-off-by:
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mware@internode.on.net authored
Currently the fsl,*lbc devices support 8 banks (ie OR and BR registers). This is adequate for most pq2 and pq3 processors, but not the MPC8280 which has 12 banks. Signed-Off-By:
Mark Ware <mware@elphinstone.net> Signed-off-by:
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Yang Li authored
Adding failure path for the following two cases. warning: ignoring return value of 'device_add', declared with attribute warn_unused_result warning: ignoring return value of 'sysfs_create_bin_file', declared with attribute warn_unused_result Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
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Nate Case authored
Some MPC85xx platforms do support 4 ethernet ports, so make sure the boot wrapper fixes up all of them in the fdt. Since MAC addresses are at the end of the bd_t structure there is no harm in expanding to support 4 MAC address on older 85xx systems that might not have that many. Signed-off-by:
Nate Case <ncase@xes-inc.com> Signed-off-by:
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Dave Liu authored
In HW UART mode the TxBD[READY] is not cleared by H/W (RISC engine) when the user send characters to Tx buffer of QE UART. So, these characters stay on the QE forever, never go to UART line. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
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Gerhard Pircher authored
Currently the kernel expects the additional four IBAT and DBAT registers to be available, but doesn't enable these registers on 745x CPUs, which have them disabled after reset. Thus set the HIGH_BAT_EN bit in HID0 register, if the corresponding MMU feature is defined. Signed-off-by:
Gerhard Pircher <gerhard_pircher@gmx.net> Signed-off-by:
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Peter Korsgaard authored
usb0 and usb1 mux settings in the sicrl register were swapped (twice!) in mpc834x_usb_cfg(), leading to various strange issues with fsl-ehci and full speed devices. The USB port config on mpc834x is done using 2 muxes: Port 0 is always used for MPH port 0, and port 1 can either be used for MPH port 1 or DR (unless DR uses UTMI phy or OTG, then it uses both ports) - See 8349 RM figure 1-4.. mpc8349_usb_cfg() had this inverted for the DR, and it also had the bit positions of the usb0 / usb1 mux settings swapped. It would basically work if you specified port1 instead of port0 for the MPH controller (and happened to use ULPI phys), which is what all the 834x dts have done, even though that configuration is physically invalid. Instead fix mpc8349_usb_cfg() and adjust the dts files to match reality. Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
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leon.woestenberg@gmail.com authored
The PCIe MSI interrupts are missing from the device tree source, and thus were not enabled. This patch adds them. Tested to work on MPC8315E-RDB with custom FPGA PCIe device. Signed-off-by:
Leon Woestenberg <leon@sidebranch.com> Tested-by:
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Martyn Welch authored
Mappings for temperature sensors (adt7461 and lm92) are missing from the SBC610's DTS file. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
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Haiying Wang authored
Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
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Anton Vorontsov authored
As of commit 40461472 ("Update FSL esdhc binding"), we use "fsl,esdhc" compatible entry as a base match. U-Boot will use the same compatible to fixup esdhc nodes. This patch updates 83xx dts files so that they conform to the new bindings. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Nate Case authored
Some boot loaders may not enable L1 instruction/data cache. Check if data and instruction caches are enabled, and enable them if needed. Signed-off-by:
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Wolfgang Denk authored
The current device tree for the MPC8272ADS assumes a mapping of 32 MB of NOR flash at 0xFE00.0000, while there are actually only 8 MB on the boards, mapped at 0xFF80.0000. When booting an uImage with such a device tree, the kernel crashes because 0xFE00.0000 is not mapped. Also introduce aliases for serial[01] and ethernet[01]. Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
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Kumar Gala authored
Add the platform-specific code for enabling SWIOTLB if needed on P2020DS, MPC85xx DS, and MPC85xx MDS boards as they are capable of having >4G of memory. We determine if we need to enable swiotlb based on how much memory is in the board and if it exceeds 4G or what we can map via PCI inbound windows. Signed-off-by: -
Becky Bruce authored
This is the final bit of code to allow enabling swiotlb on mpc86xx. The platform-specific code is very small and consists of enabling SWIOTLB in the config file, registering the swiotlb_setup_bus_notifier initcall, and setting pci_dma_ops to point to swiotlb_pci_dma_ops if we have more memory than can be mapped by the inbound PCI windows. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
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- 15 Jun, 2009 24 commits
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Geert Uytterhoeven authored
Add support for caching, to reduce FLASH wear when writing using small blocksizes. As we also don't care anymore about heads and tails in case of partial writes, this greatly simplifies the code for handling writes. Note: We don't bother caching reads smaller than the FLASH chunk size (256 KiB). Signed-off-by:
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Geert Uytterhoeven authored
Currently the FLASH database is updated by the kernel using file operations, meant for userspace only. While this works for us because copy_{from,to}_user() on powerpc can handle kernel pointers, this is unportable and a bad example. Replace the file operations by callbacks, registered by the ps3flash driver. Signed-off-by:Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by:
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Geert Uytterhoeven authored
They were never intended to be exported using EXPORT_SYMBOL() anyway Signed-off-by:
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Geert Uytterhoeven authored
It reports the failure of a call to lv1_put_iopte(), not lv1_map_device_dma_region(). Signed-off-by:
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Geert Uytterhoeven authored
probe functions should be __devinit initialization functions should be __init Signed-off-by:
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Roel Kluin authored
In the near future, the driver core is going to not allow direct access to the driver_data pointer in struct device. Instead, the functions dev_get_drvdata() and dev_set_drvdata() should be used. These functions have been around since the beginning, so are backwards compatible with all older kernel versions. [Geert: Use ps3_system_bus_[gs]et_driver_data() for ps3_system_bus_device] Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
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Geert Uytterhoeven authored
So we can kill a cast. Signed-off-by:
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
Remove the mutex serializing access to the cache. Instead, queue up new requests on a bio_list if the driver is busy. This improves sequential write performance by ca. 2%. Signed-off-by:
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Geert Uytterhoeven authored
Introduce bio_list_peek(), to obtain a pointer to the first bio on the bio_list without actually removing it from the list. This is needed when you want to serialize based on the list being empty or not. Signed-off-by:
Jens Axboe <axboe@kernel.dk> Signed-off-by:
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Paul Mackerras authored
This makes 32-bit powerpc use the generic atomic64_t implementation. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Paul Mackerras authored
Many processor architectures have no 64-bit atomic instructions, but we need atomic64_t in order to support the perf_counter subsystem. This adds an implementation of 64-bit atomic operations using hashed spinlocks to provide atomicity. For each atomic operation, the address of the atomic64_t variable is hashed to an index into an array of 16 spinlocks. That spinlock is taken (with interrupts disabled) around the operation, which can then be coded non-atomically within the lock. On UP, all the spinlock manipulation goes away and we simply disable interrupts around each operation. In fact gcc eliminates the whole atomic64_lock variable as well. Signed-off-by:
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Paul Mackerras authored
On 32-bit non-Book E, local_irq_restore() turns into just mtmsr(), which doesn't currently have a compiler memory barrier. This means that accesses to memory inside a local_irq_save/restore section, or a spin_lock_irqsave/spin_unlock_irqrestore section on UP, can be reordered by the compiler to occur outside that section. To fix this, this adds a compiler memory barrier to mtmsr for both 32-bit and 64-bit. Having a compiler memory barrier in mtmsr makes sense because it will almost always be changing something about the context in which memory accesses are done, so in general we don't want memory accesses getting moved from one side of an mtmsr to the other. With the barrier in mtmsr(), some of the explicit barriers in hw_irq.h are now redundant, so this removes them. Signed-off-by:
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Michael Ellerman authored
signal_vsp_instruction() is currently only used if CONFIG_PROC_FS is enabled. However logically it has nothing to do with PROC_FS, so rather than making it depend on that mark it as maybe unused. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Michael Ellerman authored
If CONFIG_BLK_DEV_INITRD is unset dt_prop_u64() is unused, which causes a warning. We don't really want to tie the definition to BLK_DEV_INITRD, so mark it as maybe unused. Signed-off-by:
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Michael Ellerman authored
Commit 28794d34 ("powerpc/kconfig: Kill PPC_MULTIPLATFORM"), added CONFIG_PPC_OF_BOOT_TRAMPOLINE to control the buliding of prom_init.o However the Makefile still unconditionally builds prom_init_check, the script that checks prom_init.o for symbol usage, and so in turn prom_init.o is still always being built. (it's not linked though) So surround all the prom_init_check logic with an ifeq block testing if CONFIG_PPC_OF_BOOT_TRAMPOLINE is set. Signed-off-by:
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Stephen Rothwell authored
Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Michael Ellerman authored
The Axon MSI driver incorrectly uses platform_data, rather than the proper accessors for driver_data. Signed-off-by:
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Michael Ellerman authored
When CONFIG_RELOCATABLE is enabled, PHYSICAL_START is actually a variable of type phys_addr_t. That means to print it we need to cast to unsigned long long and use llx. Signed-off-by:
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