- 29 Jul, 2014 9 commits
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Gabriel FERNANDEZ authored
This patch introduces polarity indication for pll power up bit and for standby bit in order to have same code between stih416 and stih407 boards. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by:
Peter Griffin <peter.griffin@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Gabriel FERNANDEZ authored
The patch added support for DT registration of ClockGenA0 It includes c32 type PLL. Signed-off-by:
Olivier Bideau <olivier.bideau@st.com> Signed-off-by:
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Gabriel FERNANDEZ authored
The patch supports the A9-mux clocks used by ClockGenA9 Signed-off-by:
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Gabriel FERNANDEZ authored
This patch is the Flexgen implementation reusing as much as possible of Common Clock Framework functions. The idea is to have an instance of "struct flexgen" per output clock. It represents the clock cross bar (by a mux element), and the pre and final dividers (using dividers and gates elements). Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
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Gabriel FERNANDEZ authored
A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by:
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Gabriel FERNANDEZ authored
Signed-off-by:
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Gabriel FERNANDEZ authored
converts clkgen_pll_data tables into static const Signed-off-by:
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Gabriel FERNANDEZ authored
converts stm_fs tables into static const Signed-off-by:
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Gabriel FERNANDEZ authored
Naming convention was changed in dts file but the clock binding documentation hasn't been updated. Signed-off-by:
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- 28 Jul, 2014 2 commits
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Emilio López authored
There are some structs and arrays on the driver that are not used anywhere else. Let's mark them as static. Signed-off-by:
Emilio López <emilio@elopez.com.ar> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Emilio López authored
This commit adds __iomem thoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here. Signed-off-by:
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- 26 Jul, 2014 1 commit
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Mike Turquette authored
Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi Allwinner clocks additions for 3.17 This pull request adds support for the clocks found in the newly supported Allwinner A23 clocks.
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- 25 Jul, 2014 3 commits
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Mike Turquette authored
Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm qcom clock changes for 3.17 These patches add support for a handful of Qualcomm's SoC clock controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064. There's also a small collection of bug fixes that aren't critical -rc worthy regressions because the consumer drivers aren't present or using the buggy clocks and one optimization for HDMI.
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Mike Turquette authored
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Sylwester Nawrocki authored
This patch adds helper functions to configure clock parents and rates as specified through 'assigned-clock-parents', 'assigned-clock-rates' DT properties for a clock provider or clock consumer device. The helpers are now being called by the bus code for the platform, I2C and SPI busses, before the driver probing and also in the clock core after registration of a clock provider. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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- 24 Jul, 2014 1 commit
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Mike Turquette authored
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- 15 Jul, 2014 10 commits
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Stephen Boyd authored
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: -
Stephen Boyd authored
The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by:
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Stephen Boyd authored
Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f "clk: qcom: Consolidate common probe code" Signed-off-by:
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Stephen Boyd authored
Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Stephen Boyd authored
In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by:
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Kumar Gala authored
Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
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Georgi Djakov authored
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by:
Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by:
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Chen-Yu Tsai authored
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific compatible to the sun6i-a31-apb0-gates clock driver, along with the gate bitmap. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
sun6i-apb0-gates uses the "clock-indices" DT property to indicate valid gate bits or holes in between. However, the rest of sunxi clock drivers use bitmaps for this purpose. This patch modifies sun6i-apb0-gates to use bitmaps as well, to be consistent with the sunxi platform. Also add the missing call to clk_register_clkdev, so system clock lookups will work. Signed-off-by:
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- 13 Jul, 2014 14 commits
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Heiko Stübner authored
All known Rockchip SoCs have a reset controller in their CRUs, so it's helpful to have the reset controller framework selected by default, only be deselected by the user in special cases. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-By:
Max Schwarz <max.schwarz@online.de> Tested-By:
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Heiko Stübner authored
Add the clock tree definition for the new rk3288 SoC. Signed-off-by:
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Heiko Stübner authored
This adds the dt-binding documentation for the clock and reset unit found on Rockchip rk3288 SoCs. Signed-off-by:
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Heiko Stübner authored
This adds a clock driver that handles the specific muxes, dividers and gates of rk3188 and rk3066 SoCs. The structure of the clock list resembles the arrangement of their counterparts in the clock architecture diagrams found in the SoC documentation. Clocks exported to the clock provider are currently limited to well known or measured ones. So additional clock exports may be necessary in the future. Signed-off-by:
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Heiko Stübner authored
This add bindings documentation for the clock and reset unit found on rk3188 and rk3066 SoCs from Rockchip. Also deprecate the old gate clock binding, as these shouldn't be used in the future. Signed-off-by:
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Heiko Stübner authored
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by:
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Heiko Stübner authored
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: -
Heiko Stübner authored
This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by:
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Mike Turquette authored
The function pointer population and sanity checking logic got a bit ugly with the advent of the .determine_rate callback. Clean it up. Signed-off-by: -
Heiko Stübner authored
This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by:
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Boris BREZILLON authored
In case the rate_hw does not implement determine_rate, but only round_rate we fallback to best_parent selection if mux_hw is present and support reparenting. This also fixes a rate calculation problem when using the standard div and mux ops, as in this case currently only the mux->determine_rate is used in the composite rate calculation. So when for example the composite clock has two parents at 600 and 800MHz, the requested rate is 75MHz, which the divider could provide, without this change the rate would be set 600MHz ignoring the divider completely. This may be way out of spec for the component. Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by:
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Mike Turquette authored
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Thomas Gleixner authored
The uarts only work when the parent is ras_ahb_clk. The stale 3.5 based ST tree does this in the board file. Add it to the clk init function. Not pretty, but the mess there is amazing anyway. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Thomas Gleixner authored
The control register is at offset 0x10, not 0x0. This is wreckaged since commit 5df33a62 (SPEAr: Switch to common clock framework). Signed-off-by:
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