- 17 Jun, 2009 2 commits
-
-
Anton Vorontsov authored
mpc52xx_psc_spi driver is the last user of the legacy activate_cs and deactivate_cs callbacks, so convert the driver to the cs_control hook and remove the legacy callbacks from fsl_spi_platform_data struct. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
-
Grant Likely authored
The xilinxfb driver is improperly casting a physical address to a u32, and the probe routine isn't as straight forward as it could be. (discovered by gcc spitting out warnings on most recent change to xilinxfb driver). This patch fixes the cast and simplifies the probe path. Signed-off-by:
John Linn <john.linn@xilinx.com>
-
- 16 Jun, 2009 30 commits
-
-
Geert Uytterhoeven authored
probe functions should be __devinit initialization functions should be __init Signed-off-by:
Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Acked-by:
Geoff Levand <geoffrey.levand@am.sony.com> Acked-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Without this clobber, mtspr can be re-ordered by gcc vs. surrounding memory accesses. While this might be ok for some cases, it's not in others and I'm not confident that all callers get it right (In fact I'm sure some of them don't). So for now, let's make mtspr() itself contain a memory clobber until we can audit and fix everything, at which point we can remove it if we think it's worth doing so. Signed-off-by: -
Benjamin Herrenschmidt authored
commit 5b7c3c91 introduced an invalid construct in our CPU selection. This caused warnings, though it still appeared to do the right thing. This fixes it properly by having separate formal definitions of PPC_BOOK3S_32 and PPC_BOOK3S_64 and one statement defining PPC_BOOK3S based on the two above. Signed-off-by:
-
Geert Uytterhoeven authored
Signed-off-by:
James E.J. Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by:
-
Michael Ellerman authored
Add the option to build the code under arch/powerpc with -Werror. The intention is to make it harder for people to inadvertantly introduce warnings in the arch/powerpc code. It needs to be configurable so that if a warning is introduced, people can easily work around it while it's being fixed. The option is a negative, ie. don't enable -Werror, so that it will be turned on for allyes and allmodconfig builds. The default is n, in the hope that developers will build with -Werror, that will probably lead to some build breaks, I am prepared to be flamed. It's not enabled for math-emu, which is a steaming pile of warnings. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
-
Dave Mitchell authored
This patch adds the UPF_FIXED_TYPE flag which will bypass the 8250's autoconfig probe for uart type. The uart type identified by the of_serial's parse of the flat device tree will be utilized as defined. Signed-off-by:
Dave Mitchell <dmitchell@amcc.com> Signed-off-by:
-
Mike Frysinger authored
The remove function uses __devexit, so the .remove assignment needs __devexit_p() to fix a build error with hotplug disabled. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
-
Geert Uytterhoeven authored
probe functions should be __devinit Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
-
Timur Tabi authored
The macro spin_event_timeout() takes a condition and timeout value (in microseconds) as parameters. It spins until either the condition is true or the timeout expires. It returns the result of the condition when the loop was terminated. This primary purpose of this macro is to poll on a hardware register until a status bit changes. The timeout ensures that the loop still terminates if the bit doesn't change as expected. This macro makes it easier for driver developers to perform this kind of operation properly. Signed-off-by:
Timur Tabi <timur@freescale.com> Acked-by:
Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by:
-
Sean MacLennan authored
If no device is passed to __dma_alloc_coherent, it defaults to using ISA_DMA_THRESHOLD for the mask. This patch provides a reasonable default rather than 0. Signed-off-by:
Sean MacLennan <smaclennan@pikatech.com> Signed-off-by:
-
Nate Case authored
Some XPedite52xx boards have a legacy boot loader requiring some special care in the boot wrapper. The use of cuboot-85xx is needed to fix up embedded device trees, and a custom link address is specified to accommodate the boot loader and larger kernel image sizes used on X-ES MPC85xx platforms. Signed-off-by:
Nate Case <ncase@xes-inc.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
-
Nate Case authored
Signed-off-by:
-
Nate Case authored
Add device tree source files for various MPC85xx boards from Extreme Engineering Solutions. Supported boards include XPedite5370, XPedite5200, XPedite5301, XPedite5330, and XCalibur1501. Signed-off-by:
-
Nate Case authored
Add support for X-ES single-board computers based on the Freescale MPC85xx processors. Signed-off-by:
-
Heiko Schocher authored
The following series implements basic board support for the kmeter1 board from keymile, based on a MPC8360. This series provides the following functionality: - The board can boot with a serial console on UART1 - Ethernet: UCC1 in RGMII mode UCC2 in RGMII mode UCC4 in RMII mode UCC5 in RMII mode UCC6 in RMII mode UCC7 in RMII mode UCC8 in RMII mode following patch is necessary for working UCC in RMII mode: http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070804.html - Flash accessed via MTD layer On this hardware there is an Intel P30 flash, following patch series is necessary for working with this hardware: http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070624.html - I2C using I2C Bus 1 from the MPC8360 cpu Signed-off-by:Heiko Schocher <hs@denx.de> Signed-off-by:
-
Kevin Hao authored
Add 4 partitions in nor flash. Also fix nor flash bank width bug. The flash is capable of x8/x16 width but is configured for x8. Signed-off-by:
Kevin Hao <kexin.hao@windriver.com> Signed-off-by:
-
mware@internode.on.net authored
Currently the fsl,*lbc devices support 8 banks (ie OR and BR registers). This is adequate for most pq2 and pq3 processors, but not the MPC8280 which has 12 banks. Signed-Off-By:
Mark Ware <mware@elphinstone.net> Signed-off-by:
-
Yang Li authored
Adding failure path for the following two cases. warning: ignoring return value of 'device_add', declared with attribute warn_unused_result warning: ignoring return value of 'sysfs_create_bin_file', declared with attribute warn_unused_result Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
-
Nate Case authored
Some MPC85xx platforms do support 4 ethernet ports, so make sure the boot wrapper fixes up all of them in the fdt. Since MAC addresses are at the end of the bd_t structure there is no harm in expanding to support 4 MAC address on older 85xx systems that might not have that many. Signed-off-by:
-
Dave Liu authored
In HW UART mode the TxBD[READY] is not cleared by H/W (RISC engine) when the user send characters to Tx buffer of QE UART. So, these characters stay on the QE forever, never go to UART line. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
-
Gerhard Pircher authored
Currently the kernel expects the additional four IBAT and DBAT registers to be available, but doesn't enable these registers on 745x CPUs, which have them disabled after reset. Thus set the HIGH_BAT_EN bit in HID0 register, if the corresponding MMU feature is defined. Signed-off-by:
Gerhard Pircher <gerhard_pircher@gmx.net> Signed-off-by:
-
Peter Korsgaard authored
usb0 and usb1 mux settings in the sicrl register were swapped (twice!) in mpc834x_usb_cfg(), leading to various strange issues with fsl-ehci and full speed devices. The USB port config on mpc834x is done using 2 muxes: Port 0 is always used for MPH port 0, and port 1 can either be used for MPH port 1 or DR (unless DR uses UTMI phy or OTG, then it uses both ports) - See 8349 RM figure 1-4.. mpc8349_usb_cfg() had this inverted for the DR, and it also had the bit positions of the usb0 / usb1 mux settings swapped. It would basically work if you specified port1 instead of port0 for the MPH controller (and happened to use ULPI phys), which is what all the 834x dts have done, even though that configuration is physically invalid. Instead fix mpc8349_usb_cfg() and adjust the dts files to match reality. Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
-
leon.woestenberg@gmail.com authored
The PCIe MSI interrupts are missing from the device tree source, and thus were not enabled. This patch adds them. Tested to work on MPC8315E-RDB with custom FPGA PCIe device. Signed-off-by:
Leon Woestenberg <leon@sidebranch.com> Tested-by:
-
Martyn Welch authored
Mappings for temperature sensors (adt7461 and lm92) are missing from the SBC610's DTS file. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
-
Haiying Wang authored
Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
-
Anton Vorontsov authored
As of commit 40461472 ("Update FSL esdhc binding"), we use "fsl,esdhc" compatible entry as a base match. U-Boot will use the same compatible to fixup esdhc nodes. This patch updates 83xx dts files so that they conform to the new bindings. Signed-off-by:
-
Nate Case authored
Some boot loaders may not enable L1 instruction/data cache. Check if data and instruction caches are enabled, and enable them if needed. Signed-off-by:
-
Wolfgang Denk authored
The current device tree for the MPC8272ADS assumes a mapping of 32 MB of NOR flash at 0xFE00.0000, while there are actually only 8 MB on the boards, mapped at 0xFF80.0000. When booting an uImage with such a device tree, the kernel crashes because 0xFE00.0000 is not mapped. Also introduce aliases for serial[01] and ethernet[01]. Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
-
Kumar Gala authored
Add the platform-specific code for enabling SWIOTLB if needed on P2020DS, MPC85xx DS, and MPC85xx MDS boards as they are capable of having >4G of memory. We determine if we need to enable swiotlb based on how much memory is in the board and if it exceeds 4G or what we can map via PCI inbound windows. Signed-off-by: -
Becky Bruce authored
This is the final bit of code to allow enabling swiotlb on mpc86xx. The platform-specific code is very small and consists of enabling SWIOTLB in the config file, registering the swiotlb_setup_bus_notifier initcall, and setting pci_dma_ops to point to swiotlb_pci_dma_ops if we have more memory than can be mapped by the inbound PCI windows. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
-
- 15 Jun, 2009 8 commits
-
-
Geert Uytterhoeven authored
Signed-off-by:
-
Geert Uytterhoeven authored
Add support for caching, to reduce FLASH wear when writing using small blocksizes. As we also don't care anymore about heads and tails in case of partial writes, this greatly simplifies the code for handling writes. Note: We don't bother caching reads smaller than the FLASH chunk size (256 KiB). Signed-off-by:
-
Geert Uytterhoeven authored
Currently the FLASH database is updated by the kernel using file operations, meant for userspace only. While this works for us because copy_{from,to}_user() on powerpc can handle kernel pointers, this is unportable and a bad example. Replace the file operations by callbacks, registered by the ps3flash driver. Signed-off-by: -
Geert Uytterhoeven authored
They were never intended to be exported using EXPORT_SYMBOL() anyway Signed-off-by:
-
Geert Uytterhoeven authored
It reports the failure of a call to lv1_put_iopte(), not lv1_map_device_dma_region(). Signed-off-by:
-
Geert Uytterhoeven authored
probe functions should be __devinit initialization functions should be __init Signed-off-by:
-
Geert Uytterhoeven authored
Signed-off-by:
-
Geert Uytterhoeven authored
Signed-off-by:
-
