- 29 Oct, 2013 25 commits
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Christian Kujau authored
During "make ppc6xx_defconfig" the following happens: HOSTCC scripts/basic/fixdep GEN /usr/local/src/tmp/lnx/Makefile HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf arch/powerpc/configs/ppc6xx_defconfig:74:warning: symbol value 'm' invalid for MCU_MPC8349EMITX Setting CONFIG_MCU_MPC8349EMITX=y in ppc6xx_defconfig makes the warning go away. This too has been reported by Geert Uytterhoeven a long time ago: https://lkml.org/lkml/2011/11/13/11 - I only came across this because I needed a "clean" defconfig for this Powerbook G5. Signed-off-by: Christian Kujau <lists@nerdbynature.de> [scottwood@freescale.com: cleaned up commit message slightly] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Wei Yongjun authored
In case of error, the function platform_device_register_simple() returns RR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Zhao Qiang authored
The P1010RDB-PB is similar to P1010RDB(P1010RDB-PA). So, P1010RDB-PB use the same platform file as P1010RDB. Then Add support for P1010RDB-PB platform. Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Wolfram Sang authored
A few new i2c-drivers came into the kernel which clear the clientdata-pointer on exit or error. This is obsolete meanwhile, the core will do it. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Wei Yongjun authored
Add the missing iounmap() before return from hlwd_pic_init() in the error handling case. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Scott Wood <scottwood@freescale.com>
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LEROY Christophe authored
Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory at bootup instead of 8. It is needed for "big" kernels for instance when activating CONFIG_LOCKDEP_SUPPORT. This needs to be taken into account in init_32 too, otherwise memory allocation soon fails after startup. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Scott Wood <scottwood@freescale.com>
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LEROY Christophe authored
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was missing before the pinning of the third 8Mb page. As the index is decremented module 28 (MD_RSV4D is set) after every DTLB update, the third 8Mbytes page was not pinned. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Kevin Hao authored
Currently all these boards use the same machine struct and also select the same kernel options, so it seems a bit of redundant to keep one separate kernel option for each board. Also update the defconfigs according to this change. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Kevin Hao authored
This file is also used by some RDB and QDS boards. So the name seems not so accurate. Rename it to corenet_generic.c. Also update the function names in this file according to the change. Signed-off-by: Kevin Hao <haokexin@gmail.com>
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Kevin Hao authored
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds, p5020ds, p5040ds, t4240qds and b4qds are almost the same except the machine name. So this introduces a cornet_generic machine to support all these boards to avoid the code duplication. With these changes the file corenet_ds.h becomes useless. Just delete it. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Prabhakar Kushwaha authored
C290PCIe has NAND flash present on IFC Chip Select(CS) 1. So Add "ranges" field for NAND flash on CS1. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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York Sun authored
B4860EMU is a emualtor target with minimum peripherals. It is based on B4860QDS and trimmed down most peripherals due to either not modeled or lack of board level connections. The main purpose of this minimum dts is to speed up booting on emulator. Signed-off-by: York Sun <yorksun@freescale.com> [scottwood@freescale.com: whitespace fix] Signed-off-by: Scott Wood <scottwood@freescale.com>
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York Sun authored
T4240EMU is an emulator target with minimum peripherals. It is based on T4240QDS and trimmed down most peripherals due to either not modeled or lack of board level connections. The main purpose of this minimum dts is to speed up booting on emulator. Signed-off-by: York Sun <yorksun@freescale.com> [scottwood@freescale.com: whitespace fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Scott Wood authored
Commit 9837b43c ("powerpc/85xx: enable coreint for all the 64bit boards") removed the ifdef that avoided coreint on 64-bit, but it missed b4_qds.c. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Kevin Hao <haokexin@gmail.com> Cc: Shaveta Leekha <shaveta@freescale.com>
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LEROY Christophe authored
The commit e0908085 ("powerpc/8xx: Fix regression introduced by cache coherency rewrite") is not needed anymore. The issue was because dcbst wrongly sets the store bit when causing a DTLB error, but this is now fixed by commit 0a2ab51f ("powerpc/8xx: Fixup DAR from buggy dcbX instructions.") which handles the buggy dcbx instructions on data page faults on the 8xx. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [scottwood@freescale.com: fix commit message] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Hongtao Jia authored
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used. The sub-nodes are also reorganized according to right I2C topology. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Shengzhou Liu authored
Enable CONFIG_AT803X_PHY to support AR8030/8033/8035 PHY. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Haijun.Zhang authored
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12" to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Haijun.Zhang authored
Freescale T4240QDS reference board has extra voltage shifters added to allow 3.3V operation, so add 3.3v voltage support for T4240QDS. 1.8v and 3.3v is recommand for eMMC and SDHC card. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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LEROY Christophe authored
This patch modifies the Oops message in case of Software Emulation Exception. The existing message is quite confusing because it refers to FPU Emulation while most often the issue is due to either a non supported instruction (not necessarily FPU related) or a stale instruction due to HW issues. The new message tries to be more generic in order to make the user understand that the Oops is due to something wrong with an instruction, not necessarily due to an FPU instruction. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Suzuki Poulose authored
The regset defintion for SPE doesn't have the core_note_type set, which prevents it from being dumped. Add the note type NT_PPC_SPE for SPE regset. Signed-off-by: Suzuki K Poulose <suzuki@in.ibm.com> Cc: Roland McGrath <roland@hack.frob.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Lijun Pan authored
bsc9131 device tree does not have these properties. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Lijun Pan authored
b4420 and b4860 device trees do not have these properties. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Chunhe Lan authored
Freescale platform has class code = 0x0b2000, when it boots. This makes kernel PCI bus code to setup these devices resulting into the following notice information when trying to enable them: pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't match header type 01) The above information is outputted by judging value of dev->class before pci_setup_device() function, and the DECLARE_PCI_FIXUP_HEADER quirk runs after pci_setup_device() function. But the DECLARE_PCI_FIXUP_EARLY quirk runs before judging value of dev->class and pci_setup_device() function. So we use the DECLARE_PCI_FIXUP_EARLY macro to fix this issue. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Minghuan Lian authored
For B4 platform, MPIC EISR register is in reversed bitmap order, instead of "Error interrupt source 0-31. Bit 0 represents SRC0." the correct ordering is "Error interrupt source 0-31. Bit 0 represents SRC31." This patch is to fix sRIO EISR bit value of error interrupt in dts node. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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- 18 Oct, 2013 5 commits
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James Yang authored
BookE version of user_disable_single_step() clears DBCR0_IC for the instruction completion debug, but did not also clear DBCR0_BT for the branch taken exception. This behavior was lost by the 2/2010 patch. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Bharat Bhushan authored
KVM need this function when switching from vcpu to user-space thread. My subsequent patch will use this function. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Bharat Bhushan authored
This way we can use same data type struct with KVM and also help in using other debug related function. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Acked-by: Michael Neuling <mikey@neuling.org> [scottwood@freescale.com: removed obvious debug_reg comment] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Bharat Bhushan authored
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Tiejun Chen authored
Use DEFINE_PER_CPU to allocate thread_info statically instead of kmalloc(). This can avoid introducing more memory check codes. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> [scottwood@freescale.com: wrapped long line] Signed-off-by: Scott Wood <scottwood@freescale.com>
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- 16 Oct, 2013 4 commits
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James Yang authored
Reserved fields of the sync instruction have been used for other instructions (e.g. lwsync). On processors that do not support variants of the sync instruction, emulate it by executing a sync to subsume the effect of the intended instruction. Signed-off-by: James Yang <James.Yang@freescale.com> [scottwood@freescale.com: whitespace and subject line fix] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Mihai Caraman authored
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use common defines to indentify these numbers. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> [scottwood@freescale.com: fixed space-before-tab] Signed-off-by: Scott Wood <scottwood@freescale.com>
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Mihai Caraman authored
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use common defines to indentify these numbers. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Paul Bolle authored
The Kconfig entry that allows to "Distribute interrupts on all CPUs by default" has a (negative) dependency on MV64360. But that Kconfig symbol was removed in v2.6.27, which means that this dependency has evaluated to true ever since. It can be removed too. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Scott Wood <scottwood@freescale.com>
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- 11 Oct, 2013 6 commits
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Benjamin Herrenschmidt authored
Topic branch for commits that the KVM tree might want to pull in separately. Hand merged a few files due to conflicts with the LE stuff Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Paul Mackerras authored
This provides a facility which is intended for use by KVM, where the contents of the FP/VSX and VMX (Altivec) registers can be saved away to somewhere other than the thread_struct when kernel code wants to use floating point or VMX instructions. This is done by providing a pointer in the thread_struct to indicate where the state should be saved to. The giveup_fpu() and giveup_altivec() functions test these pointers and save state to the indicated location if they are non-NULL. Note that the MSR_FP/VEC bits in task->thread.regs->msr are still used to indicate whether the CPU register state is live, even when an alternate save location is being used. This also provides load_fp_state() and load_vr_state() functions, which load up FP/VSX and VMX state from memory into the CPU registers, and corresponding store_fp_state() and store_vr_state() functions, which store FP/VSX and VMX state into memory from the CPU registers. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Paul Mackerras authored
This creates new 'thread_fp_state' and 'thread_vr_state' structures to store FP/VSX state (including FPSCR) and Altivec/VSX state (including VSCR), and uses them in the thread_struct. In the thread_fp_state, the FPRs and VSRs are represented as u64 rather than double, since we rarely perform floating-point computations on the values, and this will enable the structures to be used in KVM code as well. Similarly FPSCR is now a u64 rather than a structure of two 32-bit values. This takes the offsets out of the macros such as SAVE_32FPRS, REST_32FPRS, etc. This enables the same macros to be used for normal and transactional state, enabling us to delete the transactional versions of the macros. This also removes the unused do_load_up_fpu and do_load_up_altivec, which were in fact buggy since they didn't create large enough stack frames to account for the fact that load_up_fpu and load_up_altivec are not designed to be called from C and assume that their caller's stack frame is an interrupt frame. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Alexey Kardashevskiy authored
The existing TCE machine calls (tce_build and tce_free) only support virtual mode as they call __raw_writeq for TCE invalidation what fails in real mode. This introduces tce_build_rm and tce_free_rm real mode versions which do mostly the same but use "Store Doubleword Caching Inhibited Indexed" instruction for TCE invalidation. This new feature is going to be utilized by real mode support of VFIO. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Alexey Kardashevskiy authored
The current VFIO-on-POWER implementation supports only user mode driven mapping, i.e. QEMU is sending requests to map/unmap pages. However this approach is really slow, so we want to move that to KVM. Since H_PUT_TCE can be extremely performance sensitive (especially with network adapters where each packet needs to be mapped/unmapped) we chose to implement that as a "fast" hypercall directly in "real mode" (processor still in the guest context but MMU off). To be able to do that, we need to provide some facilities to access the struct page count within that real mode environment as things like the sparsemem vmemmap mappings aren't accessible. This adds an API function realmode_pfn_to_page() to get page struct when MMU is off. This adds to MM a new function put_page_unless_one() which drops a page if counter is bigger than 1. It is going to be used when MMU is off (for example, real mode on PPC64) and we want to make sure that page release will not happen in real mode as it may crash the kernel in a horrible way. CONFIG_SPARSEMEM_VMEMMAP and CONFIG_FLATMEM are supported. Cc: linux-mm@kvack.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Andrew Morton <akpm@linux-foundation.org> Reviewed-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Alexey Kardashevskiy authored
This adds hash_for_each_possible_rcu_notrace() which is basically a notrace clone of hash_for_each_possible_rcu() which cannot be used in real mode due to its tracing/debugging capability. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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