- 13 Sep, 2018 37 commits
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4c529600 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support") Signed-off-by: -
Geert Uytterhoeven authored
Signed-off-by:
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Eugeniu Rosca authored
This is based on the existing KF device tree sources: $ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts Signed-off-by:
Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by:
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Sergei Shtylyov authored
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
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Biju Das authored
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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Biju Das authored
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Biju Das authored
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Fabrizio Castro authored
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly to what was done for the r8a7796 with commit 41dbbf0c ("arm64: dts: r8a7796: Add FCPF and FCPV instances"), commit 69490bc9 ("arm64: dts: renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0 ("arm64: dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0"). Signed-off-by:
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Biju Das authored
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1). This work is based on similar work done on the R8A7796 SoC by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>. Signed-off-by:
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Fabrizio Castro authored
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1) device tree. Signed-off-by:
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Biju Das authored
This patch adds definitions for L2 cache for the Cortex-A53 CPU cores (512 KiB in size, organized as 32 KiB x 16 ways), adds Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57 + 4 x Cortex-A53), and finally enables the performance monitor unit for the Cortex-A53 cores on the R8A774A1 SoC. Based on work done for r8a7796 SoC. Signed-off-by:
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Biju Das authored
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC. Based on several similar patches of the R8A7796 device tree by Geert Uytterhoeven <geert+renesas@glider.be> and Simon Horman <horms+renesas@verge.net.au>. Signed-off-by:
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Fabrizio Castro authored
Add r8a774a1 IPMMU nodes. Signed-off-by:
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Biju Das authored
Add thermal support for R8A774A1 (RZ/G2M) SoC. Based on the work done for r8a7796 SoC. Signed-off-by:
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Biju Das authored
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS) devices nodes to the r8a774a1 device tree. Signed-off-by:
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Fabrizio Castro authored
Add SDHI nodes to the DT of the r8a774a1 SoC. Signed-off-by:
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Fabrizio Castro authored
Add GPIO device nodes to the DT of the r8a774a1 SoC. Signed-off-by:
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Fabrizio Castro authored
This patch adds pinctrl device node for R8A774A1 SoC. Signed-off-by:
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Biju Das authored
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G2M (r8a774a1) SoC. Signed-off-by:
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Fabrizio Castro authored
This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by:
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Biju Das authored
Add support for the Interrupt Controller for External Devices (INTC-EX) on RZ/G2M. Signed-off-by:
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Fabrizio Castro authored
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports, incl. clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by:
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Biju Das authored
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC. Signed-off-by:
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Sergei Shtylyov authored
Define the Condor/V3HSK board dependent parts of the DU and LVDS device nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI transmitter... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Sergei Shtylyov authored
Add the eMMC chip support for the V3M Started Kit board. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A77970 part of the MMC0 (SDHI2) device node. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by:
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Dien Pham authored
This patch adds OPPs table for CA57{0,1} cpu devices Signed-off-by:Dien Pham <dien.pham.ry@renesas.com> Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by:
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Eugeniu Rosca authored
Allow the bare M3-N-based ULCB board to boot. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
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Eugeniu Rosca authored
According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN interfaces, similar to H3, M3-W and other SoCs from the same family. Add CAN placeholder nodes to avoid below DTC errors: Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not found Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not found These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts. Fix them beforehand. CAN support is inspired from below commits: - v4.7 commit 308b7e4b ("arm64: dts: r8a7795: Add CAN support") - v4.11 commit 909c1625 ("arm64: dts: r8a7796: Add CAN support") - v4.12 commit bec0948e ("arm64: dts: r8a7796: Add reset control properties") Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> [simon: make placeholder minimal by only including reg property] Signed-off-by:
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Magnus Damm authored
For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W. This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
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Biju Das authored
Basic support for the RZ/G2M SoC. Signed-off-by:
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Kieran Bingham authored
Ensure that the ADV748x device addresses do not conflict, and group them together (visually in i2cdetect) Signed-off-by:
Kieran Bingham <kieran.bingham@ideasonboard.com> Signed-off-by:
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Sergei Shtylyov authored
Describe the CSI2 and VIN (and their interconnections) in the R8A77980 device tree. Signed-off-by:
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Wolfram Sang authored
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched off for that to work. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
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Takeshi Kihara authored
This patch adds SATA controller node for the R8A77965 SoC. Signed-off-by:
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- 11 Sep, 2018 3 commits
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Sergei Shtylyov authored
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0 device trees, according to the alphanumeric node sorting rule... Signed-off-by: -
Sergei Shtylyov authored
The IPMMU nodes should follow the GEther node, not the CAN-FD node, according to the <unit-address> part of the startng IPMMU-DS1 node. While moving the nodes, also do sort them by label alphanumerically... Signed-off-by:
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Yoshihiro Shimoda authored
This patch adds PWM device nodes and enables PWM3 and PWM5 for R-Car E3 Ebisu board. These devices are used for backlight control. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
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