qla_os.c 231 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * QLogic Fibre Channel HBA Driver
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 * Copyright (c)  2003-2014 QLogic Corporation
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 */
#include "qla_def.h"

#include <linux/moduleparam.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
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#include <linux/kthread.h>
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#include <linux/mutex.h>
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#include <linux/kobject.h>
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#include <linux/slab.h>
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#include <linux/blk-mq-pci.h>
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#include <linux/refcount.h>
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#include <linux/crash_dump.h>
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#include <linux/trace_events.h>
#include <linux/trace.h>
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#include <scsi/scsi_tcq.h>
#include <scsi/scsicam.h>
#include <scsi/scsi_transport.h>
#include <scsi/scsi_transport_fc.h>

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#include "qla_target.h"

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/*
 * Driver version
 */
char qla2x00_version_str[40];

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static int apidev_major;

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/*
 * SRB allocation cache
 */
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struct kmem_cache *srb_cachep;
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static struct trace_array *qla_trc_array;
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int ql2xfulldump_on_mpifail;
module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
		 "Set this to take full dump on MPI hang.");

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int ql2xenforce_iocb_limit = 1;
module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(ql2xenforce_iocb_limit,
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		 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)");
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/*
 * CT6 CTX allocation cache
 */
static struct kmem_cache *ctx_cachep;
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/*
 * error level for logging
 */
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uint ql_errlev = 0x8001;
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int ql2xsecenable;
module_param(ql2xsecenable, int, S_IRUGO);
MODULE_PARM_DESC(ql2xsecenable,
	"Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");

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static int ql2xenableclass2;
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module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
MODULE_PARM_DESC(ql2xenableclass2,
		"Specify if Class 2 operations are supported from the very "
		"beginning. Default is 0 - class 2 not supported.");

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int ql2xlogintimeout = 20;
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module_param(ql2xlogintimeout, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xlogintimeout,
		"Login timeout value in seconds.");

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int qlport_down_retry;
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module_param(qlport_down_retry, int, S_IRUGO);
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MODULE_PARM_DESC(qlport_down_retry,
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		"Maximum number of command retries to a port that returns "
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		"a PORT-DOWN status.");

int ql2xplogiabsentdevice;
module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xplogiabsentdevice,
		"Option to enable PLOGI to devices that are not present after "
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		"a Fabric scan.  This is needed for several broken switches. "
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		"Default is 0 - no PLOGI. 1 - perform PLOGI.");
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int ql2xloginretrycount;
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module_param(ql2xloginretrycount, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xloginretrycount,
		"Specify an alternate value for the NVRAM login retry count.");

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int ql2xallocfwdump = 1;
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module_param(ql2xallocfwdump, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xallocfwdump,
		"Option to enable allocation of memory for a firmware dump "
		"during HBA initialization.  Memory allocation requirements "
		"vary by ISP type.  Default is 1 - allocate memory.");

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int ql2xextended_error_logging;
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module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
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module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(ql2xextended_error_logging,
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		"Option to enable extended error logging,\n"
		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
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		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
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		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
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		"\t\t0x1e400000 - Preferred value for capturing essential "
		"debug information (equivalent to old "
		"ql2xextended_error_logging=1).\n"
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		"\t\tDo LOGICAL OR of the value to enable more than one level");
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int ql2xextended_error_logging_ktrace = 1;
module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
		"Same BIT definiton as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");

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int ql2xshiftctondsd = 6;
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module_param(ql2xshiftctondsd, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xshiftctondsd,
		"Set to control shifting of command type processing "
		"based on total number of SG elements.");

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int ql2xfdmienable = 1;
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module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
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module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(ql2xfdmienable,
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		"Enables FDMI registrations. "
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		"0 - no FDMI registrations. "
		"1 - provide FDMI registrations (default).");
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#define MAX_Q_DEPTH	64
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static int ql2xmaxqdepth = MAX_Q_DEPTH;
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module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xmaxqdepth,
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		"Maximum queue depth to set for each LUN. "
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		"Default is 64.");
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int ql2xenabledif = 2;
module_param(ql2xenabledif, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xenabledif,
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		" Enable T10-CRC-DIF:\n"
		" Default is 2.\n"
		"  0 -- No DIF Support\n"
		"  1 -- Enable DIF for all types\n"
		"  2 -- Enable DIF for all types, except Type 0.\n");
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#if (IS_ENABLED(CONFIG_NVME_FC))
int ql2xnvmeenable = 1;
#else
int ql2xnvmeenable;
#endif
module_param(ql2xnvmeenable, int, 0644);
MODULE_PARM_DESC(ql2xnvmeenable,
    "Enables NVME support. "
    "0 - no NVMe.  Default is Y");

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int ql2xenablehba_err_chk = 2;
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module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xenablehba_err_chk,
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		" Enable T10-CRC-DIF Error isolation by HBA:\n"
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		" Default is 2.\n"
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		"  0 -- Error isolation disabled\n"
		"  1 -- Error isolation enabled only for DIX Type 0\n"
		"  2 -- Error isolation enabled for all Types\n");
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int ql2xiidmaenable = 1;
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module_param(ql2xiidmaenable, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xiidmaenable,
		"Enables iIDMA settings "
		"Default is 1 - perform iIDMA. 0 - no iIDMA.");

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int ql2xmqsupport = 1;
module_param(ql2xmqsupport, int, S_IRUGO);
MODULE_PARM_DESC(ql2xmqsupport,
		"Enable on demand multiple queue pairs support "
		"Default is 1 for supported. "
		"Set it to 0 to turn off mq qpair support.");
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int ql2xfwloadbin;
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module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
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module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(ql2xfwloadbin,
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		"Option to specify location from which to load ISP firmware:.\n"
		" 2 -- load firmware via the request_firmware() (hotplug).\n"
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		"      interface.\n"
		" 1 -- load firmware from flash.\n"
		" 0 -- use default semantics.\n");

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int ql2xetsenable;
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module_param(ql2xetsenable, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xetsenable,
		"Enables firmware ETS burst."
		"Default is 0 - skip ETS enablement.");

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int ql2xdbwr = 1;
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module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(ql2xdbwr,
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		"Option to specify scheme for request queue posting.\n"
		" 0 -- Regular doorbell.\n"
		" 1 -- CAMRAM doorbell (faster).\n");
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int ql2xgffidenable;
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module_param(ql2xgffidenable, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xgffidenable,
		"Enables GFF_ID checks of port type. "
		"Default is 0 - Do not use GFF_ID information.");
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int ql2xasynctmfenable = 1;
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module_param(ql2xasynctmfenable, int, S_IRUGO);
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MODULE_PARM_DESC(ql2xasynctmfenable,
		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
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		"Default is 1 - Issue TM IOCBs via mailbox mechanism.");
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int ql2xdontresethba;
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module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(ql2xdontresethba,
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		"Option to specify reset behaviour.\n"
		" 0 (Default) -- Reset on failure.\n"
		" 1 -- Do not reset on failure.\n");
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uint64_t ql2xmaxlun = MAX_LUNS;
module_param(ql2xmaxlun, ullong, S_IRUGO);
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MODULE_PARM_DESC(ql2xmaxlun,
		"Defines the maximum LU number to register with the SCSI "
		"midlayer. Default is 65535.");

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int ql2xmdcapmask = 0x1F;
module_param(ql2xmdcapmask, int, S_IRUGO);
MODULE_PARM_DESC(ql2xmdcapmask,
		"Set the Minidump driver capture mask level. "
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		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
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int ql2xmdenable = 1;
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module_param(ql2xmdenable, int, S_IRUGO);
MODULE_PARM_DESC(ql2xmdenable,
		"Enable/disable MiniDump. "
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		"0 - MiniDump disabled. "
		"1 (Default) - MiniDump enabled.");
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int ql2xexlogins;
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module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xexlogins,
		 "Number of extended Logins. "
		 "0 (Default)- Disabled.");

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int ql2xexchoffld = 1024;
module_param(ql2xexchoffld, uint, 0644);
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MODULE_PARM_DESC(ql2xexchoffld,
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	"Number of target exchanges.");

int ql2xiniexchg = 1024;
module_param(ql2xiniexchg, uint, 0644);
MODULE_PARM_DESC(ql2xiniexchg,
	"Number of initiator exchanges.");
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int ql2xfwholdabts;
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module_param(ql2xfwholdabts, int, S_IRUGO);
MODULE_PARM_DESC(ql2xfwholdabts,
		"Allow FW to hold status IOCB until ABTS rsp received. "
		"0 (Default) Do not set fw option. "
		"1 - Set fw option to hold ABTS.");

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int ql2xmvasynctoatio = 1;
module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(ql2xmvasynctoatio,
		"Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
		"0 (Default). Do not move IOCBs"
		"1 - Move IOCBs.");

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int ql2xautodetectsfp = 1;
module_param(ql2xautodetectsfp, int, 0444);
MODULE_PARM_DESC(ql2xautodetectsfp,
		 "Detect SFP range and set appropriate distance.\n"
		 "1 (Default): Enable\n");

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int ql2xenablemsix = 1;
module_param(ql2xenablemsix, int, 0444);
MODULE_PARM_DESC(ql2xenablemsix,
		 "Set to enable MSI or MSI-X interrupt mechanism.\n"
		 " Default is 1, enable MSI-X interrupt mechanism.\n"
		 " 0 -- enable traditional pin-based mechanism.\n"
		 " 1 -- enable MSI-X interrupt mechanism.\n"
		 " 2 -- enable MSI interrupt mechanism.\n");

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int qla2xuseresexchforels;
module_param(qla2xuseresexchforels, int, 0444);
MODULE_PARM_DESC(qla2xuseresexchforels,
		 "Reserve 1/2 of emergency exchanges for ELS.\n"
		 " 0 (default): disabled");

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static int ql2xprotmask;
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module_param(ql2xprotmask, int, 0644);
MODULE_PARM_DESC(ql2xprotmask,
		 "Override DIF/DIX protection capabilities mask\n"
		 "Default is 0 which sets protection mask based on "
		 "capabilities reported by HBA firmware.\n");

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static int ql2xprotguard;
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module_param(ql2xprotguard, int, 0644);
MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
		 "  0 -- Let HBA firmware decide\n"
		 "  1 -- Force T10 CRC\n"
		 "  2 -- Force IP checksum\n");

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int ql2xdifbundlinginternalbuffers;
module_param(ql2xdifbundlinginternalbuffers, int, 0644);
MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
    "Force using internal buffers for DIF information\n"
    "0 (Default). Based on check.\n"
    "1 Force using internal buffers\n");

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int ql2xsmartsan;
module_param(ql2xsmartsan, int, 0444);
module_param_named(smartsan, ql2xsmartsan, int, 0444);
MODULE_PARM_DESC(ql2xsmartsan,
		"Send SmartSAN Management Attributes for FDMI Registration."
		" Default is 0 - No SmartSAN registration,"
		" 1 - Register SmartSAN Management Attributes.");

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int ql2xrdpenable;
module_param(ql2xrdpenable, int, 0444);
module_param_named(rdpenable, ql2xrdpenable, int, 0444);
MODULE_PARM_DESC(ql2xrdpenable,
		"Enables RDP responses. "
		"0 - no RDP responses (default). "
		"1 - provide RDP responses.");
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int ql2xabts_wait_nvme = 1;
module_param(ql2xabts_wait_nvme, int, 0444);
MODULE_PARM_DESC(ql2xabts_wait_nvme,
		 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");

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static u32 ql2xdelay_before_pci_error_handling = 5;
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module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
	"Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");

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static void qla2x00_clear_drv_active(struct qla_hw_data *);
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static void qla2x00_free_device(scsi_qla_host_t *);
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static int qla2xxx_map_queues(struct Scsi_Host *shost);
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static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
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u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
module_param(ql2xnvme_queues, uint, S_IRUGO);
MODULE_PARM_DESC(ql2xnvme_queues,
	"Number of NVMe Queues that can be configured.\n"
	"Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
	"1 - Minimum number of queues supported\n"
	"8 - Default value");
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static struct scsi_transport_template *qla2xxx_transport_template = NULL;
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struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
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/* TODO Convert to inlines
 *
 * Timer routines
 */

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__inline__ void
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qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
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{
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	timer_setup(&vha->timer, qla2x00_timer, 0);
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	vha->timer.expires = jiffies + interval * HZ;
	add_timer(&vha->timer);
	vha->timer_active = 1;
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}

static inline void
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qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
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{
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	/* Currently used for 82XX only. */
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	if (vha->device_flags & DFLG_DEV_FAILED) {
		ql_dbg(ql_dbg_timer, vha, 0x600d,
		    "Device in a failed state, returning.\n");
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		return;
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	}
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	mod_timer(&vha->timer, jiffies + interval * HZ);
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}

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static __inline__ void
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qla2x00_stop_timer(scsi_qla_host_t *vha)
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{
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	del_timer_sync(&vha->timer);
	vha->timer_active = 0;
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}

static int qla2x00_do_dpc(void *data);

static void qla2x00_rst_aen(scsi_qla_host_t *);

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static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
	struct req_que **, struct rsp_que **);
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static void qla2x00_free_fw_dump(struct qla_hw_data *);
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static void qla2x00_mem_free(struct qla_hw_data *);
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int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
	struct qla_qpair *qpair);
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/* -------------------------------------------------------------------------- */
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static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
    struct rsp_que *rsp)
{
	struct qla_hw_data *ha = vha->hw;
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	rsp->qpair = ha->base_qpair;
	rsp->req = req;
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	ha->base_qpair->hw = ha;
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	ha->base_qpair->req = req;
	ha->base_qpair->rsp = rsp;
	ha->base_qpair->vha = vha;
	ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
	ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
	ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
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	ha->base_qpair->srb_mempool = ha->srb_mempool;
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	INIT_LIST_HEAD(&ha->base_qpair->hints_list);
	ha->base_qpair->enable_class_2 = ql2xenableclass2;
	/* init qpair to this cpu. Will adjust at run time. */
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	qla_cpu_update(rsp->qpair, raw_smp_processor_id());
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	ha->base_qpair->pdev = ha->pdev;

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	if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
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		ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
}

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static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
				struct rsp_que *rsp)
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{
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	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
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	ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
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				GFP_KERNEL);
	if (!ha->req_q_map) {
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		ql_log(ql_log_fatal, vha, 0x003b,
		    "Unable to allocate memory for request queue ptrs.\n");
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		goto fail_req_map;
	}

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	ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
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				GFP_KERNEL);
	if (!ha->rsp_q_map) {
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		ql_log(ql_log_fatal, vha, 0x003c,
		    "Unable to allocate memory for response queue ptrs.\n");
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		goto fail_rsp_map;
	}
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	ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
	if (ha->base_qpair == NULL) {
		ql_log(ql_log_warn, vha, 0x00e0,
		    "Failed to allocate base queue pair memory.\n");
		goto fail_base_qpair;
	}

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	qla_init_base_qpair(vha, req, rsp);
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	if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
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		ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
			GFP_KERNEL);
		if (!ha->queue_pair_map) {
			ql_log(ql_log_fatal, vha, 0x0180,
			    "Unable to allocate memory for queue pair ptrs.\n");
			goto fail_qpair_map;
		}
	}

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	/*
	 * Make sure we record at least the request and response queue zero in
	 * case we need to free them if part of the probe fails.
	 */
	ha->rsp_q_map[0] = rsp;
	ha->req_q_map[0] = req;
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	set_bit(0, ha->rsp_qid_map);
	set_bit(0, ha->req_qid_map);
485
	return 0;
486

487
fail_qpair_map:
488 489 490
	kfree(ha->base_qpair);
	ha->base_qpair = NULL;
fail_base_qpair:
491 492
	kfree(ha->rsp_q_map);
	ha->rsp_q_map = NULL;
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fail_rsp_map:
	kfree(ha->req_q_map);
	ha->req_q_map = NULL;
fail_req_map:
	return -ENOMEM;
}

500
static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
501
{
502 503 504 505 506 507
	if (IS_QLAFX00(ha)) {
		if (req && req->ring_fx00)
			dma_free_coherent(&ha->pdev->dev,
			    (req->length_fx00 + 1) * sizeof(request_t),
			    req->ring_fx00, req->dma_fx00);
	} else if (req && req->ring)
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		dma_free_coherent(&ha->pdev->dev,
		(req->length + 1) * sizeof(request_t),
		req->ring, req->dma);

512
	if (req)
513
		kfree(req->outstanding_cmds);
514 515

	kfree(req);
516 517
}

518 519
static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
{
520
	if (IS_QLAFX00(ha)) {
521
		if (rsp && rsp->ring_fx00)
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			dma_free_coherent(&ha->pdev->dev,
			    (rsp->length_fx00 + 1) * sizeof(request_t),
			    rsp->ring_fx00, rsp->dma_fx00);
	} else if (rsp && rsp->ring) {
526 527 528
		dma_free_coherent(&ha->pdev->dev,
		(rsp->length + 1) * sizeof(response_t),
		rsp->ring, rsp->dma);
529
	}
530
	kfree(rsp);
531 532
}

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static void qla2x00_free_queues(struct qla_hw_data *ha)
{
	struct req_que *req;
	struct rsp_que *rsp;
	int cnt;
538
	unsigned long flags;
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	if (ha->queue_pair_map) {
		kfree(ha->queue_pair_map);
		ha->queue_pair_map = NULL;
	}
	if (ha->base_qpair) {
		kfree(ha->base_qpair);
		ha->base_qpair = NULL;
	}

549
	spin_lock_irqsave(&ha->hardware_lock, flags);
550
	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
551 552 553
		if (!test_bit(cnt, ha->req_qid_map))
			continue;

554
		req = ha->req_q_map[cnt];
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		clear_bit(cnt, ha->req_qid_map);
		ha->req_q_map[cnt] = NULL;

		spin_unlock_irqrestore(&ha->hardware_lock, flags);
559
		qla2x00_free_req_que(ha, req);
560
		spin_lock_irqsave(&ha->hardware_lock, flags);
561
	}
562 563
	spin_unlock_irqrestore(&ha->hardware_lock, flags);

564 565
	kfree(ha->req_q_map);
	ha->req_q_map = NULL;
566

567 568

	spin_lock_irqsave(&ha->hardware_lock, flags);
569
	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
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		if (!test_bit(cnt, ha->rsp_qid_map))
			continue;

573
		rsp = ha->rsp_q_map[cnt];
574
		clear_bit(cnt, ha->rsp_qid_map);
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		ha->rsp_q_map[cnt] =  NULL;
		spin_unlock_irqrestore(&ha->hardware_lock, flags);
577
		qla2x00_free_rsp_que(ha, rsp);
578
		spin_lock_irqsave(&ha->hardware_lock, flags);
579
	}
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	spin_unlock_irqrestore(&ha->hardware_lock, flags);

582 583
	kfree(ha->rsp_q_map);
	ha->rsp_q_map = NULL;
584 585
}

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static char *
587
qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
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{
589
	struct qla_hw_data *ha = vha->hw;
590
	static const char *const pci_bus_modes[] = {
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		"33", "66", "100", "133",
	};
	uint16_t pci_bus;

	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
	if (pci_bus) {
597 598
		snprintf(str, str_len, "PCI-X (%s MHz)",
			 pci_bus_modes[pci_bus]);
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	} else {
		pci_bus = (ha->pci_attr & BIT_8) >> 8;
601
		snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
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	}

604
	return str;
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}

607
static char *
608
qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
609
{
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	static const char *const pci_bus_modes[] = {
		"33", "66", "100", "133",
	};
613
	struct qla_hw_data *ha = vha->hw;
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	uint32_t pci_bus;

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	if (pci_is_pcie(ha->pdev)) {
		uint32_t lstat, lspeed, lwidth;
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		const char *speed_str;
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		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
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		switch (lspeed) {
		case 1:
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			speed_str = "2.5GT/s";
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			break;
		case 2:
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			speed_str = "5.0GT/s";
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			break;
		case 3:
632
			speed_str = "8.0GT/s";
633
			break;
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		case 4:
			speed_str = "16.0GT/s";
			break;
637
		default:
638
			speed_str = "<unknown>";
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			break;
		}
641
		snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
642 643 644 645 646

		return str;
	}

	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
647 648 649 650 651 652 653
	if (pci_bus == 0 || pci_bus == 8)
		snprintf(str, str_len, "PCI (%s MHz)",
			 pci_bus_modes[pci_bus >> 3]);
	else
		snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
			 pci_bus & 4 ? 2 : 1,
			 pci_bus_modes[pci_bus & 3]);
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	return str;
}

658
static char *
659
qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
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{
	char un_str[10];
662
	struct qla_hw_data *ha = vha->hw;
663

664 665
	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
	    ha->fw_minor_version, ha->fw_subminor_version);
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	if (ha->fw_attributes & BIT_9) {
		strcat(str, "FLX");
		return (str);
	}

	switch (ha->fw_attributes & 0xFF) {
	case 0x7:
		strcat(str, "EF");
		break;
	case 0x17:
		strcat(str, "TP");
		break;
	case 0x37:
		strcat(str, "IP");
		break;
	case 0x77:
		strcat(str, "VI");
		break;
	default:
		sprintf(un_str, "(%x)", ha->fw_attributes);
		strcat(str, un_str);
		break;
	}
	if (ha->fw_attributes & 0x100)
		strcat(str, "X");

	return (str);
}

696
static char *
697
qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
698
{
699
	struct qla_hw_data *ha = vha->hw;
700

701
	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
702
	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
703 704 705
	return str;
}

706
void qla2x00_sp_free_dma(srb_t *sp)
707
{
708
	struct qla_hw_data *ha = sp->vha->hw;
709
	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
710

711 712 713
	if (sp->flags & SRB_DMA_VALID) {
		scsi_dma_unmap(cmd);
		sp->flags &= ~SRB_DMA_VALID;
714
	}
715

716 717 718 719 720 721 722 723
	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
	}

	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
		/* List assured to be having elements */
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		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
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		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
	}

	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
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		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
730 731

		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
732 733 734 735
		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
	}

	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
736
		struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
737

738
		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
739
		    ctx1->fcp_cmnd_dma);
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		list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
		ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
		ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
		mempool_free(ctx1, ha->ctx_mempool);
	}
}

747
void qla2x00_sp_compl(srb_t *sp, int res)
748 749
{
	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
750
	struct completion *comp = sp->comp;
751

752 753
	/* kref: INIT */
	kref_put(&sp->cmd_kref, qla2x00_sp_release);
754
	cmd->result = res;
755
	sp->type = 0;
756
	scsi_done(cmd);
757 758
	if (comp)
		complete(comp);
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}

761
void qla2xxx_qpair_sp_free_dma(srb_t *sp)
762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778
{
	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
	struct qla_hw_data *ha = sp->fcport->vha->hw;

	if (sp->flags & SRB_DMA_VALID) {
		scsi_dma_unmap(cmd);
		sp->flags &= ~SRB_DMA_VALID;
	}

	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
	}

	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
		/* List assured to be having elements */
779
		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
780 781 782
		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
	}

783
	if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
784
		struct crc_context *difctx = sp->u.scmd.crc_ctx;
785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816
		struct dsd_dma *dif_dsd, *nxt_dsd;

		list_for_each_entry_safe(dif_dsd, nxt_dsd,
		    &difctx->ldif_dma_hndl_list, list) {
			list_del(&dif_dsd->list);
			dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
			    dif_dsd->dsd_list_dma);
			kfree(dif_dsd);
			difctx->no_dif_bundl--;
		}

		list_for_each_entry_safe(dif_dsd, nxt_dsd,
		    &difctx->ldif_dsd_list, list) {
			list_del(&dif_dsd->list);
			dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
			    dif_dsd->dsd_list_dma);
			kfree(dif_dsd);
			difctx->no_ldif_dsd--;
		}

		if (difctx->no_ldif_dsd) {
			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
			    "%s: difctx->no_ldif_dsd=%x\n",
			    __func__, difctx->no_ldif_dsd);
		}

		if (difctx->no_dif_bundl) {
			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
			    "%s: difctx->no_dif_bundl=%x\n",
			    __func__, difctx->no_dif_bundl);
		}
		sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
817
	}
818 819

	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
820
		struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
821 822 823 824 825 826 827 828 829 830 831

		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
		    ctx1->fcp_cmnd_dma);
		list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
		ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
		ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
		mempool_free(ctx1, ha->ctx_mempool);
		sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
	}

	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
832
		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
833

834
		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
835 836
		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
	}
837 838
}

839
void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
840 841
{
	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
842
	struct completion *comp = sp->comp;
843

844 845
	/* ref: INIT */
	kref_put(&sp->cmd_kref, qla2x00_sp_release);
846
	cmd->result = res;
847
	sp->type = 0;
848
	scsi_done(cmd);
849 850
	if (comp)
		complete(comp);
851 852
}

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853
static int
854
qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
855
{
856
	scsi_qla_host_t *vha = shost_priv(host);
857
	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
858
	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
859 860
	struct qla_hw_data *ha = vha->hw;
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
861 862 863
	srb_t *sp;
	int rval;

864 865
	if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
	    WARN_ON_ONCE(!rport)) {
866 867 868 869
		cmd->result = DID_NO_CONNECT << 16;
		goto qc24_fail_command;
	}

870
	if (ha->mqenable) {
871 872 873 874
		uint32_t tag;
		uint16_t hwq;
		struct qla_qpair *qpair = NULL;

875
		tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
876 877
		hwq = blk_mq_unique_tag_to_hwq(tag);
		qpair = ha->queue_pair_map[hwq];
878 879 880

		if (qpair)
			return qla2xxx_mqueuecommand(host, cmd, qpair);
881 882
	}

883
	if (ha->flags.eeh_busy) {
884
		if (ha->flags.pci_channel_io_perm_failure) {
885
			ql_dbg(ql_dbg_aer, vha, 0x9010,
886 887
			    "PCI Channel IO permanent failure, exiting "
			    "cmd=%p.\n", cmd);
888
			cmd->result = DID_NO_CONNECT << 16;
889
		} else {
890
			ql_dbg(ql_dbg_aer, vha, 0x9011,
891
			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
892
			cmd->result = DID_REQUEUE << 16;
893
		}
894 895 896
		goto qc24_fail_command;
	}

897 898 899
	rval = fc_remote_port_chkready(rport);
	if (rval) {
		cmd->result = rval;
900
		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
901 902
		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
		    cmd, rval);
903 904 905
		goto qc24_fail_command;
	}

906 907
	if (!vha->flags.difdix_supported &&
		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
908 909 910
			ql_dbg(ql_dbg_io, vha, 0x3004,
			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
			    cmd);
911 912 913
			cmd->result = DID_NO_CONNECT << 16;
			goto qc24_fail_command;
	}
914

915 916
	if (!fcport || fcport->deleted) {
		cmd->result = DID_IMM_RETRY << 16;
917 918 919
		goto qc24_fail_command;
	}

920
	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
921
		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
922
			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
923 924 925 926
			ql_dbg(ql_dbg_io, vha, 0x3005,
			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
			    atomic_read(&fcport->state),
			    atomic_read(&base_vha->loop_state));
927 928 929
			cmd->result = DID_NO_CONNECT << 16;
			goto qc24_fail_command;
		}
930
		goto qc24_target_busy;
931 932
	}

933 934 935 936
	/*
	 * Return target busy if we've received a non-zero retry_delay_timer
	 * in a FCP_RSP.
	 */
937 938 939
	if (fcport->retry_delay_timestamp == 0) {
		/* retry delay not set */
	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
940 941 942 943
		fcport->retry_delay_timestamp = 0;
	else
		goto qc24_target_busy;

944
	sp = scsi_cmd_priv(cmd);
945
	/* ref: INIT */
946
	qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
947

948 949 950 951 952
	sp->u.scmd.cmd = cmd;
	sp->type = SRB_SCSI_CMD;
	sp->free = qla2x00_sp_free_dma;
	sp->done = qla2x00_sp_compl;

953
	rval = ha->isp_ops->start_scsi(sp);
954
	if (rval != QLA_SUCCESS) {
955
		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
956
		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
957
		goto qc24_host_busy_free_sp;
958
	}
959 960 961 962

	return 0;

qc24_host_busy_free_sp:
963 964
	/* ref: INIT */
	kref_put(&sp->cmd_kref, qla2x00_sp_release);
965

966 967 968
qc24_target_busy:
	return SCSI_MLQUEUE_TARGET_BUSY;

969
qc24_fail_command:
970
	scsi_done(cmd);
971 972 973 974

	return 0;
}

975 976 977 978 979 980 981 982 983 984 985 986 987
/* For MQ supported I/O */
int
qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
    struct qla_qpair *qpair)
{
	scsi_qla_host_t *vha = shost_priv(host);
	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
	struct qla_hw_data *ha = vha->hw;
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
	srb_t *sp;
	int rval;

988
	rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
989 990 991 992 993 994 995 996
	if (rval) {
		cmd->result = rval;
		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
		    cmd, rval);
		goto qc24_fail_command;
	}

997 998 999 1000 1001 1002 1003
	if (!qpair->online) {
		ql_dbg(ql_dbg_io, vha, 0x3077,
		       "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
		cmd->result = DID_NO_CONNECT << 16;
		goto qc24_fail_command;
	}

1004 1005
	if (!fcport || fcport->deleted) {
		cmd->result = DID_IMM_RETRY << 16;
1006 1007 1008
		goto qc24_fail_command;
	}

1009
	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
			ql_dbg(ql_dbg_io, vha, 0x3077,
			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
			    atomic_read(&fcport->state),
			    atomic_read(&base_vha->loop_state));
			cmd->result = DID_NO_CONNECT << 16;
			goto qc24_fail_command;
		}
		goto qc24_target_busy;
	}

	/*
	 * Return target busy if we've received a non-zero retry_delay_timer
	 * in a FCP_RSP.
	 */
	if (fcport->retry_delay_timestamp == 0) {
		/* retry delay not set */
	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
		fcport->retry_delay_timestamp = 0;
	else
		goto qc24_target_busy;

1033
	sp = scsi_cmd_priv(cmd);
1034
	/* ref: INIT */
1035
	qla2xxx_init_sp(sp, vha, qpair, fcport);
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051

	sp->u.scmd.cmd = cmd;
	sp->type = SRB_SCSI_CMD;
	sp->free = qla2xxx_qpair_sp_free_dma;
	sp->done = qla2xxx_qpair_sp_compl;

	rval = ha->isp_ops->start_scsi_mq(sp);
	if (rval != QLA_SUCCESS) {
		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
		goto qc24_host_busy_free_sp;
	}

	return 0;

qc24_host_busy_free_sp:
1052 1053
	/* ref: INIT */
	kref_put(&sp->cmd_kref, qla2x00_sp_release);
1054 1055 1056 1057 1058

qc24_target_busy:
	return SCSI_MLQUEUE_TARGET_BUSY;

qc24_fail_command:
1059
	scsi_done(cmd);
1060 1061 1062 1063

	return 0;
}

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/*
 * qla2x00_eh_wait_on_command
 *    Waits for the command to be returned by the Firmware for some
 *    max time.
 *
 * Input:
 *    cmd = Scsi Command to wait on.
 *
 * Return:
1073 1074
 *    Completed in time : QLA_SUCCESS
 *    Did not complete in time : QLA_FUNCTION_FAILED
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 */
static int
1077
qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
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{
1079
#define ABORT_POLLING_PERIOD	1000
1080
#define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
1081
	unsigned long wait_iter = ABORT_WAIT_ITER;
1082 1083
	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
	struct qla_hw_data *ha = vha->hw;
1084
	srb_t *sp = scsi_cmd_priv(cmd);
1085
	int ret = QLA_SUCCESS;
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1087
	if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1088 1089
		ql_dbg(ql_dbg_taskm, vha, 0x8005,
		    "Return:eh_wait.\n");
1090 1091 1092
		return ret;
	}

1093
	while (sp->type && wait_iter--)
1094
		msleep(ABORT_POLLING_PERIOD);
1095
	if (sp->type)
1096
		ret = QLA_FUNCTION_FAILED;
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1098
	return ret;
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}

/*
 * qla2x00_wait_for_hba_online
1103
 *    Wait till the HBA is online after going through
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 *    <= MAX_RETRIES_OF_ISP_ABORT  or
 *    finally HBA is disabled ie marked offline
 *
 * Input:
 *     ha - pointer to host adapter structure
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 *
 * Note:
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 *    Does context switching-Release SPIN_LOCK
 *    (if any) before calling this routine.
 *
 * Return:
 *    Success (Adapter is online) : 0
 *    Failed  (Adapter is offline/disabled) : 1
 */
1118
int
1119
qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
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{
1121 1122
	int		return_status;
	unsigned long	wait_online;
1123 1124
	struct qla_hw_data *ha = vha->hw;
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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1126
	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
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	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
	    ha->dpc_active) && time_before(jiffies, wait_online)) {
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		msleep(1000);
	}
1134
	if (base_vha->flags.online)
1135
		return_status = QLA_SUCCESS;
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	else
		return_status = QLA_FUNCTION_FAILED;

	return (return_status);
}

1142 1143 1144 1145 1146
static inline int test_fcport_count(scsi_qla_host_t *vha)
{
	struct qla_hw_data *ha = vha->hw;
	unsigned long flags;
	int res;
1147
	/* Return 0 = sleep, x=wake */
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	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1150 1151 1152
	ql_dbg(ql_dbg_init, vha, 0x00ec,
	    "tgt %p, fcport_count=%d\n",
	    vha, vha->fcport_count);
1153
	res = (vha->fcport_count == 0);
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	if  (res) {
		struct fc_port *fcport;

		list_for_each_entry(fcport, &vha->vp_fcports, list) {
			if (fcport->deleted != QLA_SESS_DELETED) {
				/* session(s) may not be fully logged in
				 * (ie fcport_count=0), but session
				 * deletion thread(s) may be inflight.
				 */

				res = 0;
				break;
			}
		}
	}
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	spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);

	return res;
}

/*
 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
 * it has dependency on UNLOADING flag to stop device discovery
 */
1178
void
1179 1180
qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
{
1181 1182
	u8 i;

1183
	qla2x00_mark_all_devices_lost(vha);
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1185 1186 1187 1188 1189
	for (i = 0; i < 10; i++) {
		if (wait_event_timeout(vha->fcport_waitQ,
		    test_fcport_count(vha), HZ) > 0)
			break;
	}
1190

1191
	flush_workqueue(vha->hw->wq);
1192 1193
}

1194
/*
1195 1196
 * qla2x00_wait_for_hba_ready
 * Wait till the HBA is ready before doing driver unload
1197 1198 1199 1200 1201 1202 1203 1204 1205
 *
 * Input:
 *     ha - pointer to host adapter structure
 *
 * Note:
 *    Does context switching-Release SPIN_LOCK
 *    (if any) before calling this routine.
 *
 */
1206 1207
static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1208 1209
{
	struct qla_hw_data *ha = vha->hw;
1210
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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1212 1213 1214 1215 1216 1217
	while ((qla2x00_reset_active(vha) || ha->dpc_active ||
		ha->flags.mbox_busy) ||
	       test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
	       test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
		if (test_bit(UNLOADING, &base_vha->dpc_flags))
			break;
1218
		msleep(1000);
1219
	}
1220 1221
}

1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
int
qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
{
	int		return_status;
	unsigned long	wait_reset;
	struct qla_hw_data *ha = vha->hw;
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);

	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
	    ha->dpc_active) && time_before(jiffies, wait_reset)) {

		msleep(1000);

		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
		    ha->flags.chip_reset_done)
			break;
	}
	if (ha->flags.chip_reset_done)
		return_status = QLA_SUCCESS;
	else
		return_status = QLA_FUNCTION_FAILED;

	return return_status;
}

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/**************************************************************************
* qla2xxx_eh_abort
*
* Description:
*    The abort function will abort the specified command.
*
* Input:
*    cmd = Linux SCSI command packet to be aborted.
*
* Returns:
*    Either SUCCESS or FAILED.
*
* Note:
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*    Only return FAILED if command not returned by firmware.
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**************************************************************************/
1265
static int
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qla2xxx_eh_abort(struct scsi_cmnd *cmd)
{
1268
	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1269
	DECLARE_COMPLETION_ONSTACK(comp);
1270
	srb_t *sp;
1271
	int ret;
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	unsigned int id;
	uint64_t lun;
1274
	int rval;
1275
	struct qla_hw_data *ha = vha->hw;
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	uint32_t ratov_j;
	struct qla_qpair *qpair;
	unsigned long flags;
1279
	int fast_fail_status = SUCCESS;
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1281 1282 1283
	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, vha, 0x8042,
		    "PCI/Register disconnect, exiting.\n");
1284
		qla_pci_set_eeh_busy(vha);
1285 1286
		return FAILED;
	}
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1288
	/* Save any FAST_IO_FAIL value to return later if abort succeeds */
1289 1290
	ret = fc_block_scsi_eh(cmd);
	if (ret != 0)
1291
		fast_fail_status = ret;
1292

1293
	sp = scsi_cmd_priv(cmd);
1294
	qpair = sp->qpair;
1295

1296 1297
	vha->cmd_timeout_cnt++;

1298
	if ((sp->fcport && sp->fcport->deleted) || !qpair)
1299
		return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
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1301 1302 1303 1304
	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
	sp->comp = &comp;
	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);

1305 1306 1307

	id = cmd->device->id;
	lun = cmd->device->lun;
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1309
	ql_dbg(ql_dbg_taskm, vha, 0x8002,
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	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
	    vha->host_no, id, lun, sp, cmd, sp->handle);
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	/*
	 * Abort will release the original Command/sp from FW. Let the
	 * original command call scsi_done. In return, he will wakeup
	 * this sleeping thread.
	 */
1318
	rval = ha->isp_ops->abort_command(sp);
1319

1320 1321
	ql_dbg(ql_dbg_taskm, vha, 0x8003,
	       "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1322

1323 1324 1325
	/* Wait for the command completion. */
	ratov_j = ha->r_a_tov/10 * 4 * 1000;
	ratov_j = msecs_to_jiffies(ratov_j);
1326 1327
	switch (rval) {
	case QLA_SUCCESS:
1328 1329 1330
		if (!wait_for_completion_timeout(&comp, ratov_j)) {
			ql_dbg(ql_dbg_taskm, vha, 0xffff,
			    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1331
			    __func__, ha->r_a_tov/10);
1332 1333
			ret = FAILED;
		} else {
1334
			ret = fast_fail_status;
1335 1336
		}
		break;
1337 1338 1339
	default:
		ret = FAILED;
		break;
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	}
1341

1342
	sp->comp = NULL;
1343

1344
	ql_log(ql_log_info, vha, 0x801c,
1345 1346
	    "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
	    vha->host_no, id, lun, ret);
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1348 1349
	return ret;
}
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/*
 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
 */
1354 1355 1356
static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
				       uint64_t l, enum nexus_wait_type type)
1357
{
1358
	int cnt, match, status;
1359
	unsigned long flags;
1360 1361
	scsi_qla_host_t *vha = qpair->vha;
	struct req_que *req = qpair->req;
1362
	srb_t *sp;
1363
	struct scsi_cmnd *cmd;
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1364

1365
	status = QLA_SUCCESS;
1366

1367
	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1368
	for (cnt = 1; status == QLA_SUCCESS &&
1369
		cnt < req->num_outstanding_cmds; cnt++) {
1370 1371
		sp = req->outstanding_cmds[cnt];
		if (!sp)
1372
			continue;
1373
		if (sp->type != SRB_SCSI_CMD)
1374
			continue;
1375
		if (vha->vp_idx != sp->vha->vp_idx)
1376 1377
			continue;
		match = 0;
1378
		cmd = GET_CMD_SP(sp);
1379 1380 1381 1382 1383
		switch (type) {
		case WAIT_HOST:
			match = 1;
			break;
		case WAIT_TARGET:
1384
			match = cmd->device->id == t;
1385 1386
			break;
		case WAIT_LUN:
1387 1388
			match = (cmd->device->id == t &&
				cmd->device->lun == l);
1389
			break;
1390
		}
1391 1392 1393
		if (!match)
			continue;

1394
		spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1395
		status = qla2x00_eh_wait_on_command(cmd);
1396
		spin_lock_irqsave(qpair->qp_lock_ptr, flags);
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	}
1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);

	return status;
}

int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
				     uint64_t l, enum nexus_wait_type type)
{
	struct qla_qpair *qpair;
	struct qla_hw_data *ha = vha->hw;
	int i, status = QLA_SUCCESS;
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1411 1412 1413 1414 1415 1416 1417 1418 1419
	status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
							type);
	for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
		qpair = ha->queue_pair_map[i];
		if (!qpair)
			continue;
		status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
								type);
	}
1420
	return status;
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}

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static char *reset_errors[] = {
	"HBA not online",
	"HBA not ready",
	"Task management failed",
	"Waiting for command completions",
};
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1430
static int
1431
qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
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{
1433 1434 1435 1436 1437
	struct scsi_device *sdev = cmd->device;
	scsi_qla_host_t *vha = shost_priv(sdev->host);
	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
	fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
	struct qla_hw_data *ha = vha->hw;
1438
	int err;
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1440 1441 1442 1443 1444 1445 1446
	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, vha, 0x803e,
		    "PCI/Register disconnect, exiting.\n");
		qla_pci_set_eeh_busy(vha);
		return FAILED;
	}

1447
	if (!fcport) {
1448
		return FAILED;
1449
	}
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1451
	err = fc_block_rport(rport);
1452 1453 1454
	if (err != 0)
		return err;

1455
	if (fcport->deleted)
1456
		return FAILED;
1457

1458
	ql_log(ql_log_info, vha, 0x8009,
1459 1460
	    "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
	    sdev->id, sdev->lun, cmd);
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1462
	err = 0;
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	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x800a,
		    "Wait for hba online failed for cmd=%p.\n", cmd);
1466
		goto eh_reset_failed;
1467
	}
1468
	err = 2;
1469
	if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1470 1471 1472
		!= QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x800c,
		    "do_reset failed for cmd=%p.\n", cmd);
1473
		goto eh_reset_failed;
1474
	}
1475
	err = 3;
1476 1477
	if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id,
	    sdev->lun, WAIT_LUN) != QLA_SUCCESS) {
1478
		ql_log(ql_log_warn, vha, 0x800d,
1479
		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1480
		goto eh_reset_failed;
1481
	}
1482

1483
	ql_log(ql_log_info, vha, 0x800e,
1484 1485
	    "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
	    vha->host_no, sdev->id, sdev->lun, cmd);
1486 1487 1488

	return SUCCESS;

1489
eh_reset_failed:
1490
	ql_log(ql_log_info, vha, 0x800f,
1491 1492
	    "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
	    reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1493
	    cmd);
1494
	vha->reset_cmd_err_cnt++;
1495 1496
	return FAILED;
}
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static int
1499
qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
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{
1501 1502 1503
	struct scsi_device *sdev = cmd->device;
	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
	scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1504
	struct qla_hw_data *ha = vha->hw;
1505 1506
	fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
	int err;
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1508 1509 1510
	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, vha, 0x803f,
		    "PCI/Register disconnect, exiting.\n");
1511
		qla_pci_set_eeh_busy(vha);
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		return FAILED;
	}

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	if (!fcport) {
		return FAILED;
	}

	err = fc_block_rport(rport);
	if (err != 0)
		return err;

	if (fcport->deleted)
1524
		return FAILED;
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	ql_log(ql_log_info, vha, 0x8009,
	    "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
	    sdev->id, cmd);

	err = 0;
	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x800a,
		    "Wait for hba online failed for cmd=%p.\n", cmd);
		goto eh_reset_failed;
	}
	err = 2;
	if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x800c,
		    "target_reset failed for cmd=%p.\n", cmd);
		goto eh_reset_failed;
	}
	err = 3;
	if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id,
	    0, WAIT_TARGET) != QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x800d,
		    "wait for pending cmds failed for cmd=%p.\n", cmd);
		goto eh_reset_failed;
	}

	ql_log(ql_log_info, vha, 0x800e,
	    "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
	    vha->host_no, sdev->id, cmd);

	return SUCCESS;

eh_reset_failed:
	ql_log(ql_log_info, vha, 0x800f,
	    "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
	    cmd);
	vha->reset_cmd_err_cnt++;
	return FAILED;
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}

/**************************************************************************
* qla2xxx_eh_bus_reset
*
* Description:
*    The bus reset function will reset the bus and abort any executing
*    commands.
*
* Input:
*    cmd = Linux SCSI command packet of the command that cause the
*          bus reset.
*
* Returns:
*    SUCCESS/FAILURE (defined as macro in scsi.h).
*
**************************************************************************/
1580
static int
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qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
{
1583
	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1584
	int ret = FAILED;
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	unsigned int id;
	uint64_t lun;
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	struct qla_hw_data *ha = vha->hw;

	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, vha, 0x8040,
		    "PCI/Register disconnect, exiting.\n");
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		qla_pci_set_eeh_busy(vha);
1593 1594
		return FAILED;
	}
1595 1596 1597

	id = cmd->device->id;
	lun = cmd->device->lun;
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	if (qla2x00_chip_is_down(vha))
		return ret;

1602
	ql_log(ql_log_info, vha, 0x8012,
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	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
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1605
	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
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		ql_log(ql_log_fatal, vha, 0x8013,
		    "Wait for hba online failed board disabled.\n");
1608
		goto eh_bus_reset_done;
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	}

1611 1612 1613
	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
		ret = SUCCESS;

1614 1615
	if (ret == FAILED)
		goto eh_bus_reset_done;
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1616

1617
	/* Flush outstanding commands. */
1618
	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
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	    QLA_SUCCESS) {
		ql_log(ql_log_warn, vha, 0x8014,
		    "Wait for pending commands failed.\n");
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		ret = FAILED;
1623
	}
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1625
eh_bus_reset_done:
1626
	ql_log(ql_log_warn, vha, 0x802b,
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	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
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	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
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	return ret;
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}

/**************************************************************************
* qla2xxx_eh_host_reset
*
* Description:
*    The reset function will reset the Adapter.
*
* Input:
*      cmd = Linux SCSI command packet of the command that cause the
*            adapter reset.
*
* Returns:
*      Either SUCCESS or FAILED.
*
* Note:
**************************************************************************/
1648
static int
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qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
{
1651 1652
	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
	struct qla_hw_data *ha = vha->hw;
1653
	int ret = FAILED;
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	unsigned int id;
	uint64_t lun;
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	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, vha, 0x8041,
		    "PCI/Register disconnect, exiting.\n");
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		qla_pci_set_eeh_busy(vha);
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		return SUCCESS;
	}

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	id = cmd->device->id;
	lun = cmd->device->lun;

1668
	ql_log(ql_log_info, vha, 0x8018,
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	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
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	/*
	 * No point in issuing another reset if one is active.  Also do not
	 * attempt a reset if we are updating flash.
	 */
	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1676
		goto eh_host_reset_lock;
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1678 1679
	if (vha != base_vha) {
		if (qla2x00_vp_abort_isp(vha))
1680
			goto eh_host_reset_lock;
1681
	} else {
1682
		if (IS_P3P_TYPE(vha->hw)) {
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			if (!qla82xx_fcoe_ctx_reset(vha)) {
				/* Ctx reset success */
				ret = SUCCESS;
				goto eh_host_reset_lock;
			}
			/* fall thru if ctx reset failed */
		}
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		if (ha->wq)
			flush_workqueue(ha->wq);

1693
		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1694
		if (ha->isp_ops->abort_isp(base_vha)) {
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			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
			/* failed. schedule dpc to try */
			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);

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			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
				ql_log(ql_log_warn, vha, 0x802a,
				    "wait for hba online failed.\n");
1702
				goto eh_host_reset_lock;
1703
			}
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		}
		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1706
	}
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	/* Waiting for command to be returned to OS.*/
1709
	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1710
		QLA_SUCCESS)
1711
		ret = SUCCESS;
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eh_host_reset_lock:
1714
	ql_log(ql_log_info, vha, 0x8017,
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	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1716
	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
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	return ret;
}
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/*
* qla2x00_loop_reset
*      Issue loop reset.
*
* Input:
*      ha = adapter block pointer.
*
* Returns:
*      0 = success
*/
1731
int
1732
qla2x00_loop_reset(scsi_qla_host_t *vha)
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{
1734
	int ret;
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	struct qla_hw_data *ha = vha->hw;
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	if (IS_QLAFX00(ha))
		return QLA_SUCCESS;
1739

1740
	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
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		atomic_set(&vha->loop_state, LOOP_DOWN);
		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
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		qla2x00_mark_all_devices_lost(vha);
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		ret = qla2x00_full_login_lip(vha);
1745
		if (ret != QLA_SUCCESS) {
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			ql_dbg(ql_dbg_taskm, vha, 0x802d,
			    "full_login_lip=%d.\n", ret);
1748
		}
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	}

1751
	if (ha->flags.enable_lip_reset) {
1752
		ret = qla2x00_lip_reset(vha);
1753
		if (ret != QLA_SUCCESS)
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			ql_dbg(ql_dbg_taskm, vha, 0x802e,
			    "lip_reset failed (%d).\n", ret);
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	}

	/* Issue marker command only when we are going to start the I/O */
1759
	vha->marker_needed = 1;
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1761
	return QLA_SUCCESS;
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}

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/*
 * The caller must ensure that no completion interrupts will happen
 * while this function is in progress.
 */
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static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
			      unsigned long *flags)
	__releases(qp->qp_lock_ptr)
	__acquires(qp->qp_lock_ptr)
{
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	DECLARE_COMPLETION_ONSTACK(comp);
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	scsi_qla_host_t *vha = qp->vha;
	struct qla_hw_data *ha = vha->hw;
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	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1777
	int rval;
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	bool ret_cmd;
	uint32_t ratov_j;
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	lockdep_assert_held(qp->qp_lock_ptr);

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	if (qla2x00_chip_is_down(vha)) {
		sp->done(sp, res);
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		return;
1786
	}
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	if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
	    (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
	     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
	     !qla2x00_isp_reg_stat(ha))) {
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		if (sp->comp) {
			sp->done(sp, res);
			return;
		}

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		sp->comp = &comp;
		spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);

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		rval = ha->isp_ops->abort_command(sp);
		/* Wait for command completion. */
		ret_cmd = false;
		ratov_j = ha->r_a_tov/10 * 4 * 1000;
		ratov_j = msecs_to_jiffies(ratov_j);
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		switch (rval) {
		case QLA_SUCCESS:
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			if (wait_for_completion_timeout(&comp, ratov_j)) {
				ql_dbg(ql_dbg_taskm, vha, 0xffff,
				    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
				    __func__, ha->r_a_tov/10);
				ret_cmd = true;
			}
			/* else FW return SP to driver */
1814
			break;
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		default:
			ret_cmd = true;
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			break;
1818
		}
1819 1820

		spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1821
		if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
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			sp->done(sp, res);
	} else {
		sp->done(sp, res);
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	}
}

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/*
 * The caller must ensure that no completion interrupts will happen
 * while this function is in progress.
 */
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static void
__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1834
{
1835
	int cnt;
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	unsigned long flags;
	srb_t *sp;
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	scsi_qla_host_t *vha = qp->vha;
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	struct qla_hw_data *ha = vha->hw;
1840
	struct req_que *req;
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	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
	struct qla_tgt_cmd *cmd;
1843

1844 1845
	if (!ha->req_q_map)
		return;
1846 1847 1848 1849 1850
	spin_lock_irqsave(qp->qp_lock_ptr, flags);
	req = qp->req;
	for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
		sp = req->outstanding_cmds[cnt];
		if (sp) {
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			switch (sp->cmd_type) {
			case TYPE_SRB:
1853
				qla2x00_abort_srb(qp, sp, res, &flags);
1854 1855
				break;
			case TYPE_TGT_CMD:
1856 1857
				if (!vha->hw->tgt.tgt_ops || !tgt ||
				    qla_ini_mode_enabled(vha)) {
1858 1859 1860
					ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
					    "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
					    vha->dpc_flags);
1861
					continue;
1862
				}
1863
				cmd = (struct qla_tgt_cmd *)sp;
1864
				cmd->aborted = 1;
1865 1866
				break;
			case TYPE_TGT_TMCMD:
1867
				/* Skip task management functions. */
1868 1869 1870
				break;
			default:
				break;
1871
			}
1872
			req->outstanding_cmds[cnt] = NULL;
1873 1874
		}
	}
1875 1876 1877
	spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
}

1878 1879 1880 1881
/*
 * The caller must ensure that no completion interrupts will happen
 * while this function is in progress.
 */
1882 1883 1884 1885 1886 1887
void
qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
{
	int que;
	struct qla_hw_data *ha = vha->hw;

1888 1889 1890
	/* Continue only if initialization complete. */
	if (!ha->base_qpair)
		return;
1891 1892
	__qla2x00_abort_all_cmds(ha->base_qpair, res);

1893 1894
	if (!ha->queue_pair_map)
		return;
1895 1896 1897 1898 1899 1900
	for (que = 0; que < ha->max_qpairs; que++) {
		if (!ha->queue_pair_map[que])
			continue;

		__qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
	}
1901 1902
}

1903 1904
static int
qla2xxx_slave_alloc(struct scsi_device *sdev)
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{
1906
	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
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1908
	if (!rport || fc_remote_port_chkready(rport))
1909
		return -ENXIO;
1910

1911
	sdev->hostdata = *(fc_port_t **)rport->dd_data;
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1913 1914
	return 0;
}
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1916 1917 1918
static int
qla2xxx_slave_configure(struct scsi_device *sdev)
{
1919
	scsi_qla_host_t *vha = shost_priv(sdev->host);
1920
	struct req_que *req = vha->req;
1921

1922 1923 1924
	if (IS_T10_PI_CAPABLE(vha->hw))
		blk_queue_update_dma_alignment(sdev->request_queue, 0x7);

1925
	scsi_change_queue_depth(sdev, req->max_q_depth);
1926 1927
	return 0;
}
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1929 1930 1931 1932
static void
qla2xxx_slave_destroy(struct scsi_device *sdev)
{
	sdev->hostdata = NULL;
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}

/**
 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
 * @ha: HA context
 *
 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
 * supported addressing method.
 */
static void
1943
qla2x00_config_dma_addressing(struct qla_hw_data *ha)
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1944
{
1945
	/* Assume a 32bit DMA mask. */
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1946 1947
	ha->flags.enable_64bit_addressing = 0;

1948
	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1949 1950
		/* Any upper-dword bits set? */
		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1951
		    !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1952
			/* Ok, a 64bit DMA mask is applicable. */
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			ha->flags.enable_64bit_addressing = 1;
1954 1955
			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1956
			return;
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1957 1958
		}
	}
1959

1960
	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1961
	dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
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1962 1963
}

1964
static void
1965
qla2x00_enable_intrs(struct qla_hw_data *ha)
1966 1967 1968 1969 1970 1971 1972
{
	unsigned long flags = 0;
	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;

	spin_lock_irqsave(&ha->hardware_lock, flags);
	ha->interrupts_on = 1;
	/* enable risc and host interrupts */
1973 1974
	wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
	rd_reg_word(&reg->ictrl);
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	spin_unlock_irqrestore(&ha->hardware_lock, flags);

}

static void
1980
qla2x00_disable_intrs(struct qla_hw_data *ha)
1981 1982 1983 1984 1985 1986 1987
{
	unsigned long flags = 0;
	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;

	spin_lock_irqsave(&ha->hardware_lock, flags);
	ha->interrupts_on = 0;
	/* disable risc and host interrupts */
1988 1989
	wrt_reg_word(&reg->ictrl, 0);
	rd_reg_word(&reg->ictrl);
1990 1991 1992 1993
	spin_unlock_irqrestore(&ha->hardware_lock, flags);
}

static void
1994
qla24xx_enable_intrs(struct qla_hw_data *ha)
1995 1996 1997 1998 1999 2000
{
	unsigned long flags = 0;
	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;

	spin_lock_irqsave(&ha->hardware_lock, flags);
	ha->interrupts_on = 1;
2001 2002
	wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
	rd_reg_dword(&reg->ictrl);
2003 2004 2005 2006
	spin_unlock_irqrestore(&ha->hardware_lock, flags);
}

static void
2007
qla24xx_disable_intrs(struct qla_hw_data *ha)
2008 2009 2010 2011
{
	unsigned long flags = 0;
	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;

2012 2013
	if (IS_NOPOLLING_TYPE(ha))
		return;
2014 2015
	spin_lock_irqsave(&ha->hardware_lock, flags);
	ha->interrupts_on = 0;
2016 2017
	wrt_reg_dword(&reg->ictrl, 0);
	rd_reg_dword(&reg->ictrl);
2018 2019 2020
	spin_unlock_irqrestore(&ha->hardware_lock, flags);
}

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static int
qla2x00_iospace_config(struct qla_hw_data *ha)
{
	resource_size_t pio;
	uint16_t msix;

	if (pci_request_selected_regions(ha->pdev, ha->bars,
	    QLA2XXX_DRIVER_NAME)) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}
	if (!(ha->bars & 1))
		goto skip_pio;

	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
	pio = pci_resource_start(ha->pdev, 0);
	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
			    "Invalid pci I/O region size (%s).\n",
			    pci_name(ha->pdev));
			pio = 0;
		}
	} else {
		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
		    "Region #0 no a PIO resource (%s).\n",
		    pci_name(ha->pdev));
		pio = 0;
	}
	ha->pio_address = pio;
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
	    "PIO address=%llu.\n",
	    (unsigned long long)ha->pio_address);

skip_pio:
	/* Use MMIO operations for all accesses. */
	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
		    "Region #1 not an MMIO resource (%s), aborting.\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}
	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
		    "Invalid PCI mem region size (%s), aborting.\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}

	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
	if (!ha->iobase) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
		    "Cannot remap MMIO (%s), aborting.\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}

	/* Determine queue resources */
	ha->max_req_queues = ha->max_rsp_queues = 1;
2082
	ha->msix_count = QLA_BASE_VECTORS;
2083 2084 2085 2086 2087

	/* Check if FW supports MQ or not */
	if (!(ha->fw_attributes & BIT_6))
		goto mqiobase_exit;

2088 2089
	if (!ql2xmqsupport || !ql2xnvmeenable ||
	    (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2090 2091 2092 2093 2094 2095 2096 2097 2098
		goto mqiobase_exit;

	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
			pci_resource_len(ha->pdev, 3));
	if (ha->mqiobase) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
		    "MQIO Base=%p.\n", ha->mqiobase);
		/* Read MSIX vector size of the board */
		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2099
		ha->msix_count = msix + 1;
2100
		/* Max queues are bounded by available msix vectors */
2101 2102 2103 2104 2105 2106 2107 2108
		/* MB interrupt uses 1 vector */
		ha->max_req_queues = ha->msix_count - 1;
		ha->max_rsp_queues = ha->max_req_queues;
		/* Queue pairs is the max value minus the base queue pair */
		ha->max_qpairs = ha->max_rsp_queues - 1;
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
		    "Max no of queues pairs: %d.\n", ha->max_qpairs);

2109
		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2110
		    "MSI-X vector count: %d.\n", ha->msix_count);
2111 2112 2113 2114 2115 2116
	} else
		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
		    "BAR 3 not enabled.\n");

mqiobase_exit:
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2117
	    "MSIX Count: %d.\n", ha->msix_count);
2118 2119 2120 2121 2122 2123 2124
	return (0);

iospace_error_exit:
	return (-ENOMEM);
}


2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164
static int
qla83xx_iospace_config(struct qla_hw_data *ha)
{
	uint16_t msix;

	if (pci_request_selected_regions(ha->pdev, ha->bars,
	    QLA2XXX_DRIVER_NAME)) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
		    pci_name(ha->pdev));

		goto iospace_error_exit;
	}

	/* Use MMIO operations for all accesses. */
	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
		    "Invalid pci I/O region size (%s).\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}
	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
		    "Invalid PCI mem region size (%s), aborting\n",
			pci_name(ha->pdev));
		goto iospace_error_exit;
	}

	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
	if (!ha->iobase) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
		    "Cannot remap MMIO (%s), aborting.\n",
		    pci_name(ha->pdev));
		goto iospace_error_exit;
	}

	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
	/* 83XX 26XX always use MQ type access for queues
	 * - mbar 2, a.k.a region 4 */
	ha->max_req_queues = ha->max_rsp_queues = 1;
2165
	ha->msix_count = QLA_BASE_VECTORS;
2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180
	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
			pci_resource_len(ha->pdev, 4));

	if (!ha->mqiobase) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
		    "BAR2/region4 not enabled\n");
		goto mqiobase_exit;
	}

	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
			pci_resource_len(ha->pdev, 2));
	if (ha->msixbase) {
		/* Read MSIX vector size of the board */
		pci_read_config_word(ha->pdev,
		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
2181
		ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE)  + 1;
2182 2183 2184 2185
		/*
		 * By default, driver uses at least two msix vectors
		 * (default & rspq)
		 */
2186
		if (ql2xmqsupport || ql2xnvmeenable) {
2187 2188
			/* MB interrupt uses 1 vector */
			ha->max_req_queues = ha->msix_count - 1;
2189 2190 2191 2192 2193

			/* ATIOQ needs 1 vector. That's 1 less QPair */
			if (QLA_TGT_MODE_ENABLED())
				ha->max_req_queues--;

2194 2195
			ha->max_rsp_queues = ha->max_req_queues;

2196 2197 2198
			/* Queue pairs is the max value minus
			 * the base queue pair */
			ha->max_qpairs = ha->max_req_queues - 1;
2199
			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2200
			    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2201 2202
		}
		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2203
		    "MSI-X vector count: %d.\n", ha->msix_count);
2204 2205 2206 2207 2208 2209
	} else
		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
		    "BAR 1 not enabled.\n");

mqiobase_exit:
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2210
	    "MSIX Count: %d.\n", ha->msix_count);
2211 2212 2213 2214 2215 2216
	return 0;

iospace_error_exit:
	return -ENOMEM;
}

2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
static struct isp_operations qla2100_isp_ops = {
	.pci_config		= qla2100_pci_config,
	.reset_chip		= qla2x00_reset_chip,
	.chip_diag		= qla2x00_chip_diag,
	.config_rings		= qla2x00_config_rings,
	.reset_adapter		= qla2x00_reset_adapter,
	.nvram_config		= qla2x00_nvram_config,
	.update_fw_options	= qla2x00_update_fw_options,
	.load_risc		= qla2x00_load_risc,
	.pci_info_str		= qla2x00_pci_info_str,
	.fw_version_str		= qla2x00_fw_version_str,
	.intr_handler		= qla2100_intr_handler,
	.enable_intrs		= qla2x00_enable_intrs,
	.disable_intrs		= qla2x00_disable_intrs,
	.abort_command		= qla2x00_abort_command,
2232 2233
	.target_reset		= qla2x00_abort_target,
	.lun_reset		= qla2x00_lun_reset,
2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248
	.fabric_login		= qla2x00_login_fabric,
	.fabric_logout		= qla2x00_fabric_logout,
	.calc_req_entries	= qla2x00_calc_iocbs_32,
	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
	.read_nvram		= qla2x00_read_nvram_data,
	.write_nvram		= qla2x00_write_nvram_data,
	.fw_dump		= qla2100_fw_dump,
	.beacon_on		= NULL,
	.beacon_off		= NULL,
	.beacon_blink		= NULL,
	.read_optrom		= qla2x00_read_optrom_data,
	.write_optrom		= qla2x00_write_optrom_data,
	.get_flash_version	= qla2x00_get_flash_version,
2249
	.start_scsi		= qla2x00_start_scsi,
2250
	.start_scsi_mq          = NULL,
2251
	.abort_isp		= qla2x00_abort_isp,
2252
	.iospace_config     	= qla2x00_iospace_config,
2253
	.initialize_adapter	= qla2x00_initialize_adapter,
2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270
};

static struct isp_operations qla2300_isp_ops = {
	.pci_config		= qla2300_pci_config,
	.reset_chip		= qla2x00_reset_chip,
	.chip_diag		= qla2x00_chip_diag,
	.config_rings		= qla2x00_config_rings,
	.reset_adapter		= qla2x00_reset_adapter,
	.nvram_config		= qla2x00_nvram_config,
	.update_fw_options	= qla2x00_update_fw_options,
	.load_risc		= qla2x00_load_risc,
	.pci_info_str		= qla2x00_pci_info_str,
	.fw_version_str		= qla2x00_fw_version_str,
	.intr_handler		= qla2300_intr_handler,
	.enable_intrs		= qla2x00_enable_intrs,
	.disable_intrs		= qla2x00_disable_intrs,
	.abort_command		= qla2x00_abort_command,
2271 2272
	.target_reset		= qla2x00_abort_target,
	.lun_reset		= qla2x00_lun_reset,
2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287
	.fabric_login		= qla2x00_login_fabric,
	.fabric_logout		= qla2x00_fabric_logout,
	.calc_req_entries	= qla2x00_calc_iocbs_32,
	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
	.read_nvram		= qla2x00_read_nvram_data,
	.write_nvram		= qla2x00_write_nvram_data,
	.fw_dump		= qla2300_fw_dump,
	.beacon_on		= qla2x00_beacon_on,
	.beacon_off		= qla2x00_beacon_off,
	.beacon_blink		= qla2x00_beacon_blink,
	.read_optrom		= qla2x00_read_optrom_data,
	.write_optrom		= qla2x00_write_optrom_data,
	.get_flash_version	= qla2x00_get_flash_version,
2288
	.start_scsi		= qla2x00_start_scsi,
2289
	.start_scsi_mq          = NULL,
2290
	.abort_isp		= qla2x00_abort_isp,
2291
	.iospace_config		= qla2x00_iospace_config,
2292
	.initialize_adapter	= qla2x00_initialize_adapter,
2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309
};

static struct isp_operations qla24xx_isp_ops = {
	.pci_config		= qla24xx_pci_config,
	.reset_chip		= qla24xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla24xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla24xx_nvram_config,
	.update_fw_options	= qla24xx_update_fw_options,
	.load_risc		= qla24xx_load_risc,
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla24xx_intr_handler,
	.enable_intrs		= qla24xx_enable_intrs,
	.disable_intrs		= qla24xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
2310 2311
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= qla24xx_read_nvram_data,
	.write_nvram		= qla24xx_write_nvram_data,
	.fw_dump		= qla24xx_fw_dump,
	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
	.beacon_blink		= qla24xx_beacon_blink,
	.read_optrom		= qla24xx_read_optrom_data,
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
2327
	.start_scsi		= qla24xx_start_scsi,
2328
	.start_scsi_mq          = NULL,
2329
	.abort_isp		= qla2x00_abort_isp,
2330
	.iospace_config		= qla2x00_iospace_config,
2331
	.initialize_adapter	= qla2x00_initialize_adapter,
2332 2333
};

2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348
static struct isp_operations qla25xx_isp_ops = {
	.pci_config		= qla25xx_pci_config,
	.reset_chip		= qla24xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla24xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla24xx_nvram_config,
	.update_fw_options	= qla24xx_update_fw_options,
	.load_risc		= qla24xx_load_risc,
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla24xx_intr_handler,
	.enable_intrs		= qla24xx_enable_intrs,
	.disable_intrs		= qla24xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
2349 2350
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= qla25xx_read_nvram_data,
	.write_nvram		= qla25xx_write_nvram_data,
	.fw_dump		= qla25xx_fw_dump,
	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
	.beacon_blink		= qla24xx_beacon_blink,
2363
	.read_optrom		= qla25xx_read_optrom_data,
2364 2365
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
2366
	.start_scsi		= qla24xx_dif_start_scsi,
2367
	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2368
	.abort_isp		= qla2x00_abort_isp,
2369
	.iospace_config		= qla2x00_iospace_config,
2370
	.initialize_adapter	= qla2x00_initialize_adapter,
2371 2372
};

2373 2374 2375 2376 2377 2378 2379
static struct isp_operations qla81xx_isp_ops = {
	.pci_config		= qla25xx_pci_config,
	.reset_chip		= qla24xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla24xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla81xx_nvram_config,
2380
	.update_fw_options	= qla24xx_update_fw_options,
2381
	.load_risc		= qla81xx_load_risc,
2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla24xx_intr_handler,
	.enable_intrs		= qla24xx_enable_intrs,
	.disable_intrs		= qla24xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2396 2397
	.read_nvram		= NULL,
	.write_nvram		= NULL,
2398 2399 2400
	.fw_dump		= qla81xx_fw_dump,
	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
2401
	.beacon_blink		= qla83xx_beacon_blink,
2402 2403 2404
	.read_optrom		= qla25xx_read_optrom_data,
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
2405
	.start_scsi		= qla24xx_dif_start_scsi,
2406
	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2407
	.abort_isp		= qla2x00_abort_isp,
2408
	.iospace_config		= qla2x00_iospace_config,
2409
	.initialize_adapter	= qla2x00_initialize_adapter,
2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420
};

static struct isp_operations qla82xx_isp_ops = {
	.pci_config		= qla82xx_pci_config,
	.reset_chip		= qla82xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla82xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla81xx_nvram_config,
	.update_fw_options	= qla24xx_update_fw_options,
	.load_risc		= qla82xx_load_risc,
2421
	.pci_info_str		= qla24xx_pci_info_str,
2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla82xx_intr_handler,
	.enable_intrs		= qla82xx_enable_intrs,
	.disable_intrs		= qla82xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= qla24xx_read_nvram_data,
	.write_nvram		= qla24xx_write_nvram_data,
2437
	.fw_dump		= qla82xx_fw_dump,
2438 2439 2440
	.beacon_on		= qla82xx_beacon_on,
	.beacon_off		= qla82xx_beacon_off,
	.beacon_blink		= NULL,
2441 2442
	.read_optrom		= qla82xx_read_optrom_data,
	.write_optrom		= qla82xx_write_optrom_data,
2443
	.get_flash_version	= qla82xx_get_flash_version,
2444
	.start_scsi             = qla82xx_start_scsi,
2445
	.start_scsi_mq          = NULL,
2446
	.abort_isp		= qla82xx_abort_isp,
2447
	.iospace_config     	= qla82xx_iospace_config,
2448
	.initialize_adapter	= qla2x00_initialize_adapter,
2449 2450
};

2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475
static struct isp_operations qla8044_isp_ops = {
	.pci_config		= qla82xx_pci_config,
	.reset_chip		= qla82xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla82xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla81xx_nvram_config,
	.update_fw_options	= qla24xx_update_fw_options,
	.load_risc		= qla82xx_load_risc,
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla8044_intr_handler,
	.enable_intrs		= qla82xx_enable_intrs,
	.disable_intrs		= qla82xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= NULL,
	.write_nvram		= NULL,
2476
	.fw_dump		= qla8044_fw_dump,
2477 2478 2479
	.beacon_on		= qla82xx_beacon_on,
	.beacon_off		= qla82xx_beacon_off,
	.beacon_blink		= NULL,
2480
	.read_optrom		= qla8044_read_optrom_data,
2481 2482 2483
	.write_optrom		= qla8044_write_optrom_data,
	.get_flash_version	= qla82xx_get_flash_version,
	.start_scsi             = qla82xx_start_scsi,
2484
	.start_scsi_mq          = NULL,
2485 2486 2487 2488 2489
	.abort_isp		= qla8044_abort_isp,
	.iospace_config		= qla82xx_iospace_config,
	.initialize_adapter	= qla2x00_initialize_adapter,
};

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static struct isp_operations qla83xx_isp_ops = {
	.pci_config		= qla25xx_pci_config,
	.reset_chip		= qla24xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla24xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla81xx_nvram_config,
2497
	.update_fw_options	= qla24xx_update_fw_options,
2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
	.load_risc		= qla81xx_load_risc,
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla24xx_intr_handler,
	.enable_intrs		= qla24xx_enable_intrs,
	.disable_intrs		= qla24xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= NULL,
	.write_nvram		= NULL,
	.fw_dump		= qla83xx_fw_dump,
	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
	.beacon_blink		= qla83xx_beacon_blink,
	.read_optrom		= qla25xx_read_optrom_data,
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
	.start_scsi		= qla24xx_dif_start_scsi,
2523
	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2524 2525
	.abort_isp		= qla2x00_abort_isp,
	.iospace_config		= qla83xx_iospace_config,
2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
	.initialize_adapter	= qla2x00_initialize_adapter,
};

static struct isp_operations qlafx00_isp_ops = {
	.pci_config		= qlafx00_pci_config,
	.reset_chip		= qlafx00_soft_reset,
	.chip_diag		= qlafx00_chip_diag,
	.config_rings		= qlafx00_config_rings,
	.reset_adapter		= qlafx00_soft_reset,
	.nvram_config		= NULL,
	.update_fw_options	= NULL,
	.load_risc		= NULL,
	.pci_info_str		= qlafx00_pci_info_str,
	.fw_version_str		= qlafx00_fw_version_str,
	.intr_handler		= qlafx00_intr_handler,
	.enable_intrs		= qlafx00_enable_intrs,
	.disable_intrs		= qlafx00_disable_intrs,
2543
	.abort_command		= qla24xx_async_abort_command,
2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561
	.target_reset		= qlafx00_abort_target,
	.lun_reset		= qlafx00_lun_reset,
	.fabric_login		= NULL,
	.fabric_logout		= NULL,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= qla24xx_read_nvram_data,
	.write_nvram		= qla24xx_write_nvram_data,
	.fw_dump		= NULL,
	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
	.beacon_blink		= NULL,
	.read_optrom		= qla24xx_read_optrom_data,
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
	.start_scsi		= qlafx00_start_scsi,
2562
	.start_scsi_mq          = NULL,
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	.abort_isp		= qlafx00_abort_isp,
	.iospace_config		= qlafx00_iospace_config,
	.initialize_adapter	= qlafx00_initialize_adapter,
2566 2567
};

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static struct isp_operations qla27xx_isp_ops = {
	.pci_config		= qla25xx_pci_config,
	.reset_chip		= qla24xx_reset_chip,
	.chip_diag		= qla24xx_chip_diag,
	.config_rings		= qla24xx_config_rings,
	.reset_adapter		= qla24xx_reset_adapter,
	.nvram_config		= qla81xx_nvram_config,
2575
	.update_fw_options	= qla24xx_update_fw_options,
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	.load_risc		= qla81xx_load_risc,
	.pci_info_str		= qla24xx_pci_info_str,
	.fw_version_str		= qla24xx_fw_version_str,
	.intr_handler		= qla24xx_intr_handler,
	.enable_intrs		= qla24xx_enable_intrs,
	.disable_intrs		= qla24xx_disable_intrs,
	.abort_command		= qla24xx_abort_command,
	.target_reset		= qla24xx_abort_target,
	.lun_reset		= qla24xx_lun_reset,
	.fabric_login		= qla24xx_login_fabric,
	.fabric_logout		= qla24xx_fabric_logout,
	.calc_req_entries	= NULL,
	.build_iocbs		= NULL,
	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
	.read_nvram		= NULL,
	.write_nvram		= NULL,
	.fw_dump		= qla27xx_fwdump,
2594
	.mpi_fw_dump		= qla27xx_mpi_fwdump,
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	.beacon_on		= qla24xx_beacon_on,
	.beacon_off		= qla24xx_beacon_off,
	.beacon_blink		= qla83xx_beacon_blink,
	.read_optrom		= qla25xx_read_optrom_data,
	.write_optrom		= qla24xx_write_optrom_data,
	.get_flash_version	= qla24xx_get_flash_version,
	.start_scsi		= qla24xx_dif_start_scsi,
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	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
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	.abort_isp		= qla2x00_abort_isp,
	.iospace_config		= qla83xx_iospace_config,
	.initialize_adapter	= qla2x00_initialize_adapter,
};

2608
static inline void
2609
qla2x00_set_isp_flags(struct qla_hw_data *ha)
2610 2611 2612 2613
{
	ha->device_type = DT_EXTENDED_IDS;
	switch (ha->pdev->device) {
	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2614
		ha->isp_type |= DT_ISP2100;
2615
		ha->device_type &= ~DT_EXTENDED_IDS;
2616
		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
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		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2619
		ha->isp_type |= DT_ISP2200;
2620
		ha->device_type &= ~DT_EXTENDED_IDS;
2621
		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2622 2623
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2624
		ha->isp_type |= DT_ISP2300;
2625
		ha->device_type |= DT_ZIO_SUPPORTED;
2626
		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2627 2628
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2629
		ha->isp_type |= DT_ISP2312;
2630
		ha->device_type |= DT_ZIO_SUPPORTED;
2631
		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2632 2633
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2634
		ha->isp_type |= DT_ISP2322;
2635
		ha->device_type |= DT_ZIO_SUPPORTED;
2636 2637 2638
		if (ha->pdev->subsystem_vendor == 0x1028 &&
		    ha->pdev->subsystem_device == 0x0170)
			ha->device_type |= DT_OEM_001;
2639
		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2640 2641
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2642
		ha->isp_type |= DT_ISP6312;
2643
		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2644 2645
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2646
		ha->isp_type |= DT_ISP6322;
2647
		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2648 2649
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2650
		ha->isp_type |= DT_ISP2422;
2651
		ha->device_type |= DT_ZIO_SUPPORTED;
2652
		ha->device_type |= DT_FWI2;
2653
		ha->device_type |= DT_IIDMA;
2654
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2655 2656
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2657
		ha->isp_type |= DT_ISP2432;
2658
		ha->device_type |= DT_ZIO_SUPPORTED;
2659
		ha->device_type |= DT_FWI2;
2660
		ha->device_type |= DT_IIDMA;
2661
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2662
		break;
2663
	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2664
		ha->isp_type |= DT_ISP8432;
2665 2666 2667 2668 2669
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2670
	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2671
		ha->isp_type |= DT_ISP5422;
2672
		ha->device_type |= DT_FWI2;
2673
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2674
		break;
2675
	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2676
		ha->isp_type |= DT_ISP5432;
2677
		ha->device_type |= DT_FWI2;
2678
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2679
		break;
2680
	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2681
		ha->isp_type |= DT_ISP2532;
2682 2683 2684
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
2685
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2686
		break;
2687
	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2688
		ha->isp_type |= DT_ISP8001;
2689 2690 2691 2692 2693
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2694
	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2695
		ha->isp_type |= DT_ISP8021;
2696 2697 2698 2699 2700 2701
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		/* Initialize 82XX ISP flags */
		qla82xx_init_flags(ha);
		break;
2702
	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2703
		ha->isp_type |= DT_ISP8044;
2704 2705 2706 2707 2708 2709
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		/* Initialize 82XX ISP flags */
		qla82xx_init_flags(ha);
		break;
2710
	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2711
		ha->isp_type |= DT_ISP2031;
2712 2713 2714 2715 2716 2717 2718
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->device_type |= DT_T10_PI;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2719
		ha->isp_type |= DT_ISP8031;
2720 2721 2722 2723 2724 2725
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->device_type |= DT_T10_PI;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2726
	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2727
		ha->isp_type |= DT_ISPFX00;
2728
		break;
2729
	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2730
		ha->isp_type |= DT_ISP2071;
2731 2732 2733
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
2734
		ha->device_type |= DT_T10_PI;
2735 2736
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2737
	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2738
		ha->isp_type |= DT_ISP2271;
2739 2740 2741
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
2742
		ha->device_type |= DT_T10_PI;
2743 2744
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2745
	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2746
		ha->isp_type |= DT_ISP2261;
2747 2748 2749
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
2750
		ha->device_type |= DT_T10_PI;
2751 2752
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770
	case PCI_DEVICE_ID_QLOGIC_ISP2081:
	case PCI_DEVICE_ID_QLOGIC_ISP2089:
		ha->isp_type |= DT_ISP2081;
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->device_type |= DT_T10_PI;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
	case PCI_DEVICE_ID_QLOGIC_ISP2281:
	case PCI_DEVICE_ID_QLOGIC_ISP2289:
		ha->isp_type |= DT_ISP2281;
		ha->device_type |= DT_ZIO_SUPPORTED;
		ha->device_type |= DT_FWI2;
		ha->device_type |= DT_IIDMA;
		ha->device_type |= DT_T10_PI;
		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
		break;
2771
	}
2772

2773
	if (IS_QLA82XX(ha))
2774
		ha->port_no = ha->portnum & 1;
2775
	else {
2776 2777
		/* Get adapter physical port no from interrupt pin register. */
		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2778 2779
		if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
		    IS_QLA27XX(ha) || IS_QLA28XX(ha))
2780 2781 2782 2783
			ha->port_no--;
		else
			ha->port_no = !(ha->port_no & 1);
	}
2784

2785
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2786
	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2787
	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2788 2789
}

2790 2791 2792
static void
qla2xxx_scan_start(struct Scsi_Host *shost)
{
2793
	scsi_qla_host_t *vha = shost_priv(shost);
2794

2795 2796 2797
	if (vha->hw->flags.running_gold_fw)
		return;

2798 2799 2800 2801
	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
	set_bit(RSCN_UPDATE, &vha->dpc_flags);
	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2802 2803 2804 2805 2806
}

static int
qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
{
2807
	scsi_qla_host_t *vha = shost_priv(shost);
2808

2809 2810
	if (test_bit(UNLOADING, &vha->dpc_flags))
		return 1;
2811
	if (!vha->host)
2812
		return 1;
2813
	if (time > vha->hw->loop_reset_delay * HZ)
2814 2815
		return 1;

2816
	return atomic_read(&vha->loop_state) == LOOP_READY;
2817 2818
}

2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
static void qla_heartbeat_work_fn(struct work_struct *work)
{
	struct qla_hw_data *ha = container_of(work,
		struct qla_hw_data, heartbeat_work);
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);

	if (!ha->flags.mbox_busy && base_vha->flags.init_done)
		qla_no_op_mb(base_vha);
}

2829 2830 2831 2832
static void qla2x00_iocb_work_fn(struct work_struct *work)
{
	struct scsi_qla_host *vha = container_of(work,
		struct scsi_qla_host, iocb_work);
2833 2834
	struct qla_hw_data *ha = vha->hw;
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2835
	int i = 2;
2836 2837 2838 2839
	unsigned long flags;

	if (test_bit(UNLOADING, &base_vha->dpc_flags))
		return;
2840

2841
	while (!list_empty(&vha->work_list) && i > 0) {
2842
		qla2x00_do_work(vha);
2843
		i--;
2844
	}
2845 2846 2847 2848

	spin_lock_irqsave(&vha->work_lock, flags);
	clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
	spin_unlock_irqrestore(&vha->work_lock, flags);
2849 2850
}

2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871
static void
qla_trace_init(void)
{
	qla_trc_array = trace_array_get_by_name("qla2xxx");
	if (!qla_trc_array) {
		ql_log(ql_log_fatal, NULL, 0x0001,
		       "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
		return;
	}

	QLA_TRACE_ENABLE(qla_trc_array);
}

static void
qla_trace_uninit(void)
{
	if (!qla_trc_array)
		return;
	trace_array_put(qla_trc_array);
}

Linus Torvalds's avatar
Linus Torvalds committed
2872 2873 2874
/*
 * PCI driver interface
 */
2875
static int
2876
qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
Linus Torvalds's avatar
Linus Torvalds committed
2877
{
2878
	int	ret = -ENODEV;
Linus Torvalds's avatar
Linus Torvalds committed
2879
	struct Scsi_Host *host;
2880 2881
	scsi_qla_host_t *base_vha = NULL;
	struct qla_hw_data *ha;
2882
	char pci_info[30];
2883
	char fw_str[30], wq_name[30];
2884
	struct scsi_host_template *sht;
2885
	int bars, mem_only = 0;
2886
	uint16_t req_length = 0, rsp_length = 0;
2887 2888
	struct req_que *req = NULL;
	struct rsp_que *rsp = NULL;
2889
	int i;
2890

2891
	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2892
	sht = &qla2xxx_driver_template;
2893
	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2894
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2895
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2896
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2897
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2898
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2899
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2900 2901
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2902
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2903
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2904
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2905
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2906
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2907 2908 2909 2910 2911
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2912
		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2913
		mem_only = 1;
2914 2915
		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
		    "Mem only adapter.\n");
2916
	}
2917 2918
	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
	    "Bars=%d.\n", bars);
2919

2920 2921
	if (mem_only) {
		if (pci_enable_device_mem(pdev))
2922
			return ret;
2923 2924
	} else {
		if (pci_enable_device(pdev))
2925
			return ret;
2926
	}
2927

2928 2929 2930 2931 2932
	if (is_kdump_kernel()) {
		ql2xmqsupport = 0;
		ql2xallocfwdump = 0;
	}

2933 2934
	/* This may fail but that's ok */
	pci_enable_pcie_error_reporting(pdev);
2935

2936 2937
	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
	if (!ha) {
2938 2939
		ql_log_pci(ql_log_fatal, pdev, 0x0009,
		    "Unable to allocate memory for ha.\n");
2940
		goto disable_device;
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Linus Torvalds committed
2941
	}
2942 2943
	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
	    "Memory allocated for ha=%p.\n", ha);
2944
	ha->pdev = pdev;
2945 2946
	INIT_LIST_HEAD(&ha->tgt.q_full_list);
	spin_lock_init(&ha->tgt.q_full_lock);
2947
	spin_lock_init(&ha->tgt.sess_lock);
2948 2949
	spin_lock_init(&ha->tgt.atio_lock);

2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960
	spin_lock_init(&ha->sadb_lock);
	INIT_LIST_HEAD(&ha->sadb_tx_index_list);
	INIT_LIST_HEAD(&ha->sadb_rx_index_list);

	spin_lock_init(&ha->sadb_fp_lock);

	if (qla_edif_sadb_build_free_pool(ha)) {
		kfree(ha);
		goto  disable_device;
	}

2961
	atomic_set(&ha->nvme_active_aen_cnt, 0);
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2962 2963

	/* Clear our data area */
2964
	ha->bars = bars;
2965
	ha->mem_only = mem_only;
2966
	spin_lock_init(&ha->hardware_lock);
2967
	spin_lock_init(&ha->vport_slock);
2968
	mutex_init(&ha->selflogin_lock);
2969
	mutex_init(&ha->optrom_mutex);
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2970

2971 2972
	/* Set ISP-type information. */
	qla2x00_set_isp_flags(ha);
2973 2974

	/* Set EEH reset type to fundamental if required by hba */
2975
	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2976
	    IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2977 2978
		pdev->needs_freset = 1;

2979 2980 2981 2982
	ha->prev_topology = 0;
	ha->init_cb_size = sizeof(init_cb_t);
	ha->link_data_rate = PORT_SPEED_UNKNOWN;
	ha->optrom_size = OPTROM_SIZE_2300;
2983
	ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2984 2985 2986
	atomic_set(&ha->num_pend_mbx_stage1, 0);
	atomic_set(&ha->num_pend_mbx_stage2, 0);
	atomic_set(&ha->num_pend_mbx_stage3, 0);
2987 2988
	atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
	ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2989

2990
	/* Assign ISP specific operations. */
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2991
	if (IS_QLA2100(ha)) {
2992
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
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2993
		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2994 2995 2996
		req_length = REQUEST_ENTRY_CNT_2100;
		rsp_length = RESPONSE_ENTRY_CNT_2100;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2997
		ha->gid_list_info_size = 4;
2998 2999 3000 3001
		ha->flash_conf_off = ~0;
		ha->flash_data_off = ~0;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3002
		ha->isp_ops = &qla2100_isp_ops;
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3003
	} else if (IS_QLA2200(ha)) {
3004
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3005
		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3006 3007 3008
		req_length = REQUEST_ENTRY_CNT_2200;
		rsp_length = RESPONSE_ENTRY_CNT_2100;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3009
		ha->gid_list_info_size = 4;
3010 3011 3012 3013
		ha->flash_conf_off = ~0;
		ha->flash_data_off = ~0;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3014
		ha->isp_ops = &qla2100_isp_ops;
3015
	} else if (IS_QLA23XX(ha)) {
3016
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
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3017
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3018 3019 3020
		req_length = REQUEST_ENTRY_CNT_2200;
		rsp_length = RESPONSE_ENTRY_CNT_2300;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3021
		ha->gid_list_info_size = 6;
3022 3023
		if (IS_QLA2322(ha) || IS_QLA6322(ha))
			ha->optrom_size = OPTROM_SIZE_2322;
3024 3025 3026 3027
		ha->flash_conf_off = ~0;
		ha->flash_data_off = ~0;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3028
		ha->isp_ops = &qla2300_isp_ops;
3029
	} else if (IS_QLA24XX_TYPE(ha)) {
3030
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3031
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3032 3033
		req_length = REQUEST_ENTRY_CNT_24XX;
		rsp_length = RESPONSE_ENTRY_CNT_2300;
3034
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3035
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3036
		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3037
		ha->gid_list_info_size = 8;
3038
		ha->optrom_size = OPTROM_SIZE_24XX;
3039
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3040
		ha->isp_ops = &qla24xx_isp_ops;
3041 3042 3043 3044
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3045
	} else if (IS_QLA25XX(ha)) {
3046
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3047
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3048 3049
		req_length = REQUEST_ENTRY_CNT_24XX;
		rsp_length = RESPONSE_ENTRY_CNT_2300;
3050
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3051
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3052 3053 3054
		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_25XX;
3055
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3056
		ha->isp_ops = &qla25xx_isp_ops;
3057 3058 3059 3060 3061
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
	} else if (IS_QLA81XX(ha)) {
3062
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3063 3064 3065
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
		req_length = REQUEST_ENTRY_CNT_24XX;
		rsp_length = RESPONSE_ENTRY_CNT_2300;
3066
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3067 3068 3069 3070
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_81XX;
3071
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3072 3073 3074 3075 3076
		ha->isp_ops = &qla81xx_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3077
	} else if (IS_QLA82XX(ha)) {
3078
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3079 3080 3081 3082 3083 3084 3085
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
		req_length = REQUEST_ENTRY_CNT_82XX;
		rsp_length = RESPONSE_ENTRY_CNT_82XX;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_82XX;
3086
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3087 3088 3089 3090 3091
		ha->isp_ops = &qla82xx_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106
	} else if (IS_QLA8044(ha)) {
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
		req_length = REQUEST_ENTRY_CNT_82XX;
		rsp_length = RESPONSE_ENTRY_CNT_82XX;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_83XX;
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
		ha->isp_ops = &qla8044_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3107
	} else if (IS_QLA83XX(ha)) {
3108
		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3109
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3110
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3111
		req_length = REQUEST_ENTRY_CNT_83XX;
Quinn Tran's avatar
Quinn Tran committed
3112
		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3113
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3114 3115 3116 3117 3118 3119 3120 3121 3122 3123
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_83XX;
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
		ha->isp_ops = &qla83xx_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3124 3125 3126 3127 3128 3129 3130 3131 3132 3133
	}  else if (IS_QLAFX00(ha)) {
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
		req_length = REQUEST_ENTRY_CNT_FX00;
		rsp_length = RESPONSE_ENTRY_CNT_FX00;
		ha->isp_ops = &qlafx00_isp_ops;
		ha->port_down_retry_count = 30; /* default value */
		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3134
		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3135
		ha->mr.fw_hbt_en = 1;
3136 3137
		ha->mr.host_info_resend = false;
		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3138 3139 3140 3141
	} else if (IS_QLA27XX(ha)) {
		ha->portnum = PCI_FUNC(ha->pdev->devfn);
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
Quinn Tran's avatar
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3142 3143
		req_length = REQUEST_ENTRY_CNT_83XX;
		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3144
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3145 3146 3147 3148 3149 3150 3151 3152 3153 3154
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_83XX;
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
		ha->isp_ops = &qla27xx_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
3155 3156 3157 3158
	} else if (IS_QLA28XX(ha)) {
		ha->portnum = PCI_FUNC(ha->pdev->devfn);
		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3159 3160
		req_length = REQUEST_ENTRY_CNT_83XX;
		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171
		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
		ha->gid_list_info_size = 8;
		ha->optrom_size = OPTROM_SIZE_28XX;
		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
		ha->isp_ops = &qla27xx_isp_ops;
		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
		ha->nvram_conf_off = ~0;
		ha->nvram_data_off = ~0;
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3172
	}
3173

3174 3175 3176
	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
	    "mbx_count=%d, req_length=%d, "
	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3177 3178
	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
	    "max_fibre_devices=%d.\n",
3179 3180
	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3181
	    ha->nvram_npiv_size, ha->max_fibre_devices);
3182 3183 3184 3185 3186
	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
	    "isp_ops=%p, flash_conf_off=%d, "
	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
	    ha->nvram_conf_off, ha->nvram_data_off);
3187 3188 3189 3190

	/* Configure PCI I/O space */
	ret = ha->isp_ops->iospace_config(ha);
	if (ret)
3191
		goto iospace_config_failed;
3192 3193 3194 3195

	ql_log_pci(ql_log_info, pdev, 0x001d,
	    "Found an ISP%04X irq %d iobase 0x%p.\n",
	    pdev->device, pdev->irq, ha->iobase);
3196
	mutex_init(&ha->vport_lock);
3197
	mutex_init(&ha->mq_lock);
3198 3199 3200
	init_completion(&ha->mbx_cmd_comp);
	complete(&ha->mbx_cmd_comp);
	init_completion(&ha->mbx_intr_comp);
3201
	init_completion(&ha->dcbx_comp);
3202
	init_completion(&ha->lb_portup_comp);
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3203

3204
	set_bit(0, (unsigned long *) ha->vp_idx_map);
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Linus Torvalds committed
3205

3206
	qla2x00_config_dma_addressing(ha);
3207 3208 3209 3210
	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
	    "64 Bit addressing is %s.\n",
	    ha->flags.enable_64bit_addressing ? "enable" :
	    "disable");
3211
	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3212
	if (ret) {
3213 3214
		ql_log_pci(ql_log_fatal, pdev, 0x0031,
		    "Failed to allocate memory for adapter, aborting.\n");
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3215

3216 3217 3218
		goto probe_hw_failed;
	}

3219
	req->max_q_depth = MAX_Q_DEPTH;
3220
	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3221 3222
		req->max_q_depth = ql2xmaxqdepth;

3223 3224 3225

	base_vha = qla2x00_create_host(sht, ha);
	if (!base_vha) {
3226
		ret = -ENOMEM;
3227
		goto probe_hw_failed;
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Linus Torvalds committed
3228 3229
	}

3230
	pci_set_drvdata(pdev, base_vha);
3231
	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3232 3233

	host = base_vha->host;
3234
	base_vha->req = req;
3235
	if (IS_QLA2XXX_MIDTYPE(ha))
3236 3237
		base_vha->mgmt_svr_loop_id =
			qla2x00_reserve_mgmt_server_loop_id(base_vha);
3238
	else
3239 3240
		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
						base_vha->vp_idx;
3241

3242 3243 3244 3245 3246 3247 3248 3249
	/* Setup fcport template structure. */
	ha->mr.fcport.vha = base_vha;
	ha->mr.fcport.port_type = FCT_UNKNOWN;
	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
	ha->mr.fcport.scan_state = 1;

3250 3251 3252 3253
	qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
			    QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
			    QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);

3254 3255 3256 3257 3258 3259 3260 3261
	/* Set the SG table size based on ISP type */
	if (!IS_FWI2_CAPABLE(ha)) {
		if (IS_QLA2100(ha))
			host->sg_tablesize = 32;
	} else {
		if (!IS_QLA82XX(ha))
			host->sg_tablesize = QLA_SG_ALL;
	}
3262
	host->max_id = ha->max_fibre_devices;
3263 3264
	host->cmd_per_lun = 3;
	host->unique_id = host->host_no;
3265
	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3266 3267 3268
		host->max_cmd_len = 32;
	else
		host->max_cmd_len = MAX_CMDSZ;
3269
	host->max_channel = MAX_BUSES - 1;
3270 3271 3272 3273 3274 3275
	/* Older HBAs support only 16-bit LUNs */
	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
	    ql2xmaxlun > 0xffff)
		host->max_lun = 0xffff;
	else
		host->max_lun = ql2xmaxlun;
3276
	host->transportt = qla2xxx_transport_template;
3277
	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3278

3279 3280 3281
	ql_dbg(ql_dbg_init, base_vha, 0x0033,
	    "max_id=%d this_id=%d "
	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3282
	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3283 3284 3285 3286
	    host->this_id, host->cmd_per_lun, host->unique_id,
	    host->max_cmd_len, host->max_channel, host->max_lun,
	    host->transportt, sht->vendor_id);

3287
	INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3288
	INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3289

3290 3291 3292
	/* Set up the irqs */
	ret = qla2x00_request_irqs(ha, rsp);
	if (ret)
3293
		goto probe_failed;
3294

3295
	/* Alloc arrays of request and response ring ptrs */
3296 3297
	ret = qla2x00_alloc_queues(ha, req, rsp);
	if (ret) {
3298 3299 3300
		ql_log(ql_log_fatal, base_vha, 0x003d,
		    "Failed to allocate memory for queue pointers..."
		    "aborting.\n");
3301
		ret = -ENODEV;
3302
		goto probe_failed;
3303 3304
	}

3305
	if (ha->mqenable) {
3306 3307 3308 3309 3310
		/* number of hardware queues supported by blk/scsi-mq*/
		host->nr_hw_queues = ha->max_qpairs;

		ql_dbg(ql_dbg_init, base_vha, 0x0192,
			"blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321
	} else {
		if (ql2xnvmeenable) {
			host->nr_hw_queues = ha->max_qpairs;
			ql_dbg(ql_dbg_init, base_vha, 0x0194,
			    "FC-NVMe support is enabled, HW queues=%d\n",
			    host->nr_hw_queues);
		} else {
			ql_dbg(ql_dbg_init, base_vha, 0x0193,
			    "blk/scsi-mq disabled.\n");
		}
	}
3322

3323
	qlt_probe_one_stage1(base_vha, ha);
3324

3325 3326
	pci_save_state(pdev);

3327
	/* Assign back pointers */
3328 3329
	rsp->req = req;
	req->rsp = rsp;
3330

3331 3332 3333 3334 3335 3336 3337
	if (IS_QLAFX00(ha)) {
		ha->rsp_q_map[0] = rsp;
		ha->req_q_map[0] = req;
		set_bit(0, ha->req_qid_map);
		set_bit(0, ha->rsp_qid_map);
	}

3338 3339 3340 3341 3342
	/* FWI2-capable only. */
	req->req_q_in = &ha->iobase->isp24.req_q_in;
	req->req_q_out = &ha->iobase->isp24.req_q_out;
	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3343 3344
	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
	    IS_QLA28XX(ha)) {
3345 3346 3347 3348
		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
3349 3350
	}

3351 3352 3353 3354 3355 3356 3357
	if (IS_QLAFX00(ha)) {
		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
	}

3358
	if (IS_P3P_TYPE(ha)) {
3359 3360 3361 3362 3363
		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
	}

3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377
	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
	    "req->req_q_in=%p req->req_q_out=%p "
	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
	    req->req_q_in, req->req_q_out,
	    rsp->rsp_q_in, rsp->rsp_q_out);
	ql_dbg(ql_dbg_init, base_vha, 0x003e,
	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
	ql_dbg(ql_dbg_init, base_vha, 0x003f,
	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
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3378

3379
	ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3380 3381 3382 3383
	if (unlikely(!ha->wq)) {
		ret = -ENOMEM;
		goto probe_failed;
	}
3384

3385
	if (ha->isp_ops->initialize_adapter(base_vha)) {
3386 3387 3388
		ql_log(ql_log_fatal, base_vha, 0x00d6,
		    "Failed to initialize adapter - Adapter flags %x.\n",
		    base_vha->device_flags);
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3389

3390 3391 3392
		if (IS_QLA82XX(ha)) {
			qla82xx_idc_lock(ha);
			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3393
				QLA8XXX_DEV_FAILED);
3394
			qla82xx_idc_unlock(ha);
3395 3396
			ql_log(ql_log_fatal, base_vha, 0x00d7,
			    "HW State: FAILED.\n");
3397 3398 3399 3400 3401 3402 3403 3404
		} else if (IS_QLA8044(ha)) {
			qla8044_idc_lock(ha);
			qla8044_wr_direct(base_vha,
				QLA8044_CRB_DEV_STATE_INDEX,
				QLA8XXX_DEV_FAILED);
			qla8044_idc_unlock(ha);
			ql_log(ql_log_fatal, base_vha, 0x0150,
			    "HW State: FAILED.\n");
3405 3406
		}

3407
		ret = -ENODEV;
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3408 3409 3410
		goto probe_failed;
	}

3411 3412 3413 3414 3415 3416 3417 3418 3419 3420
	if (IS_QLAFX00(ha))
		host->can_queue = QLAFX00_MAX_CANQUEUE;
	else
		host->can_queue = req->num_outstanding_cmds - 10;

	ql_dbg(ql_dbg_init, base_vha, 0x0032,
	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
	    host->can_queue, base_vha->req,
	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);

3421 3422 3423 3424
	/* Check if FW supports MQ or not for ISP25xx */
	if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
		ha->mqenable = 0;

3425 3426 3427
	if (ha->mqenable) {
		bool startit = false;

3428
		if (QLA_TGT_MODE_ENABLED())
3429 3430
			startit = false;

3431
		if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3432 3433
			startit = true;

3434 3435 3436
		/* Create start of day qpairs for Block MQ */
		for (i = 0; i < ha->max_qpairs; i++)
			qla2xxx_create_qpair(base_vha, 5, 0, startit);
3437
	}
3438
	qla_init_iocb_limit(base_vha);
3439

3440 3441 3442
	if (ha->flags.running_gold_fw)
		goto skip_dpc;

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3443 3444 3445
	/*
	 * Startup the kernel thread for this host adapter
	 */
3446
	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3447
	    "%s_dpc", base_vha->host_str);
3448
	if (IS_ERR(ha->dpc_thread)) {
3449 3450
		ql_log(ql_log_fatal, base_vha, 0x00ed,
		    "Failed to start DPC thread.\n");
3451
		ret = PTR_ERR(ha->dpc_thread);
3452
		ha->dpc_thread = NULL;
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3453 3454
		goto probe_failed;
	}
3455 3456
	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
	    "DPC thread started successfully.\n");
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3457

3458 3459 3460 3461 3462 3463 3464 3465
	/*
	 * If we're not coming up in initiator mode, we might sit for
	 * a while without waking up the dpc thread, which leads to a
	 * stuck process warning.  So just kick the dpc once here and
	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
	 */
	qla2xxx_wake_dpc(base_vha);

3466 3467
	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);

3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481
	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
		ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);

		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
		ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
		INIT_WORK(&ha->idc_state_handler,
		    qla83xx_idc_state_handler_work);
		INIT_WORK(&ha->nic_core_unrecoverable,
		    qla83xx_nic_core_unrecoverable_work);
	}

3482
skip_dpc:
3483 3484
	list_add_tail(&base_vha->list, &ha->vp_list);
	base_vha->host->irq = ha->pdev->irq;
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3485 3486

	/* Initialized the timer */
3487
	qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3488 3489 3490 3491 3492 3493
	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
	    "Started qla2x00_timer with "
	    "interval=%d.\n", WATCH_INTERVAL);
	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
	    "Detected hba at address=%p.\n",
	    ha);
3494

3495
	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3496
		if (ha->fw_attributes & BIT_4) {
3497
			int prot = 0, guard;
3498

3499
			base_vha->flags.difdix_supported = 1;
3500 3501
			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
			    "Registering for DIF/DIX type 1 and 3 protection.\n");
3502 3503
			if (ql2xenabledif == 1)
				prot = SHOST_DIX_TYPE0_PROTECTION;
3504 3505 3506 3507 3508 3509 3510 3511 3512 3513
			if (ql2xprotmask)
				scsi_host_set_prot(host, ql2xprotmask);
			else
				scsi_host_set_prot(host,
				    prot | SHOST_DIF_TYPE1_PROTECTION
				    | SHOST_DIF_TYPE2_PROTECTION
				    | SHOST_DIF_TYPE3_PROTECTION
				    | SHOST_DIX_TYPE1_PROTECTION
				    | SHOST_DIX_TYPE2_PROTECTION
				    | SHOST_DIX_TYPE3_PROTECTION);
3514 3515 3516 3517 3518 3519 3520

			guard = SHOST_DIX_GUARD_CRC;

			if (IS_PI_IPGUARD_CAPABLE(ha) &&
			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
				guard |= SHOST_DIX_GUARD_IP;

3521 3522 3523 3524
			if (ql2xprotguard)
				scsi_host_set_guard(host, ql2xprotguard);
			else
				scsi_host_set_guard(host, guard);
3525 3526 3527 3528
		} else
			base_vha->flags.difdix_supported = 0;
	}

3529 3530
	ha->isp_ops->enable_intrs(ha);

3531 3532 3533 3534 3535 3536 3537
	if (IS_QLAFX00(ha)) {
		ret = qlafx00_fx_disc(base_vha,
			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
		    QLA_SG_ALL : 128;
	}

3538 3539 3540 3541
	ret = scsi_add_host(host, &pdev->dev);
	if (ret)
		goto probe_failed;

3542 3543
	base_vha->flags.init_done = 1;
	base_vha->flags.online = 1;
3544
	ha->prev_minidump_failed = 0;
3545

3546 3547 3548
	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
	    "Init done and hba is online.\n");

3549 3550
	if (qla_ini_mode_enabled(base_vha) ||
		qla_dual_mode_enabled(base_vha))
3551 3552
		scsi_scan_host(host);
	else
3553
		ql_log(ql_log_info, base_vha, 0x0122,
3554
			"skipping scsi_scan_host() for non-initiator port\n");
3555

3556
	qla2x00_alloc_sysfs_attr(base_vha);
3557

3558 3559 3560 3561 3562 3563 3564 3565 3566
	if (IS_QLAFX00(ha)) {
		ret = qlafx00_fx_disc(base_vha,
			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);

		/* Register system information */
		ret =  qlafx00_fx_disc(base_vha,
			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
	}

3567
	qla2x00_init_host_attr(base_vha);
3568

3569
	qla2x00_dfs_setup(base_vha);
3570

3571 3572
	ql_log(ql_log_info, base_vha, 0x00fb,
	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3573 3574
	ql_log(ql_log_info, base_vha, 0x00fc,
	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3575 3576
	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
						       sizeof(pci_info)),
3577 3578
	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
	    base_vha->host_no,
3579
	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
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3580

3581 3582
	qlt_add_target(ha, base_vha);

3583
	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3584 3585 3586 3587

	if (test_bit(UNLOADING, &base_vha->dpc_flags))
		return -ENODEV;

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3588 3589 3590
	return 0;

probe_failed:
3591
	qla_enode_stop(base_vha);
3592
	qla_edb_stop(base_vha);
3593 3594 3595 3596 3597 3598
	if (base_vha->gnl.l) {
		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
				base_vha->gnl.l, base_vha->gnl.ldma);
		base_vha->gnl.l = NULL;
	}

3599 3600 3601 3602 3603 3604 3605 3606 3607 3608
	if (base_vha->timer_active)
		qla2x00_stop_timer(base_vha);
	base_vha->flags.online = 0;
	if (ha->dpc_thread) {
		struct task_struct *t = ha->dpc_thread;

		ha->dpc_thread = NULL;
		kthread_stop(t);
	}

3609 3610
	qla2x00_free_device(base_vha);
	scsi_host_put(base_vha->host);
3611 3612 3613 3614 3615 3616 3617 3618
	/*
	 * Need to NULL out local req/rsp after
	 * qla2x00_free_device => qla2x00_free_queues frees
	 * what these are pointing to. Or else we'll
	 * fall over below in qla2x00_free_req/rsp_que.
	 */
	req = NULL;
	rsp = NULL;
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3619

3620
probe_hw_failed:
3621 3622 3623
	qla2x00_mem_free(ha);
	qla2x00_free_req_que(ha, req);
	qla2x00_free_rsp_que(ha, rsp);
3624 3625
	qla2x00_clear_drv_active(ha);

3626
iospace_config_failed:
3627
	if (IS_P3P_TYPE(ha)) {
3628
		if (!ha->nx_pcibase)
3629
			iounmap((device_reg_t *)ha->nx_pcibase);
3630
		if (!ql2xdbwr)
3631
			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3632 3633 3634
	} else {
		if (ha->iobase)
			iounmap(ha->iobase);
3635 3636
		if (ha->cregbase)
			iounmap(ha->cregbase);
3637
	}
3638 3639
	pci_release_selected_regions(ha->pdev, ha->bars);
	kfree(ha);
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3640

3641
disable_device:
3642
	pci_disable_device(pdev);
3643
	return ret;
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3644 3645
}

3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668
static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
{
	scsi_qla_host_t *vp;
	unsigned long flags;
	struct qla_hw_data *ha;

	if (!base_vha)
		return;

	ha = base_vha->hw;

	spin_lock_irqsave(&ha->vport_slock, flags);
	list_for_each_entry(vp, &ha->vp_list, list)
		set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);

	/*
	 * Indicate device removal to prevent future board_disable
	 * and wait until any pending board_disable has completed.
	 */
	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
	spin_unlock_irqrestore(&ha->vport_slock, flags);
}

3669 3670 3671 3672 3673 3674 3675 3676 3677
static void
qla2x00_shutdown(struct pci_dev *pdev)
{
	scsi_qla_host_t *vha;
	struct qla_hw_data  *ha;

	vha = pci_get_drvdata(pdev);
	ha = vha->hw;

3678 3679 3680 3681 3682 3683 3684
	ql_log(ql_log_info, vha, 0xfffa,
		"Adapter shutdown\n");

	/*
	 * Prevent future board_disable and wait
	 * until any pending board_disable has completed.
	 */
3685
	__qla_set_remove_flag(vha);
3686 3687 3688 3689 3690
	cancel_work_sync(&ha->board_disable);

	if (!atomic_read(&pdev->enable_cnt))
		return;

3691 3692 3693 3694
	/* Notify ISPFX00 firmware */
	if (IS_QLAFX00(ha))
		qlafx00_driver_shutdown(vha, 20);

3695 3696 3697 3698 3699 3700 3701 3702 3703 3704
	/* Turn-off FCE trace */
	if (ha->flags.fce_enabled) {
		qla2x00_disable_fce_trace(vha, NULL, NULL);
		ha->flags.fce_enabled = 0;
	}

	/* Turn-off EFT trace */
	if (ha->eft)
		qla2x00_disable_eft_trace(vha);

3705 3706
	if (IS_QLA25XX(ha) ||  IS_QLA2031(ha) || IS_QLA27XX(ha) ||
	    IS_QLA28XX(ha)) {
3707 3708 3709 3710 3711 3712
		if (ha->flags.fw_started)
			qla2x00_abort_isp_cleanup(vha);
	} else {
		/* Stop currently executing firmware. */
		qla2x00_try_to_stop_firmware(vha);
	}
3713

3714 3715 3716 3717
	/* Disable timer */
	if (vha->timer_active)
		qla2x00_stop_timer(vha);

3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729
	/* Turn adapter off line */
	vha->flags.online = 0;

	/* turn-off interrupts on the card */
	if (ha->interrupts_on) {
		vha->flags.init_done = 0;
		ha->isp_ops->disable_intrs(ha);
	}

	qla2x00_free_irqs(vha);

	qla2x00_free_fw_dump(ha);
3730 3731

	pci_disable_device(pdev);
3732 3733
	ql_log(ql_log_info, vha, 0xfffe,
		"Adapter shutdown successfully.\n");
3734 3735
}

3736
/* Deletes all the virtual ports for a given ha */
3737
static void
3738
qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
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3739
{
3740
	scsi_qla_host_t *vha;
3741
	unsigned long flags;
3742

3743 3744 3745
	mutex_lock(&ha->vport_lock);
	while (ha->cur_vport_count) {
		spin_lock_irqsave(&ha->vport_slock, flags);
3746

3747 3748 3749
		BUG_ON(base_vha->list.next == &ha->vp_list);
		/* This assumes first entry in ha->vp_list is always base vha */
		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3750
		scsi_host_get(vha->host);
3751

3752 3753 3754
		spin_unlock_irqrestore(&ha->vport_slock, flags);
		mutex_unlock(&ha->vport_lock);

3755 3756
		qla_nvme_delete(vha);

3757 3758
		fc_vport_terminate(vha->fc_vport);
		scsi_host_put(vha->host);
3759

3760
		mutex_lock(&ha->vport_lock);
3761
	}
3762
	mutex_unlock(&ha->vport_lock);
3763
}
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3764

3765 3766 3767 3768
/* Stops all deferred work threads */
static void
qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
{
3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783
	/* Cancel all work and destroy DPC workqueues */
	if (ha->dpc_lp_wq) {
		cancel_work_sync(&ha->idc_aen);
		destroy_workqueue(ha->dpc_lp_wq);
		ha->dpc_lp_wq = NULL;
	}

	if (ha->dpc_hp_wq) {
		cancel_work_sync(&ha->nic_core_reset);
		cancel_work_sync(&ha->idc_state_handler);
		cancel_work_sync(&ha->nic_core_unrecoverable);
		destroy_workqueue(ha->dpc_hp_wq);
		ha->dpc_hp_wq = NULL;
	}

3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794
	/* Kill the kernel thread for this host */
	if (ha->dpc_thread) {
		struct task_struct *t = ha->dpc_thread;

		/*
		 * qla2xxx_wake_dpc checks for ->dpc_thread
		 * so we need to zero it out.
		 */
		ha->dpc_thread = NULL;
		kthread_stop(t);
	}
3795
}
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3796

3797 3798 3799
static void
qla2x00_unmap_iobases(struct qla_hw_data *ha)
{
3800
	if (IS_QLA82XX(ha)) {
3801

3802
		iounmap((device_reg_t *)ha->nx_pcibase);
3803
		if (!ql2xdbwr)
3804
			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3805 3806 3807
	} else {
		if (ha->iobase)
			iounmap(ha->iobase);
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3808

3809 3810 3811
		if (ha->cregbase)
			iounmap(ha->cregbase);

3812 3813
		if (ha->mqiobase)
			iounmap(ha->mqiobase);
3814

3815
		if (ha->msixbase)
3816
			iounmap(ha->msixbase);
3817
	}
3818 3819 3820
}

static void
3821
qla2x00_clear_drv_active(struct qla_hw_data *ha)
3822 3823 3824
{
	if (IS_QLA8044(ha)) {
		qla8044_idc_lock(ha);
3825
		qla8044_clear_drv_active(ha);
3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839
		qla8044_idc_unlock(ha);
	} else if (IS_QLA82XX(ha)) {
		qla82xx_idc_lock(ha);
		qla82xx_clear_drv_active(ha);
		qla82xx_idc_unlock(ha);
	}
}

static void
qla2x00_remove_one(struct pci_dev *pdev)
{
	scsi_qla_host_t *base_vha;
	struct qla_hw_data  *ha;

3840 3841
	base_vha = pci_get_drvdata(pdev);
	ha = base_vha->hw;
3842 3843
	ql_log(ql_log_info, base_vha, 0xb079,
	    "Removing driver\n");
3844
	__qla_set_remove_flag(base_vha);
3845 3846
	cancel_work_sync(&ha->board_disable);

3847
	/*
3848 3849 3850
	 * If the PCI device is disabled then there was a PCI-disconnect and
	 * qla2x00_disable_board_on_pci_error has taken care of most of the
	 * resources.
3851
	 */
3852
	if (!atomic_read(&pdev->enable_cnt)) {
3853 3854
		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
		    base_vha->gnl.l, base_vha->gnl.ldma);
3855
		base_vha->gnl.l = NULL;
3856 3857 3858
		scsi_host_put(base_vha->host);
		kfree(ha);
		pci_set_drvdata(pdev, NULL);
3859
		return;
3860
	}
3861 3862
	qla2x00_wait_for_hba_ready(base_vha);

3863 3864 3865 3866 3867 3868 3869
	/*
	 * if UNLOADING flag is already set, then continue unload,
	 * where it was set first.
	 */
	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
		return;

3870 3871
	if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
	    IS_QLA28XX(ha)) {
3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885
		if (ha->flags.fw_started)
			qla2x00_abort_isp_cleanup(base_vha);
	} else if (!IS_QLAFX00(ha)) {
		if (IS_QLA8031(ha)) {
			ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
			    "Clearing fcoe driver presence.\n");
			if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
				ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
				    "Error while clearing DRV-Presence.\n");
		}

		qla2x00_try_to_stop_firmware(base_vha);
	}

3886 3887
	qla2x00_wait_for_sess_deletion(base_vha);

3888 3889
	qla_nvme_delete(base_vha);

3890 3891
	dma_free_coherent(&ha->pdev->dev,
		base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3892

3893
	base_vha->gnl.l = NULL;
3894
	qla_enode_stop(base_vha);
3895
	qla_edb_stop(base_vha);
3896

3897 3898
	vfree(base_vha->scan.l);

3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913
	if (IS_QLAFX00(ha))
		qlafx00_driver_shutdown(base_vha, 20);

	qla2x00_delete_all_vps(ha, base_vha);

	qla2x00_dfs_remove(base_vha);

	qla84xx_put_chip(base_vha);

	/* Disable timer */
	if (base_vha->timer_active)
		qla2x00_stop_timer(base_vha);

	base_vha->flags.online = 0;

3914 3915 3916 3917
	/* free DMA memory */
	if (ha->exlogin_buf)
		qla2x00_free_exlogin_buffer(ha);

3918 3919 3920 3921
	/* free DMA memory */
	if (ha->exchoffld_buf)
		qla2x00_free_exchoffld_buffer(ha);

3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933
	qla2x00_destroy_deferred_work(ha);

	qlt_remove_target(ha, base_vha);

	qla2x00_free_sysfs_attr(base_vha, true);

	fc_remove_host(base_vha->host);

	scsi_remove_host(base_vha->host);

	qla2x00_free_device(base_vha);

3934
	qla2x00_clear_drv_active(ha);
3935

3936 3937
	scsi_host_put(base_vha->host);

3938
	qla2x00_unmap_iobases(ha);
3939

3940 3941
	pci_release_selected_regions(ha->pdev, ha->bars);
	kfree(ha);
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3942

3943 3944
	pci_disable_pcie_error_reporting(pdev);

3945
	pci_disable_device(pdev);
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3946 3947
}

3948 3949 3950
static inline void
qla24xx_free_purex_list(struct purex_list *list)
{
3951
	struct purex_item *item, *next;
3952 3953 3954
	ulong flags;

	spin_lock_irqsave(&list->lock, flags);
3955 3956
	list_for_each_entry_safe(item, next, &list->head, list) {
		list_del(&item->list);
3957 3958
		if (item == &item->vha->default_item)
			continue;
3959
		kfree(item);
3960 3961 3962 3963
	}
	spin_unlock_irqrestore(&list->lock, flags);
}

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3964
static void
3965
qla2x00_free_device(scsi_qla_host_t *vha)
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3966
{
3967
	struct qla_hw_data *ha = vha->hw;
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3968

3969 3970 3971 3972 3973 3974
	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);

	/* Disable timer */
	if (vha->timer_active)
		qla2x00_stop_timer(vha);

3975
	qla25xx_delete_queues(vha);
3976 3977
	vha->flags.online = 0;

3978
	/* turn-off interrupts on the card */
3979 3980
	if (ha->interrupts_on) {
		vha->flags.init_done = 0;
3981
		ha->isp_ops->disable_intrs(ha);
3982
	}
3983

3984 3985
	qla2x00_free_fcports(vha);

3986
	qla2x00_free_irqs(vha);
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3987

3988 3989 3990 3991 3992 3993
	/* Flush the work queue and remove it */
	if (ha->wq) {
		destroy_workqueue(ha->wq);
		ha->wq = NULL;
	}

3994

3995 3996
	qla24xx_free_purex_list(&vha->purex_list);

3997
	qla2x00_mem_free(ha);
3998

3999 4000
	qla82xx_md_free(vha);

4001 4002 4003
	qla_edif_sadb_release_free_pool(ha);
	qla_edif_sadb_release(ha);

4004
	qla2x00_free_queues(ha);
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4005 4006
}

4007 4008 4009 4010
void qla2x00_free_fcports(struct scsi_qla_host *vha)
{
	fc_port_t *fcport, *tfcport;

4011 4012
	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
		qla2x00_free_fcport(fcport);
4013 4014
}

4015
static inline void
4016
qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4017
{
4018
	int now;
4019 4020 4021 4022

	if (!fcport->rport)
		return;

4023 4024 4025 4026 4027 4028
	if (fcport->rport) {
		ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
		    "%s %8phN. rport %p roles %x\n",
		    __func__, fcport->port_name, fcport->rport,
		    fcport->rport->roles);
		fc_remote_port_delete(fcport->rport);
4029
	}
4030
	qlt_do_generation_tick(vha, &now);
4031 4032
}

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4033 4034 4035 4036 4037 4038 4039 4040 4041
/*
 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
 *
 * Input: ha = adapter block pointer.  fcport = port structure pointer.
 *
 * Return: None.
 *
 * Context:
 */
4042
void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4043
    int do_login)
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Linus Torvalds committed
4044
{
4045 4046
	if (IS_QLAFX00(vha->hw)) {
		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4047
		qla2x00_schedule_rport_del(vha, fcport);
4048 4049 4050
		return;
	}

4051
	if (atomic_read(&fcport->state) == FCS_ONLINE &&
4052
	    vha->vp_idx == fcport->vha->vp_idx) {
4053
		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4054
		qla2x00_schedule_rport_del(vha, fcport);
4055
	}
4056

4057
	/*
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Linus Torvalds committed
4058 4059 4060 4061
	 * We may need to retry the login, so don't change the state of the
	 * port but do the retries.
	 */
	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4062
		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
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4063 4064 4065 4066

	if (!do_login)
		return;

4067
	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
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4068 4069 4070
}

void
4071
qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
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4072 4073 4074
{
	fc_port_t *fcport;

4075 4076
	ql_dbg(ql_dbg_disc, vha, 0x20f1,
	    "Mark all dev lost\n");
4077

4078
	list_for_each_entry(fcport, &vha->vp_fcports, list) {
4079 4080 4081 4082 4083 4084 4085 4086 4087 4088
		if (fcport->loop_id != FC_NO_LOOP_ID &&
		    (fcport->flags & FCF_FCP2_DEVICE) &&
		    fcport->port_type == FCT_TARGET &&
		    !qla2x00_reset_active(vha)) {
			ql_dbg(ql_dbg_disc, vha, 0x211a,
			       "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
			       fcport->flags, fcport->port_type,
			       fcport->d_id.b24, fcport->port_name);
			continue;
		}
4089
		fcport->scan_state = 0;
4090
		qlt_schedule_sess_for_deletion(fcport);
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4091 4092 4093
	}
}

4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106
static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
{
	int i;

	if (IS_FWI2_CAPABLE(ha))
		return;

	for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
		set_bit(i, ha->loop_id_map);
	set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
	set_bit(BROADCAST, ha->loop_id_map);
}

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4107 4108 4109 4110 4111 4112
/*
* qla2x00_mem_alloc
*      Allocates adapter memory.
*
* Returns:
*      0  = success.
4113
*      !0  = failure.
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4114
*/
4115
static int
4116 4117
qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
	struct req_que **req, struct rsp_que **rsp)
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4118 4119
{
	char	name[16];
4120
	int rc;
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4121

4122
	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4123
		&ha->init_cb_dma, GFP_KERNEL);
4124
	if (!ha->init_cb)
4125
		goto fail;
4126

4127 4128
	rc = btree_init32(&ha->host_map);
	if (rc)
4129 4130
		goto fail_free_init_cb;

4131 4132 4133
	if (qlt_mem_alloc(ha) < 0)
		goto fail_free_btree;

4134 4135
	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4136
	if (!ha->gid_list)
4137
		goto fail_free_tgt_mem;
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4138

4139 4140
	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
	if (!ha->srb_mempool)
4141
		goto fail_free_gid_list;
4142

4143
	if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4144 4145 4146 4147 4148 4149
		/* Allocate cache for CT6 Ctx. */
		if (!ctx_cachep) {
			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
				sizeof(struct ct6_dsd), 0,
				SLAB_HWCACHE_ALIGN, NULL);
			if (!ctx_cachep)
4150
				goto fail_free_srb_mempool;
4151 4152 4153 4154 4155
		}
		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
			ctx_cachep);
		if (!ha->ctx_mempool)
			goto fail_free_srb_mempool;
4156 4157 4158
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
		    "ctx_cachep=%p ctx_mempool=%p.\n",
		    ctx_cachep, ha->ctx_mempool);
4159 4160
	}

4161 4162 4163
	/* Get memory for cached NVRAM */
	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
	if (!ha->nvram)
4164
		goto fail_free_ctx_mempool;
4165

4166 4167 4168 4169 4170 4171 4172
	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
		ha->pdev->device);
	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
		DMA_POOL_SIZE, 8, 0);
	if (!ha->s_dma_pool)
		goto fail_free_nvram;

4173 4174 4175 4176
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);

4177
	if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4178 4179 4180
		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
			DSD_LIST_DMA_POOL_SIZE, 8, 0);
		if (!ha->dl_dma_pool) {
4181 4182
			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
			    "Failed to allocate memory for dl_dma_pool.\n");
4183 4184 4185 4186 4187 4188
			goto fail_s_dma_pool;
		}

		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
			FCP_CMND_DMA_POOL_SIZE, 8, 0);
		if (!ha->fcp_cmnd_dma_pool) {
4189 4190
			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4191 4192
			goto fail_dl_dma_pool;
		}
4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217

		if (ql2xenabledif) {
			u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
			struct dsd_dma *dsd, *nxt;
			uint i;
			/* Creata a DMA pool of buffers for DIF bundling */
			ha->dif_bundl_pool = dma_pool_create(name,
			    &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
			if (!ha->dif_bundl_pool) {
				ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
				    "%s: failed create dif_bundl_pool\n",
				    __func__);
				goto fail_dif_bundl_dma_pool;
			}

			INIT_LIST_HEAD(&ha->pool.good.head);
			INIT_LIST_HEAD(&ha->pool.unusable.head);
			ha->pool.good.count = 0;
			ha->pool.unusable.count = 0;
			for (i = 0; i < 128; i++) {
				dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
				if (!dsd) {
					ql_dbg_pci(ql_dbg_init, ha->pdev,
					    0xe0ee, "%s: failed alloc dsd\n",
					    __func__);
4218
					return -ENOMEM;
4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268
				}
				ha->dif_bundle_kallocs++;

				dsd->dsd_addr = dma_pool_alloc(
				    ha->dif_bundl_pool, GFP_ATOMIC,
				    &dsd->dsd_list_dma);
				if (!dsd->dsd_addr) {
					ql_dbg_pci(ql_dbg_init, ha->pdev,
					    0xe0ee,
					    "%s: failed alloc ->dsd_addr\n",
					    __func__);
					kfree(dsd);
					ha->dif_bundle_kallocs--;
					continue;
				}
				ha->dif_bundle_dma_allocs++;

				/*
				 * if DMA buffer crosses 4G boundary,
				 * put it on bad list
				 */
				if (MSD(dsd->dsd_list_dma) ^
				    MSD(dsd->dsd_list_dma + bufsize)) {
					list_add_tail(&dsd->list,
					    &ha->pool.unusable.head);
					ha->pool.unusable.count++;
				} else {
					list_add_tail(&dsd->list,
					    &ha->pool.good.head);
					ha->pool.good.count++;
				}
			}

			/* return the good ones back to the pool */
			list_for_each_entry_safe(dsd, nxt,
			    &ha->pool.good.head, list) {
				list_del(&dsd->list);
				dma_pool_free(ha->dif_bundl_pool,
				    dsd->dsd_addr, dsd->dsd_list_dma);
				ha->dif_bundle_dma_allocs--;
				kfree(dsd);
				ha->dif_bundle_kallocs--;
			}

			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
			    "%s: dif dma pool (good=%u unusable=%u)\n",
			    __func__, ha->pool.good.count,
			    ha->pool.unusable.count);
		}

4269
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4270 4271 4272
		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
		    ha->dif_bundl_pool);
4273 4274
	}

4275 4276
	/* Allocate memory for SNS commands */
	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4277
	/* Get consistent memory allocated for SNS commands */
4278
		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4279
		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4280
		if (!ha->sns_cmd)
4281
			goto fail_dma_pool;
4282
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4283
		    "sns_cmd: %p.\n", ha->sns_cmd);
4284
	} else {
4285
	/* Get consistent memory allocated for MS IOCB */
4286
		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4287
			&ha->ms_iocb_dma);
4288
		if (!ha->ms_iocb)
4289 4290
			goto fail_dma_pool;
	/* Get consistent memory allocated for CT SNS commands */
4291
		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4292
			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4293 4294
		if (!ha->ct_sns)
			goto fail_free_ms_iocb;
4295 4296 4297
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
		    "ms_iocb=%p ct_sns=%p.\n",
		    ha->ms_iocb, ha->ct_sns);
Linus Torvalds's avatar
Linus Torvalds committed
4298 4299
	}

4300
	/* Allocate memory for request ring */
4301 4302
	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
	if (!*req) {
4303 4304
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
		    "Failed to allocate memory for req.\n");
4305 4306
		goto fail_req;
	}
4307 4308 4309 4310 4311
	(*req)->length = req_len;
	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
		((*req)->length + 1) * sizeof(request_t),
		&(*req)->dma, GFP_KERNEL);
	if (!(*req)->ring) {
4312 4313
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
		    "Failed to allocate memory for req_ring.\n");
4314 4315 4316
		goto fail_req_ring;
	}
	/* Allocate memory for response ring */
4317 4318
	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
	if (!*rsp) {
4319 4320
		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
		    "Failed to allocate memory for rsp.\n");
4321 4322
		goto fail_rsp;
	}
4323 4324 4325 4326 4327 4328
	(*rsp)->hw = ha;
	(*rsp)->length = rsp_len;
	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
		((*rsp)->length + 1) * sizeof(response_t),
		&(*rsp)->dma, GFP_KERNEL);
	if (!(*rsp)->ring) {
4329 4330
		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
		    "Failed to allocate memory for rsp_ring.\n");
4331 4332
		goto fail_rsp_ring;
	}
4333 4334
	(*req)->rsp = *rsp;
	(*rsp)->req = *req;
4335 4336 4337 4338 4339
	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
	    "req=%p req->length=%d req->ring=%p rsp=%p "
	    "rsp->length=%d rsp->ring=%p.\n",
	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
	    (*rsp)->ring);
4340 4341
	/* Allocate memory for NVRAM data for vports */
	if (ha->nvram_npiv_size) {
4342 4343 4344
		ha->npiv_info = kcalloc(ha->nvram_npiv_size,
					sizeof(struct qla_npiv_entry),
					GFP_KERNEL);
4345
		if (!ha->npiv_info) {
4346 4347
			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
			    "Failed to allocate memory for npiv_info.\n");
4348 4349 4350 4351
			goto fail_npiv_info;
		}
	} else
		ha->npiv_info = NULL;
4352

4353
	/* Get consistent memory allocated for EX-INIT-CB. */
4354 4355
	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
	    IS_QLA28XX(ha)) {
4356 4357 4358 4359
		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
		    &ha->ex_init_cb_dma);
		if (!ha->ex_init_cb)
			goto fail_ex_init_cb;
4360 4361
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
		    "ex_init_cb=%p.\n", ha->ex_init_cb);
4362 4363
	}

4364 4365
	/* Get consistent memory allocated for Special Features-CB. */
	if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4366
		ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4367 4368 4369 4370 4371 4372 4373
						&ha->sf_init_cb_dma);
		if (!ha->sf_init_cb)
			goto fail_sf_init_cb;
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
			   "sf_init_cb=%p.\n", ha->sf_init_cb);
	}

4374 4375
	INIT_LIST_HEAD(&ha->gbl_dsd_list);

4376 4377 4378 4379 4380 4381
	/* Get consistent memory allocated for Async Port-Database. */
	if (!IS_FWI2_CAPABLE(ha)) {
		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
			&ha->async_pd_dma);
		if (!ha->async_pd)
			goto fail_async_pd;
4382 4383
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
		    "async_pd=%p.\n", ha->async_pd);
4384 4385
	}

4386
	INIT_LIST_HEAD(&ha->vp_list);
4387 4388

	/* Allocate memory for our loop_id bitmap */
4389 4390 4391
	ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
				  sizeof(long),
				  GFP_KERNEL);
4392
	if (!ha->loop_id_map)
4393
		goto fail_loop_id_map;
4394 4395 4396
	else {
		qla2x00_set_reserved_loop_ids(ha);
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4397
		    "loop_id_map=%p.\n", ha->loop_id_map);
4398 4399
	}

4400 4401 4402 4403 4404 4405 4406 4407
	ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
	    SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
	if (!ha->sfp_data) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
		    "Unable to allocate memory for SFP read-data.\n");
		goto fail_sfp_data;
	}

4408 4409 4410 4411 4412 4413 4414 4415 4416
	ha->flt = dma_alloc_coherent(&ha->pdev->dev,
	    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
	    GFP_KERNEL);
	if (!ha->flt) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
		    "Unable to allocate memory for FLT.\n");
		goto fail_flt_buffer;
	}

4417 4418
	/* allocate the purex dma pool */
	ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4419
	    ELS_MAX_PAYLOAD, 8, 0);
4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436

	if (!ha->purex_dma_pool) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
		    "Unable to allocate purex_dma_pool.\n");
		goto fail_flt;
	}

	ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
	ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
	    ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL);

	if (!ha->elsrej.c) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
		    "Alloc failed for els reject cmd.\n");
		goto fail_elsrej;
	}
	ha->elsrej.c->er_cmd = ELS_LS_RJT;
4437
	ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4438
	ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4439
	return 0;
4440

4441 4442 4443 4444 4445 4446
fail_elsrej:
	dma_pool_destroy(ha->purex_dma_pool);
fail_flt:
	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
	    ha->flt, ha->flt_dma);

4447 4448 4449
fail_flt_buffer:
	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
	    ha->sfp_data, ha->sfp_data_dma);
4450 4451
fail_sfp_data:
	kfree(ha->loop_id_map);
4452 4453
fail_loop_id_map:
	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4454
fail_async_pd:
4455 4456
	dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
fail_sf_init_cb:
4457
	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4458 4459
fail_ex_init_cb:
	kfree(ha->npiv_info);
4460 4461 4462 4463 4464
fail_npiv_info:
	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
	(*rsp)->ring = NULL;
	(*rsp)->dma = 0;
4465
fail_rsp_ring:
4466
	kfree(*rsp);
4467
	*rsp = NULL;
4468
fail_rsp:
4469 4470 4471 4472
	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
		sizeof(request_t), (*req)->ring, (*req)->dma);
	(*req)->ring = NULL;
	(*req)->dma = 0;
4473
fail_req_ring:
4474
	kfree(*req);
4475
	*req = NULL;
4476 4477 4478 4479 4480
fail_req:
	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
		ha->ct_sns, ha->ct_sns_dma);
	ha->ct_sns = NULL;
	ha->ct_sns_dma = 0;
4481 4482 4483 4484
fail_free_ms_iocb:
	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
	ha->ms_iocb = NULL;
	ha->ms_iocb_dma = 0;
4485 4486 4487 4488

	if (ha->sns_cmd)
		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
		    ha->sns_cmd, ha->sns_cmd_dma);
4489
fail_dma_pool:
4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507
	if (ql2xenabledif) {
		struct dsd_dma *dsd, *nxt;

		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
		    list) {
			list_del(&dsd->list);
			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
			    dsd->dsd_list_dma);
			ha->dif_bundle_dma_allocs--;
			kfree(dsd);
			ha->dif_bundle_kallocs--;
			ha->pool.unusable.count--;
		}
		dma_pool_destroy(ha->dif_bundl_pool);
		ha->dif_bundl_pool = NULL;
	}

fail_dif_bundl_dma_pool:
4508
	if (IS_QLA82XX(ha) || ql2xenabledif) {
4509 4510 4511 4512
		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
		ha->fcp_cmnd_dma_pool = NULL;
	}
fail_dl_dma_pool:
4513
	if (IS_QLA82XX(ha) || ql2xenabledif) {
4514 4515 4516 4517
		dma_pool_destroy(ha->dl_dma_pool);
		ha->dl_dma_pool = NULL;
	}
fail_s_dma_pool:
4518 4519
	dma_pool_destroy(ha->s_dma_pool);
	ha->s_dma_pool = NULL;
4520 4521 4522
fail_free_nvram:
	kfree(ha->nvram);
	ha->nvram = NULL;
4523
fail_free_ctx_mempool:
4524
	mempool_destroy(ha->ctx_mempool);
4525
	ha->ctx_mempool = NULL;
4526
fail_free_srb_mempool:
4527
	mempool_destroy(ha->srb_mempool);
4528 4529
	ha->srb_mempool = NULL;
fail_free_gid_list:
4530 4531
	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
	ha->gid_list,
4532
	ha->gid_list_dma);
4533 4534
	ha->gid_list = NULL;
	ha->gid_list_dma = 0;
4535 4536
fail_free_tgt_mem:
	qlt_mem_free(ha);
4537 4538
fail_free_btree:
	btree_destroy32(&ha->host_map);
4539 4540 4541 4542 4543
fail_free_init_cb:
	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
	ha->init_cb_dma);
	ha->init_cb = NULL;
	ha->init_cb_dma = 0;
4544
fail:
4545 4546
	ql_log(ql_log_fatal, NULL, 0x0030,
	    "Memory allocation failure.\n");
4547
	return -ENOMEM;
Linus Torvalds's avatar
Linus Torvalds committed
4548 4549
}

4550 4551 4552 4553
int
qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
{
	int rval;
4554 4555
	uint16_t	size, max_cnt;
	uint32_t temp;
4556 4557 4558
	struct qla_hw_data *ha = vha->hw;

	/* Return if we don't need to alloacate any extended logins */
4559
	if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4560 4561
		return QLA_SUCCESS;

4562 4563 4564
	if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
		return QLA_SUCCESS;

4565 4566 4567 4568 4569 4570 4571 4572 4573 4574
	ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
	max_cnt = 0;
	rval = qla_get_exlogin_status(vha, &size, &max_cnt);
	if (rval != QLA_SUCCESS) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
		    "Failed to get exlogin status.\n");
		return rval;
	}

	temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592
	temp *= size;

	if (temp != ha->exlogin_size) {
		qla2x00_free_exlogin_buffer(ha);
		ha->exlogin_size = temp;

		ql_log(ql_log_info, vha, 0xd024,
		    "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
		    max_cnt, size, temp);

		ql_log(ql_log_info, vha, 0xd025,
		    "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);

		/* Get consistent memory for extended logins */
		ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
			ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
		if (!ha->exlogin_buf) {
			ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4593
		    "Failed to allocate memory for exlogin_buf_dma.\n");
4594 4595
			return -ENOMEM;
		}
4596 4597 4598 4599 4600
	}

	/* Now configure the dma buffer */
	rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
	if (rval) {
4601
		ql_log(ql_log_fatal, vha, 0xd033,
4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625
		    "Setup extended login buffer  ****FAILED****.\n");
		qla2x00_free_exlogin_buffer(ha);
	}

	return rval;
}

/*
* qla2x00_free_exlogin_buffer
*
* Input:
*	ha = adapter block pointer
*/
void
qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
{
	if (ha->exlogin_buf) {
		dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
		    ha->exlogin_buf, ha->exlogin_buf_dma);
		ha->exlogin_buf = NULL;
		ha->exlogin_size = 0;
	}
}

4626 4627 4628 4629
static void
qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
{
	u32 temp;
4630
	struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4631 4632
	*ret_cnt = FW_DEF_EXCHANGES_CNT;

4633 4634 4635
	if (max_cnt > vha->hw->max_exchg)
		max_cnt = vha->hw->max_exchg;

4636
	if (qla_ini_mode_enabled(vha)) {
4637 4638 4639 4640 4641
		if (vha->ql2xiniexchg > max_cnt)
			vha->ql2xiniexchg = max_cnt;

		if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
			*ret_cnt = vha->ql2xiniexchg;
4642 4643

	} else if (qla_tgt_mode_enabled(vha)) {
4644 4645 4646 4647
		if (vha->ql2xexchoffld > max_cnt) {
			vha->ql2xexchoffld = max_cnt;
			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
		}
4648

4649 4650
		if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
			*ret_cnt = vha->ql2xexchoffld;
4651
	} else if (qla_dual_mode_enabled(vha)) {
4652
		temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4653
		if (temp > max_cnt) {
4654 4655
			vha->ql2xiniexchg -= (temp - max_cnt)/2;
			vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4656
			temp = max_cnt;
4657
			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4658 4659 4660 4661 4662 4663 4664
		}

		if (temp > FW_DEF_EXCHANGES_CNT)
			*ret_cnt = temp;
	}
}

4665 4666 4667 4668
int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
{
	int rval;
4669 4670
	u16	size, max_cnt;
	u32 actual_cnt, totsz;
4671 4672
	struct qla_hw_data *ha = vha->hw;

4673 4674 4675 4676
	if (!ha->flags.exchoffld_enabled)
		return QLA_SUCCESS;

	if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4677 4678 4679 4680 4681 4682 4683 4684 4685 4686
		return QLA_SUCCESS;

	max_cnt = 0;
	rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
	if (rval != QLA_SUCCESS) {
		ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
		    "Failed to get exlogin status.\n");
		return rval;
	}

4687 4688 4689 4690 4691
	qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
	ql_log(ql_log_info, vha, 0xd014,
	    "Actual exchange offload count: %d.\n", actual_cnt);

	totsz = actual_cnt * size;
4692

4693
	if (totsz != ha->exchoffld_size) {
4694
		qla2x00_free_exchoffld_buffer(ha);
4695 4696 4697 4698 4699 4700
		if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
			ha->exchoffld_size = 0;
			ha->flags.exchoffld_enabled = 0;
			return QLA_SUCCESS;
		}

4701
		ha->exchoffld_size = totsz;
4702 4703

		ql_log(ql_log_info, vha, 0xd016,
4704 4705
		    "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
		    max_cnt, actual_cnt, size, totsz);
4706 4707 4708 4709 4710 4711 4712 4713 4714 4715

		ql_log(ql_log_info, vha, 0xd017,
		    "Exchange Buffers requested size = 0x%x\n",
		    ha->exchoffld_size);

		/* Get consistent memory for extended logins */
		ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
			ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
		if (!ha->exchoffld_buf) {
			ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730
			"Failed to allocate memory for Exchange Offload.\n");

			if (ha->max_exchg >
			    (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
				ha->max_exchg -= REDUCE_EXCHANGES_CNT;
			} else if (ha->max_exchg >
			    (FW_DEF_EXCHANGES_CNT + 512)) {
				ha->max_exchg -= 512;
			} else {
				ha->flags.exchoffld_enabled = 0;
				ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
				    "Disabling Exchange offload due to lack of memory\n");
			}
			ha->exchoffld_size = 0;

4731 4732
			return -ENOMEM;
		}
4733 4734 4735 4736 4737 4738 4739 4740 4741
	} else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
		/* pathological case */
		qla2x00_free_exchoffld_buffer(ha);
		ha->exchoffld_size = 0;
		ha->flags.exchoffld_enabled = 0;
		ql_log(ql_log_info, vha, 0xd016,
		    "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
		    ha->exchoffld_size, actual_cnt, size, totsz);
		return 0;
4742 4743 4744
	}

	/* Now configure the dma buffer */
4745
	rval = qla_set_exchoffld_mem_cfg(vha);
4746 4747 4748 4749
	if (rval) {
		ql_log(ql_log_fatal, vha, 0xd02e,
		    "Setup exchange offload buffer ****FAILED****.\n");
		qla2x00_free_exchoffld_buffer(ha);
4750 4751 4752 4753 4754 4755 4756
	} else {
		/* re-adjust number of target exchange */
		struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;

		if (qla_ini_mode_enabled(vha))
			icb->exchange_count = 0;
		else
4757
			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779
	}

	return rval;
}

/*
* qla2x00_free_exchoffld_buffer
*
* Input:
*	ha = adapter block pointer
*/
void
qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
{
	if (ha->exchoffld_buf) {
		dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
		    ha->exchoffld_buf, ha->exchoffld_buf_dma);
		ha->exchoffld_buf = NULL;
		ha->exchoffld_size = 0;
	}
}

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4780
/*
4781 4782
* qla2x00_free_fw_dump
*	Frees fw dump stuff.
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4783 4784
*
* Input:
4785
*	ha = adapter block pointer
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4786
*/
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4787
static void
4788
qla2x00_free_fw_dump(struct qla_hw_data *ha)
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4789
{
4790 4791 4792
	struct fwdt *fwdt = ha->fwdt;
	uint j;

4793
	if (ha->fce)
4794 4795
		dma_free_coherent(&ha->pdev->dev,
		    FCE_SIZE, ha->fce, ha->fce_dma);
4796

4797 4798 4799 4800
	if (ha->eft)
		dma_free_coherent(&ha->pdev->dev,
		    EFT_SIZE, ha->eft, ha->eft_dma);

4801
	vfree(ha->fw_dump);
4802

4803 4804
	ha->fce = NULL;
	ha->fce_dma = 0;
4805
	ha->flags.fce_enabled = 0;
4806 4807
	ha->eft = NULL;
	ha->eft_dma = 0;
4808
	ha->fw_dumped = false;
4809
	ha->fw_dump_cap_flags = 0;
4810
	ha->fw_dump_reading = 0;
4811 4812
	ha->fw_dump = NULL;
	ha->fw_dump_len = 0;
4813 4814

	for (j = 0; j < 2; j++, fwdt++) {
4815
		vfree(fwdt->template);
4816 4817 4818
		fwdt->template = NULL;
		fwdt->length = 0;
	}
4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832
}

/*
* qla2x00_mem_free
*      Frees all adapter allocated memory.
*
* Input:
*      ha = adapter block pointer.
*/
static void
qla2x00_mem_free(struct qla_hw_data *ha)
{
	qla2x00_free_fw_dump(ha);

4833 4834 4835
	if (ha->mctp_dump)
		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
		    ha->mctp_dump_dma);
4836
	ha->mctp_dump = NULL;
4837

4838
	mempool_destroy(ha->srb_mempool);
4839
	ha->srb_mempool = NULL;
4840

4841 4842 4843
	if (ha->dcbx_tlv)
		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
4844
	ha->dcbx_tlv = NULL;
4845

4846 4847 4848
	if (ha->xgmac_data)
		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
		    ha->xgmac_data, ha->xgmac_data_dma);
4849
	ha->xgmac_data = NULL;
4850

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4851 4852
	if (ha->sns_cmd)
		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4853
		ha->sns_cmd, ha->sns_cmd_dma);
4854 4855
	ha->sns_cmd = NULL;
	ha->sns_cmd_dma = 0;
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4856 4857 4858

	if (ha->ct_sns)
		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4859
		ha->ct_sns, ha->ct_sns_dma);
4860 4861
	ha->ct_sns = NULL;
	ha->ct_sns_dma = 0;
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4862

4863
	if (ha->sfp_data)
4864 4865
		dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
		    ha->sfp_data_dma);
4866
	ha->sfp_data = NULL;
4867

4868
	if (ha->flt)
4869 4870
		dma_free_coherent(&ha->pdev->dev,
		    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4871
		    ha->flt, ha->flt_dma);
4872 4873
	ha->flt = NULL;
	ha->flt_dma = 0;
4874

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4875 4876
	if (ha->ms_iocb)
		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4877 4878
	ha->ms_iocb = NULL;
	ha->ms_iocb_dma = 0;
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4879

4880 4881 4882 4883
	if (ha->sf_init_cb)
		dma_pool_free(ha->s_dma_pool,
			      ha->sf_init_cb, ha->sf_init_cb_dma);

4884
	if (ha->ex_init_cb)
4885 4886
		dma_pool_free(ha->s_dma_pool,
			ha->ex_init_cb, ha->ex_init_cb_dma);
4887 4888
	ha->ex_init_cb = NULL;
	ha->ex_init_cb_dma = 0;
4889

4890 4891
	if (ha->async_pd)
		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4892 4893
	ha->async_pd = NULL;
	ha->async_pd_dma = 0;
4894

4895
	dma_pool_destroy(ha->s_dma_pool);
4896
	ha->s_dma_pool = NULL;
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4897 4898

	if (ha->gid_list)
4899 4900
		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
		ha->gid_list, ha->gid_list_dma);
4901 4902
	ha->gid_list = NULL;
	ha->gid_list_dma = 0;
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4903

4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918
	if (IS_QLA82XX(ha)) {
		if (!list_empty(&ha->gbl_dsd_list)) {
			struct dsd_dma *dsd_ptr, *tdsd_ptr;

			/* clean up allocated prev pool */
			list_for_each_entry_safe(dsd_ptr,
				tdsd_ptr, &ha->gbl_dsd_list, list) {
				dma_pool_free(ha->dl_dma_pool,
				dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
				list_del(&dsd_ptr->list);
				kfree(dsd_ptr);
			}
		}
	}

4919
	dma_pool_destroy(ha->dl_dma_pool);
4920
	ha->dl_dma_pool = NULL;
4921

4922
	dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4923
	ha->fcp_cmnd_dma_pool = NULL;
4924

4925
	mempool_destroy(ha->ctx_mempool);
4926
	ha->ctx_mempool = NULL;
4927

4928
	if (ql2xenabledif && ha->dif_bundl_pool) {
4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950
		struct dsd_dma *dsd, *nxt;

		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
					 list) {
			list_del(&dsd->list);
			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
				      dsd->dsd_list_dma);
			ha->dif_bundle_dma_allocs--;
			kfree(dsd);
			ha->dif_bundle_kallocs--;
			ha->pool.unusable.count--;
		}
		list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
			list_del(&dsd->list);
			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
				      dsd->dsd_list_dma);
			ha->dif_bundle_dma_allocs--;
			kfree(dsd);
			ha->dif_bundle_kallocs--;
		}
	}

4951
	dma_pool_destroy(ha->dif_bundl_pool);
4952
	ha->dif_bundl_pool = NULL;
4953

4954
	qlt_mem_free(ha);
4955
	qla_remove_hostmap(ha);
4956

4957 4958
	if (ha->init_cb)
		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4959
			ha->init_cb, ha->init_cb_dma);
4960 4961 4962 4963 4964 4965 4966 4967 4968 4969

	dma_pool_destroy(ha->purex_dma_pool);
	ha->purex_dma_pool = NULL;

	if (ha->elsrej.c) {
		dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
		    ha->elsrej.c, ha->elsrej.cdma);
		ha->elsrej.c = NULL;
	}

4970 4971
	ha->init_cb = NULL;
	ha->init_cb_dma = 0;
4972

4973
	vfree(ha->optrom_buffer);
4974
	ha->optrom_buffer = NULL;
4975
	kfree(ha->nvram);
4976
	ha->nvram = NULL;
4977
	kfree(ha->npiv_info);
4978
	ha->npiv_info = NULL;
4979
	kfree(ha->swl);
4980
	ha->swl = NULL;
4981
	kfree(ha->loop_id_map);
4982 4983
	ha->sf_init_cb = NULL;
	ha->sf_init_cb_dma = 0;
4984
	ha->loop_id_map = NULL;
4985
}
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4986

4987 4988 4989 4990 4991
struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
						struct qla_hw_data *ha)
{
	struct Scsi_Host *host;
	struct scsi_qla_host *vha = NULL;
4992

4993
	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4994
	if (!host) {
4995 4996
		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
		    "Failed to allocate host from the scsi layer, aborting.\n");
4997
		return NULL;
4998 4999 5000 5001 5002 5003 5004 5005 5006 5007
	}

	/* Clear our data area */
	vha = shost_priv(host);
	memset(vha, 0, sizeof(scsi_qla_host_t));

	vha->host = host;
	vha->host_no = host->host_no;
	vha->hw = ha;

5008 5009 5010 5011
	vha->qlini_mode = ql2x_ini_mode;
	vha->ql2xexchoffld = ql2xexchoffld;
	vha->ql2xiniexchg = ql2xiniexchg;

5012 5013 5014
	INIT_LIST_HEAD(&vha->vp_fcports);
	INIT_LIST_HEAD(&vha->work_list);
	INIT_LIST_HEAD(&vha->list);
5015
	INIT_LIST_HEAD(&vha->qla_cmd_list);
5016
	INIT_LIST_HEAD(&vha->logo_list);
5017
	INIT_LIST_HEAD(&vha->plogi_ack_list);
5018
	INIT_LIST_HEAD(&vha->qp_list);
5019
	INIT_LIST_HEAD(&vha->gnl.fcports);
5020
	INIT_LIST_HEAD(&vha->gpnid_list);
5021
	INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5022

5023 5024 5025
	INIT_LIST_HEAD(&vha->purex_list.head);
	spin_lock_init(&vha->purex_list.lock);

5026
	spin_lock_init(&vha->work_lock);
5027
	spin_lock_init(&vha->cmd_list_lock);
5028
	init_waitqueue_head(&vha->fcport_waitQ);
5029
	init_waitqueue_head(&vha->vref_waitq);
5030
	qla_enode_init(vha);
5031 5032
	qla_edb_init(vha);

5033

5034 5035
	vha->gnl.size = sizeof(struct get_name_list_extended) *
			(ha->max_loop_id + 1);
5036 5037 5038
	vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
	    vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
	if (!vha->gnl.l) {
5039
		ql_log(ql_log_fatal, vha, 0xd04a,
5040
		    "Alloc failed for name list.\n");
5041
		scsi_host_put(vha->host);
5042 5043
		return NULL;
	}
5044

5045 5046 5047 5048 5049 5050 5051 5052
	/* todo: what about ext login? */
	vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
	vha->scan.l = vmalloc(vha->scan.size);
	if (!vha->scan.l) {
		ql_log(ql_log_fatal, vha, 0xd04a,
		    "Alloc failed for scan database.\n");
		dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
		    vha->gnl.l, vha->gnl.ldma);
5053
		vha->gnl.l = NULL;
5054
		scsi_host_put(vha->host);
5055 5056
		return NULL;
	}
5057
	INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5058

5059
	sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no);
5060 5061 5062 5063 5064
	ql_dbg(ql_dbg_init, vha, 0x0041,
	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
	    vha->host, vha->hw, vha,
	    dev_name(&(ha->pdev->dev)));

5065
	return vha;
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5066 5067
}

5068
struct qla_work_evt *
5069
qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5070 5071
{
	struct qla_work_evt *e;
5072 5073
	uint8_t bail;

5074 5075 5076
	if (test_bit(UNLOADING, &vha->dpc_flags))
		return NULL;

5077 5078 5079
	QLA_VHA_MARK_BUSY(vha, bail);
	if (bail)
		return NULL;
5080

5081
	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5082 5083
	if (!e) {
		QLA_VHA_MARK_NOT_BUSY(vha);
5084
		return NULL;
5085
	}
5086 5087 5088 5089 5090 5091 5092

	INIT_LIST_HEAD(&e->list);
	e->type = type;
	e->flags = QLA_EVT_FLAG_FREE;
	return e;
}

5093
int
5094
qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5095
{
5096
	unsigned long flags;
5097
	bool q = false;
5098

5099
	spin_lock_irqsave(&vha->work_lock, flags);
5100
	list_add_tail(&e->list, &vha->work_list);
5101 5102 5103 5104

	if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
		q = true;

5105
	spin_unlock_irqrestore(&vha->work_lock, flags);
5106

5107 5108
	if (q)
		queue_work(vha->hw->wq, &vha->iocb_work);
5109

5110 5111 5112 5113
	return QLA_SUCCESS;
}

int
5114
qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5115 5116 5117 5118
    u32 data)
{
	struct qla_work_evt *e;

5119
	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5120 5121 5122 5123 5124
	if (!e)
		return QLA_FUNCTION_FAILED;

	e->u.aen.code = code;
	e->u.aen.data = data;
5125
	return qla2x00_post_work(vha, e);
5126 5127
}

5128 5129 5130 5131 5132
int
qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
{
	struct qla_work_evt *e;

5133
	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5134 5135 5136 5137
	if (!e)
		return QLA_FUNCTION_FAILED;

	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5138
	return qla2x00_post_work(vha, e);
5139 5140
}

5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156
#define qla2x00_post_async_work(name, type)	\
int qla2x00_post_async_##name##_work(		\
    struct scsi_qla_host *vha,			\
    fc_port_t *fcport, uint16_t *data)		\
{						\
	struct qla_work_evt *e;			\
						\
	e = qla2x00_alloc_work(vha, type);	\
	if (!e)					\
		return QLA_FUNCTION_FAILED;	\
						\
	e->u.logio.fcport = fcport;		\
	if (data) {				\
		e->u.logio.data[0] = data[0];	\
		e->u.logio.data[1] = data[1];	\
	}					\
5157
	fcport->flags |= FCF_ASYNC_ACTIVE;	\
5158 5159 5160 5161 5162
	return qla2x00_post_work(vha, e);	\
}

qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5163
qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5164 5165
qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5166

5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187
int
qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
{
	struct qla_work_evt *e;

	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
	if (!e)
		return QLA_FUNCTION_FAILED;

	e->u.uevent.code = code;
	return qla2x00_post_work(vha, e);
}

static void
qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
{
	char event_string[40];
	char *envp[] = { event_string, NULL };

	switch (code) {
	case QLA_UEVENT_CODE_FW_DUMP:
5188
		snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5189 5190 5191 5192 5193 5194 5195 5196 5197
		    vha->host_no);
		break;
	default:
		/* do nothing */
		break;
	}
	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
}

5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213
int
qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
			uint32_t *data, int cnt)
{
	struct qla_work_evt *e;

	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
	if (!e)
		return QLA_FUNCTION_FAILED;

	e->u.aenfx.evtcode = evtcode;
	e->u.aenfx.count = cnt;
	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
	return qla2x00_post_work(vha, e);
}

5214
void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5215
{
5216
	unsigned long flags;
5217

5218 5219
	if (IS_SW_RESV_ADDR(fcport->d_id))
		return;
5220

5221 5222 5223 5224 5225 5226 5227 5228
	spin_lock_irqsave(&fcport->vha->work_lock, flags);
	if (fcport->disc_state == DSC_UPD_FCPORT) {
		spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
		return;
	}
	fcport->jiffies_at_registration = jiffies;
	fcport->sec_since_registration = 0;
	fcport->next_disc_state = DSC_DELETED;
5229
	qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5230 5231 5232
	spin_unlock_irqrestore(&fcport->vha->work_lock, flags);

	queue_work(system_unbound_wq, &fcport->reg_work);
5233 5234 5235 5236 5237 5238
}

static
void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
{
	unsigned long flags;
5239
	fc_port_t *fcport =  NULL, *tfcp;
5240 5241
	struct qlt_plogi_ack_t *pla =
	    (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5242
	uint8_t free_fcport = 0;
5243

5244 5245 5246 5247
	ql_dbg(ql_dbg_disc, vha, 0xffff,
	    "%s %d %8phC enter\n",
	    __func__, __LINE__, e->u.new_sess.port_name);

5248 5249 5250 5251 5252 5253
	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
	fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
	if (fcport) {
		fcport->d_id = e->u.new_sess.id;
		if (pla) {
			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5254 5255 5256
			memcpy(fcport->node_name,
			    pla->iocb.u.isp24.u.plogi.node_name,
			    WWN_SIZE);
5257 5258 5259 5260 5261 5262 5263
			qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
			/* we took an extra ref_count to prevent PLOGI ACK when
			 * fcport/sess has not been created.
			 */
			pla->ref_count--;
		}
	} else {
5264
		spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5265 5266 5267 5268 5269
		fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
		if (fcport) {
			fcport->d_id = e->u.new_sess.id;
			fcport->flags |= FCF_FABRIC_DEVICE;
			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5270
			fcport->tgt_short_link_down_cnt = 0;
5271

5272 5273
			memcpy(fcport->port_name, e->u.new_sess.port_name,
			    WWN_SIZE);
5274

5275
			fcport->fc4_type = e->u.new_sess.fc4_type;
Quinn Tran's avatar
Quinn Tran committed
5276 5277 5278 5279 5280
			if (NVME_PRIORITY(vha->hw, fcport))
				fcport->do_prli_nvme = 1;
			else
				fcport->do_prli_nvme = 0;

5281
			if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5282 5283
				fcport->dm_login_expire = jiffies +
					QLA_N2N_WAIT_TIME * HZ;
5284
				fcport->fc4_type = FS_FC4TYPE_FCP;
5285
				fcport->n2n_flag = 1;
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				if (vha->flags.nvme_enabled)
					fcport->fc4_type |= FS_FC4TYPE_NVME;
			}
5289

5290 5291 5292 5293 5294
		} else {
			ql_dbg(ql_dbg_disc, vha, 0xffff,
				   "%s %8phC mem alloc fail.\n",
				   __func__, e->u.new_sess.port_name);

5295 5296
			if (pla) {
				list_del(&pla->list);
5297
				kmem_cache_free(qla_tgt_plogi_cachep, pla);
5298
			}
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			return;
		}

		spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5303
		/* search again to make sure no one else got ahead */
5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314
		tfcp = qla2x00_find_fcport_by_wwpn(vha,
		    e->u.new_sess.port_name, 1);
		if (tfcp) {
			/* should rarily happen */
			ql_dbg(ql_dbg_disc, vha, 0xffff,
			    "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
			    __func__, tfcp->port_name, tfcp->disc_state,
			    tfcp->fw_login_state);

			free_fcport = 1;
		} else {
5315 5316
			list_add_tail(&fcport->list, &vha->vp_fcports);

5317 5318 5319 5320 5321
		}
		if (pla) {
			qlt_plogi_ack_link(vha, pla, fcport,
			    QLT_PLOGI_LINK_SAME_WWN);
			pla->ref_count--;
5322 5323 5324 5325 5326
		}
	}
	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);

	if (fcport) {
5327 5328
		fcport->id_changed = 1;
		fcport->scan_state = QLA_FCPORT_FOUND;
5329
		fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5330 5331
		memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);

5332
		if (pla) {
5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353
			if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
				u16 wd3_lo;

				fcport->fw_login_state = DSC_LS_PRLI_PEND;
				fcport->local = 0;
				fcport->loop_id =
					le16_to_cpu(
					    pla->iocb.u.isp24.nport_handle);
				fcport->fw_login_state = DSC_LS_PRLI_PEND;
				wd3_lo =
				    le16_to_cpu(
					pla->iocb.u.isp24.u.prli.wd3_lo);

				if (wd3_lo & BIT_7)
					fcport->conf_compl_supported = 1;

				if ((wd3_lo & BIT_4) == 0)
					fcport->port_type = FCT_INITIATOR;
				else
					fcport->port_type = FCT_TARGET;
			}
5354
			qlt_plogi_ack_unref(vha, pla);
5355
		} else {
5356 5357
			fc_port_t *dfcp = NULL;

5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379
			spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
			tfcp = qla2x00_find_fcport_by_nportid(vha,
			    &e->u.new_sess.id, 1);
			if (tfcp && (tfcp != fcport)) {
				/*
				 * We have a conflict fcport with same NportID.
				 */
				ql_dbg(ql_dbg_disc, vha, 0xffff,
				    "%s %8phC found conflict b4 add. DS %d LS %d\n",
				    __func__, tfcp->port_name, tfcp->disc_state,
				    tfcp->fw_login_state);

				switch (tfcp->disc_state) {
				case DSC_DELETED:
					break;
				case DSC_DELETE_PEND:
					fcport->login_pause = 1;
					tfcp->conflict = fcport;
					break;
				default:
					fcport->login_pause = 1;
					tfcp->conflict = fcport;
5380
					dfcp = tfcp;
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					break;
				}
			}
			spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5385 5386
			if (dfcp)
				qlt_schedule_sess_for_deletion(tfcp);
5387

5388
			if (N2N_TOPO(vha->hw)) {
5389 5390
				fcport->flags &= ~FCF_FABRIC_DEVICE;
				fcport->keep_nport_handle = 1;
5391
				if (vha->flags.nvme_enabled) {
5392 5393
					fcport->fc4_type =
					    (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5394 5395 5396
					fcport->n2n_flag = 1;
				}
				fcport->fw_login_state = 0;
5397 5398

				schedule_delayed_work(&vha->scan.scan_work, 5);
5399 5400 5401
			} else {
				qla24xx_fcport_handle_login(vha, fcport);
			}
5402
		}
5403
	}
5404 5405 5406

	if (free_fcport) {
		qla2x00_free_fcport(fcport);
5407 5408
		if (pla) {
			list_del(&pla->list);
5409
			kmem_cache_free(qla_tgt_plogi_cachep, pla);
5410
		}
5411
	}
5412 5413
}

5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427
static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
{
	struct srb *sp = e->u.iosb.sp;
	int rval;

	rval = qla2x00_start_sp(sp);
	if (rval != QLA_SUCCESS) {
		ql_dbg(ql_dbg_disc, vha, 0x2043,
		    "%s: %s: Re-issue IOCB failed (%d).\n",
		    __func__, sp->name, rval);
		qla24xx_sp_unmap(vha, sp);
	}
}

5428
void
5429
qla2x00_do_work(struct scsi_qla_host *vha)
5430
{
5431 5432 5433
	struct qla_work_evt *e, *tmp;
	unsigned long flags;
	LIST_HEAD(work);
5434
	int rc;
5435

5436 5437 5438 5439 5440
	spin_lock_irqsave(&vha->work_lock, flags);
	list_splice_init(&vha->work_list, &work);
	spin_unlock_irqrestore(&vha->work_lock, flags);

	list_for_each_entry_safe(e, tmp, &work, list) {
5441
		rc = QLA_SUCCESS;
5442 5443
		switch (e->type) {
		case QLA_EVT_AEN:
5444
			fc_host_post_event(vha->host, fc_get_event_number(),
5445 5446
			    e->u.aen.code, e->u.aen.data);
			break;
5447 5448 5449
		case QLA_EVT_IDC_ACK:
			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
			break;
5450 5451 5452 5453 5454
		case QLA_EVT_ASYNC_LOGIN:
			qla2x00_async_login(vha, e->u.logio.fcport,
			    e->u.logio.data);
			break;
		case QLA_EVT_ASYNC_LOGOUT:
5455
			rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5456
			break;
5457 5458 5459 5460
		case QLA_EVT_ASYNC_ADISC:
			qla2x00_async_adisc(vha, e->u.logio.fcport,
			    e->u.logio.data);
			break;
5461 5462 5463
		case QLA_EVT_UEVENT:
			qla2x00_uevent_emit(vha, e->u.uevent.code);
			break;
5464 5465 5466
		case QLA_EVT_AENFX:
			qlafx00_process_aen(vha, e);
			break;
5467 5468 5469
		case QLA_EVT_GPNID:
			qla24xx_async_gpnid(vha, &e->u.gpnid.id);
			break;
5470 5471
		case QLA_EVT_UNMAP:
			qla24xx_sp_unmap(vha, e->u.iosb.sp);
5472
			break;
5473 5474 5475
		case QLA_EVT_RELOGIN:
			qla2x00_relogin(vha);
			break;
5476 5477 5478 5479 5480 5481 5482
		case QLA_EVT_NEW_SESS:
			qla24xx_create_new_sess(vha, e);
			break;
		case QLA_EVT_GPDB:
			qla24xx_async_gpdb(vha, e->u.fcport.fcport,
			    e->u.fcport.opt);
			break;
5483 5484 5485
		case QLA_EVT_PRLI:
			qla24xx_async_prli(vha, e->u.fcport.fcport);
			break;
5486 5487 5488 5489 5490 5491 5492 5493 5494
		case QLA_EVT_GPSC:
			qla24xx_async_gpsc(vha, e->u.fcport.fcport);
			break;
		case QLA_EVT_GNL:
			qla24xx_async_gnl(vha, e->u.fcport.fcport);
			break;
		case QLA_EVT_NACK:
			qla24xx_do_nack_work(vha, e);
			break;
5495
		case QLA_EVT_ASYNC_PRLO:
5496
			rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5497 5498 5499 5500 5501
			break;
		case QLA_EVT_ASYNC_PRLO_DONE:
			qla2x00_async_prlo_done(vha, e->u.logio.fcport,
			    e->u.logio.data);
			break;
5502
		case QLA_EVT_GPNFT:
5503 5504
			qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
			    e->u.gpnft.sp);
5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517
			break;
		case QLA_EVT_GPNFT_DONE:
			qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
			break;
		case QLA_EVT_GNNFT_DONE:
			qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
			break;
		case QLA_EVT_GNNID:
			qla24xx_async_gnnid(vha, e->u.fcport.fcport);
			break;
		case QLA_EVT_GFPNID:
			qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
			break;
5518 5519
		case QLA_EVT_SP_RETRY:
			qla_sp_retry(vha, e);
5520 5521 5522 5523
			break;
		case QLA_EVT_IIDMA:
			qla_do_iidma_work(vha, e->u.fcport.fcport);
			break;
5524 5525 5526 5527
		case QLA_EVT_ELS_PLOGI:
			qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
			    e->u.fcport.fcport, false);
			break;
5528
		case QLA_EVT_SA_REPLACE:
5529
			rc = qla24xx_issue_sa_replace_iocb(vha, e);
5530
			break;
5531
		}
5532 5533 5534 5535 5536 5537 5538 5539 5540

		if (rc == EAGAIN) {
			/* put 'work' at head of 'vha->work_list' */
			spin_lock_irqsave(&vha->work_lock, flags);
			list_splice(&work, &vha->work_list);
			spin_unlock_irqrestore(&vha->work_lock, flags);
			break;
		}
		list_del_init(&e->list);
5541 5542
		if (e->flags & QLA_EVT_FLAG_FREE)
			kfree(e);
5543 5544 5545

		/* For each work completed decrement vha ref count */
		QLA_VHA_MARK_NOT_BUSY(vha);
5546 5547
	}
}
5548

5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562
int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
{
	struct qla_work_evt *e;

	e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);

	if (!e) {
		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
		return QLA_FUNCTION_FAILED;
	}

	return qla2x00_post_work(vha, e);
}

5563 5564 5565 5566 5567 5568
/* Relogins all the fcports of a vport
 * Context: dpc thread
 */
void qla2x00_relogin(struct scsi_qla_host *vha)
{
	fc_port_t       *fcport;
5569
	int status, relogin_needed = 0;
5570
	struct event_arg ea;
5571 5572

	list_for_each_entry(fcport, &vha->vp_fcports, list) {
5573 5574 5575 5576
		/*
		 * If the port is not ONLINE then try to login
		 * to it if we haven't run out of retries.
		 */
5577
		if (atomic_read(&fcport->state) != FCS_ONLINE &&
5578 5579
		    fcport->login_retry) {
			if (fcport->scan_state != QLA_FCPORT_FOUND ||
5580
			    fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5581 5582
			    fcport->disc_state == DSC_LOGIN_COMPLETE)
				continue;
5583

5584 5585 5586 5587 5588 5589 5590
			if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
				fcport->disc_state == DSC_DELETE_PEND) {
				relogin_needed = 1;
			} else {
				if (vha->hw->current_topology != ISP_CFG_NL) {
					memset(&ea, 0, sizeof(ea));
					ea.fcport = fcport;
5591
					qla24xx_handle_relogin_event(vha, &ea);
5592 5593 5594 5595 5596
				} else if (vha->hw->current_topology ==
					 ISP_CFG_NL &&
					IS_QLA2XXX_MIDTYPE(vha->hw)) {
					(void)qla24xx_fcport_handle_login(vha,
									fcport);
5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621
				} else if (vha->hw->current_topology ==
				    ISP_CFG_NL) {
					fcport->login_retry--;
					status =
					    qla2x00_local_device_login(vha,
						fcport);
					if (status == QLA_SUCCESS) {
						fcport->old_loop_id =
						    fcport->loop_id;
						ql_dbg(ql_dbg_disc, vha, 0x2003,
						    "Port login OK: logged in ID 0x%x.\n",
						    fcport->loop_id);
						qla2x00_update_fcport
							(vha, fcport);
					} else if (status == 1) {
						set_bit(RELOGIN_NEEDED,
						    &vha->dpc_flags);
						/* retry the login again */
						ql_dbg(ql_dbg_disc, vha, 0x2007,
						    "Retrying %d login again loop_id 0x%x.\n",
						    fcport->login_retry,
						    fcport->loop_id);
					} else {
						fcport->login_retry = 0;
					}
5622

5623 5624 5625 5626
					if (fcport->login_retry == 0 &&
					    status != QLA_SUCCESS)
						qla2x00_clear_loop_id(fcport);
				}
5627 5628 5629 5630
			}
		}
		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
			break;
5631
	}
5632

5633 5634 5635
	if (relogin_needed)
		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);

5636 5637
	ql_dbg(ql_dbg_disc, vha, 0x400e,
	    "Relogin end.\n");
5638 5639
}

5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670
/* Schedule work on any of the dpc-workqueues */
void
qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
{
	struct qla_hw_data *ha = base_vha->hw;

	switch (work_code) {
	case MBA_IDC_AEN: /* 0x8200 */
		if (ha->dpc_lp_wq)
			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
		break;

	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
		if (!ha->flags.nic_core_reset_hdlr_active) {
			if (ha->dpc_hp_wq)
				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
		} else
			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
			    "NIC Core reset is already active. Skip "
			    "scheduling it again.\n");
		break;
	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
		if (ha->dpc_hp_wq)
			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
		break;
	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
		if (ha->dpc_hp_wq)
			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
		break;
	default:
		ql_log(ql_log_warn, base_vha, 0xb05f,
5671
		    "Unknown work-code=0x%x.\n", work_code);
5672 5673 5674 5675 5676 5677 5678 5679 5680 5681
	}

	return;
}

/* Work: Perform NIC Core Unrecoverable state handling */
void
qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
{
	struct qla_hw_data *ha =
5682
		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
	uint32_t dev_state = 0;

	qla83xx_idc_lock(base_vha, 0);
	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
	qla83xx_reset_ownership(base_vha);
	if (ha->flags.nic_core_reset_owner) {
		ha->flags.nic_core_reset_owner = 0;
		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
		    QLA8XXX_DEV_FAILED);
		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
	}
	qla83xx_idc_unlock(base_vha, 0);
}

/* Work: Execute IDC state handler */
void
qla83xx_idc_state_handler_work(struct work_struct *work)
{
	struct qla_hw_data *ha =
5704
		container_of(work, struct qla_hw_data, idc_state_handler);
5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
	uint32_t dev_state = 0;

	qla83xx_idc_lock(base_vha, 0);
	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
	if (dev_state == QLA8XXX_DEV_FAILED ||
			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
		qla83xx_idc_state_handler(base_vha);
	qla83xx_idc_unlock(base_vha, 0);
}

5716
static int
5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
{
	int rval = QLA_SUCCESS;
	unsigned long heart_beat_wait = jiffies + (1 * HZ);
	uint32_t heart_beat_counter1, heart_beat_counter2;

	do {
		if (time_after(jiffies, heart_beat_wait)) {
			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
			    "Nic Core f/w is not alive.\n");
			rval = QLA_FUNCTION_FAILED;
			break;
		}

		qla83xx_idc_lock(base_vha, 0);
		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
		    &heart_beat_counter1);
		qla83xx_idc_unlock(base_vha, 0);
		msleep(100);
		qla83xx_idc_lock(base_vha, 0);
		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
		    &heart_beat_counter2);
		qla83xx_idc_unlock(base_vha, 0);
	} while (heart_beat_counter1 == heart_beat_counter2);

	return rval;
}

/* Work: Perform NIC Core Reset handling */
void
qla83xx_nic_core_reset_work(struct work_struct *work)
{
	struct qla_hw_data *ha =
		container_of(work, struct qla_hw_data, nic_core_reset);
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
	uint32_t dev_state = 0;

5754 5755 5756 5757 5758 5759 5760
	if (IS_QLA2031(ha)) {
		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
			ql_log(ql_log_warn, base_vha, 0xb081,
			    "Failed to dump mctp\n");
		return;
	}

5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813
	if (!ha->flags.nic_core_reset_hdlr_active) {
		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
			qla83xx_idc_lock(base_vha, 0);
			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
			    &dev_state);
			qla83xx_idc_unlock(base_vha, 0);
			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
				    "Nic Core f/w is alive.\n");
				return;
			}
		}

		ha->flags.nic_core_reset_hdlr_active = 1;
		if (qla83xx_nic_core_reset(base_vha)) {
			/* NIC Core reset failed. */
			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
			    "NIC Core reset failed.\n");
		}
		ha->flags.nic_core_reset_hdlr_active = 0;
	}
}

/* Work: Handle 8200 IDC aens */
void
qla83xx_service_idc_aen(struct work_struct *work)
{
	struct qla_hw_data *ha =
		container_of(work, struct qla_hw_data, idc_aen);
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
	uint32_t dev_state, idc_control;

	qla83xx_idc_lock(base_vha, 0);
	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
	qla83xx_idc_unlock(base_vha, 0);
	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
			    "Application requested NIC Core Reset.\n");
			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
		    QLA_SUCCESS) {
			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
			    "Other protocol driver requested NIC Core Reset.\n");
			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
		}
	} else if (dev_state == QLA8XXX_DEV_FAILED ||
			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
	}
}

5814 5815 5816 5817
/*
 * Control the frequency of IDC lock retries
 */
#define QLA83XX_WAIT_LOGIC_MS	100
5818

5819
static int
5820 5821 5822 5823 5824 5825 5826
qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
{
	int rval;
	uint32_t data;
	uint32_t idc_lck_rcvry_stage_mask = 0x3;
	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
	struct qla_hw_data *ha = base_vha->hw;
5827

5828 5829
	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
	    "Trying force recovery of the IDC lock.\n");
5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880

	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
	if (rval)
		return rval;

	if ((data & idc_lck_rcvry_stage_mask) > 0) {
		return QLA_SUCCESS;
	} else {
		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
		    data);
		if (rval)
			return rval;

		msleep(200);

		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
		    &data);
		if (rval)
			return rval;

		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
			data &= (IDC_LOCK_RECOVERY_STAGE2 |
					~(idc_lck_rcvry_stage_mask));
			rval = qla83xx_wr_reg(base_vha,
			    QLA83XX_IDC_LOCK_RECOVERY, data);
			if (rval)
				return rval;

			/* Forcefully perform IDC UnLock */
			rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
			    &data);
			if (rval)
				return rval;
			/* Clear lock-id by setting 0xff */
			rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
			    0xff);
			if (rval)
				return rval;
			/* Clear lock-recovery by setting 0x0 */
			rval = qla83xx_wr_reg(base_vha,
			    QLA83XX_IDC_LOCK_RECOVERY, 0x0);
			if (rval)
				return rval;
		} else
			return QLA_SUCCESS;
	}

	return rval;
}

5881
static int
5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906
qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
{
	int rval = QLA_SUCCESS;
	uint32_t o_drv_lockid, n_drv_lockid;
	unsigned long lock_recovery_timeout;

	lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
retry_lockid:
	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
	if (rval)
		goto exit;

	/* MAX wait time before forcing IDC Lock recovery = 2 secs */
	if (time_after_eq(jiffies, lock_recovery_timeout)) {
		if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
			return QLA_SUCCESS;
		else
			return QLA_FUNCTION_FAILED;
	}

	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
	if (rval)
		goto exit;

	if (o_drv_lockid == n_drv_lockid) {
5907
		msleep(QLA83XX_WAIT_LOGIC_MS);
5908 5909 5910 5911 5912 5913 5914 5915
		goto retry_lockid;
	} else
		return QLA_SUCCESS;

exit:
	return rval;
}

5916 5917 5918
/*
 * Context: task, can sleep
 */
5919 5920 5921 5922
void
qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
{
	uint32_t data;
5923
	uint32_t lock_owner;
5924 5925
	struct qla_hw_data *ha = base_vha->hw;

5926 5927
	might_sleep();

5928 5929 5930 5931 5932 5933 5934 5935 5936
	/* IDC-lock implementation using driver-lock/lock-id remote registers */
retry_lock:
	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
	    == QLA_SUCCESS) {
		if (data) {
			/* Setting lock-id to our function-number */
			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
			    ha->portnum);
		} else {
5937 5938
			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
			    &lock_owner);
5939
			ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5940 5941
			    "Failed to acquire IDC lock, acquired by %d, "
			    "retrying...\n", lock_owner);
5942 5943 5944 5945

			/* Retry/Perform IDC-Lock recovery */
			if (qla83xx_idc_lock_recovery(base_vha)
			    == QLA_SUCCESS) {
5946
				msleep(QLA83XX_WAIT_LOGIC_MS);
5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957
				goto retry_lock;
			} else
				ql_log(ql_log_warn, base_vha, 0xb075,
				    "IDC Lock recovery FAILED.\n");
		}

	}

	return;
}

5958 5959 5960 5961 5962 5963
static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
	struct purex_entry_24xx *purex)
{
	char fwstr[16];
	u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
5964
	struct port_database_24xx *pdb;
5965 5966 5967 5968 5969 5970 5971 5972

	/* Domain Controller is always logged-out. */
	/* if RDP request is not from Domain Controller: */
	if (sid != 0xfffc01)
		return false;

	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);

5973 5974 5975 5976
	pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
	if (!pdb) {
		ql_dbg(ql_dbg_init, vha, 0x0181,
		    "%s: Failed allocate pdb\n", __func__);
5977 5978
	} else if (qla24xx_get_port_database(vha,
				le16_to_cpu(purex->nport_handle), pdb)) {
5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991
		ql_dbg(ql_dbg_init, vha, 0x0181,
		    "%s: Failed get pdb sid=%x\n", __func__, sid);
	} else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
	    pdb->current_login_state != PDS_PRLI_COMPLETE) {
		ql_dbg(ql_dbg_init, vha, 0x0181,
		    "%s: Port not logged in sid=%#x\n", __func__, sid);
	} else {
		/* RDP request is from logged in port */
		kfree(pdb);
		return false;
	}
	kfree(pdb);

5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003
	vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
	fwstr[strcspn(fwstr, " ")] = 0;
	/* if FW version allows RDP response length upto 2048 bytes: */
	if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
		return false;

	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);

	/* RDP response length is to be reduced to maximum 256 bytes */
	return true;
}

6004 6005 6006 6007 6008 6009 6010 6011 6012 6013
/*
 * Function Name: qla24xx_process_purex_iocb
 *
 * Description:
 * Prepare a RDP response and send to Fabric switch
 *
 * PARAMETERS:
 * vha:	SCSI qla host
 * purex: RDP request received by HBA
 */
6014 6015
void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
			       struct purex_item *item)
6016 6017
{
	struct qla_hw_data *ha = vha->hw;
6018 6019
	struct purex_entry_24xx *purex =
	    (struct purex_entry_24xx *)&item->iocb;
6020 6021 6022 6023 6024 6025 6026 6027 6028
	dma_addr_t rsp_els_dma;
	dma_addr_t rsp_payload_dma;
	dma_addr_t stat_dma;
	dma_addr_t sfp_dma;
	struct els_entry_24xx *rsp_els = NULL;
	struct rdp_rsp_payload *rsp_payload = NULL;
	struct link_statistics *stat = NULL;
	uint8_t *sfp = NULL;
	uint16_t sfp_flags = 0;
6029
	uint rsp_payload_length = sizeof(*rsp_payload);
6030
	int rval;
6031 6032 6033 6034 6035 6036 6037

	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
	    "%s: Enter\n", __func__);

	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
	    "-------- ELS REQ -------\n");
	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6038
	    purex, sizeof(*purex));
6039

6040 6041 6042 6043 6044 6045 6046 6047
	if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
		rsp_payload_length =
		    offsetof(typeof(*rsp_payload), optical_elmt_desc);
		ql_dbg(ql_dbg_init, vha, 0x0181,
		    "Reducing RSP payload length to %u bytes...\n",
		    rsp_payload_length);
	}

6048 6049
	rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
	    &rsp_els_dma, GFP_KERNEL);
6050 6051 6052
	if (!rsp_els) {
		ql_log(ql_log_warn, vha, 0x0183,
		    "Failed allocate dma buffer ELS RSP.\n");
6053
		goto dealloc;
6054
	}
6055 6056 6057

	rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
	    &rsp_payload_dma, GFP_KERNEL);
6058 6059 6060
	if (!rsp_payload) {
		ql_log(ql_log_warn, vha, 0x0184,
		    "Failed allocate dma buffer ELS RSP payload.\n");
6061
		goto dealloc;
6062
	}
6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076

	sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
	    &sfp_dma, GFP_KERNEL);

	stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
	    &stat_dma, GFP_KERNEL);

	/* Prepare Response IOCB */
	rsp_els->entry_type = ELS_IOCB_TYPE;
	rsp_els->entry_count = 1;
	rsp_els->sys_define = 0;
	rsp_els->entry_status = 0;
	rsp_els->handle = 0;
	rsp_els->nport_handle = purex->nport_handle;
6077
	rsp_els->tx_dsd_count = cpu_to_le16(1);
6078 6079 6080 6081 6082 6083
	rsp_els->vp_index = purex->vp_idx;
	rsp_els->sof_type = EST_SOFI3;
	rsp_els->rx_xchg_address = purex->rx_xchg_addr;
	rsp_els->rx_dsd_count = 0;
	rsp_els->opcode = purex->els_frame_payload[0];

6084 6085 6086
	rsp_els->d_id[0] = purex->s_id[0];
	rsp_els->d_id[1] = purex->s_id[1];
	rsp_els->d_id[2] = purex->s_id[2];
6087

6088
	rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6089
	rsp_els->rx_byte_count = 0;
6090
	rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6091 6092 6093 6094 6095 6096 6097 6098 6099

	put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
	rsp_els->tx_len = rsp_els->tx_byte_count;

	rsp_els->rx_address = 0;
	rsp_els->rx_len = 0;

	/* Prepare Response Payload */
	rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6100 6101
	rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
					   sizeof(rsp_payload->hdr));
6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116

	/* Link service Request Info Descriptor */
	rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
	rsp_payload->ls_req_info_desc.desc_len =
	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
	rsp_payload->ls_req_info_desc.req_payload_word_0 =
	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);

	/* Link service Request Info Descriptor 2 */
	rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
	rsp_payload->ls_req_info_desc2.desc_len =
	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
	rsp_payload->ls_req_info_desc2.req_payload_word_0 =
	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);

6117 6118 6119 6120 6121

	rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
	rsp_payload->sfp_diag_desc.desc_len =
		cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));

6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144
	if (sfp) {
		/* SFP Flags */
		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
		if (!rval) {
			/* SFP Flags bits 3-0: Port Tx Laser Type */
			if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
				sfp_flags |= BIT_0; /* short wave */
			else if (sfp[0] & BIT_1)
				sfp_flags |= BIT_1; /* long wave 1310nm */
			else if (sfp[1] & BIT_4)
				sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
		}

		/* SFP Type */
		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
		if (!rval) {
			sfp_flags |= BIT_4; /* optical */
			if (sfp[0] == 0x3)
				sfp_flags |= BIT_6; /* sfp+ */
		}

6145 6146
		rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);

6147 6148 6149
		/* SFP Diagnostics */
		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6150
		if (!rval) {
6151
			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164
			rsp_payload->sfp_diag_desc.temperature = trx[0];
			rsp_payload->sfp_diag_desc.vcc = trx[1];
			rsp_payload->sfp_diag_desc.tx_bias = trx[2];
			rsp_payload->sfp_diag_desc.tx_power = trx[3];
			rsp_payload->sfp_diag_desc.rx_power = trx[4];
		}
	}

	/* Port Speed Descriptor */
	rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
	rsp_payload->port_speed_desc.desc_len =
	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
	rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6165
	    qla25xx_fdmi_port_speed_capability(ha));
6166
	rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6167
	    qla25xx_fdmi_port_speed_currently(ha));
6168

6169 6170 6171 6172 6173
	/* Link Error Status Descriptor */
	rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
	rsp_payload->ls_err_desc.desc_len =
		cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));

6174 6175 6176 6177
	if (stat) {
		rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
		if (!rval) {
			rsp_payload->ls_err_desc.link_fail_cnt =
6178
			    cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6179
			rsp_payload->ls_err_desc.loss_sync_cnt =
6180
			    cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6181
			rsp_payload->ls_err_desc.loss_sig_cnt =
6182
			    cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6183
			rsp_payload->ls_err_desc.prim_seq_err_cnt =
6184
			    cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6185
			rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6186
			    cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6187
			rsp_payload->ls_err_desc.inval_crc_cnt =
6188
			    cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214
			rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
		}
	}

	/* Portname Descriptor */
	rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
	rsp_payload->port_name_diag_desc.desc_len =
	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
	memcpy(rsp_payload->port_name_diag_desc.WWNN,
	    vha->node_name,
	    sizeof(rsp_payload->port_name_diag_desc.WWNN));
	memcpy(rsp_payload->port_name_diag_desc.WWPN,
	    vha->port_name,
	    sizeof(rsp_payload->port_name_diag_desc.WWPN));

	/* F-Port Portname Descriptor */
	rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
	rsp_payload->port_name_direct_desc.desc_len =
	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
	memcpy(rsp_payload->port_name_direct_desc.WWNN,
	    vha->fabric_node_name,
	    sizeof(rsp_payload->port_name_direct_desc.WWNN));
	memcpy(rsp_payload->port_name_direct_desc.WWPN,
	    vha->fabric_port_name,
	    sizeof(rsp_payload->port_name_direct_desc.WWPN));

6215 6216 6217 6218 6219 6220 6221 6222
	/* Bufer Credit Descriptor */
	rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
	rsp_payload->buffer_credit_desc.desc_len =
		cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
	rsp_payload->buffer_credit_desc.fcport_b2b = 0;
	rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
	rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);

6223 6224 6225 6226
	if (ha->flags.plogi_template_valid) {
		uint32_t tmp =
		be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
		rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6227 6228
	}

6229 6230 6231
	if (rsp_payload_length < sizeof(*rsp_payload))
		goto send;

6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252
	/* Optical Element Descriptor, Temperature */
	rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
	rsp_payload->optical_elmt_desc[0].desc_len =
		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
	/* Optical Element Descriptor, Voltage */
	rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
	rsp_payload->optical_elmt_desc[1].desc_len =
		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
	/* Optical Element Descriptor, Tx Bias Current */
	rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
	rsp_payload->optical_elmt_desc[2].desc_len =
		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
	/* Optical Element Descriptor, Tx Power */
	rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
	rsp_payload->optical_elmt_desc[3].desc_len =
		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
	/* Optical Element Descriptor, Rx Power */
	rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
	rsp_payload->optical_elmt_desc[4].desc_len =
		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));

6253 6254 6255 6256
	if (sfp) {
		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
		if (!rval) {
6257
			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344

			/* Optical Element Descriptor, Temperature */
			rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
			rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
			rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
			rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
			rsp_payload->optical_elmt_desc[0].element_flags =
			    cpu_to_be32(1 << 28);

			/* Optical Element Descriptor, Voltage */
			rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
			rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
			rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
			rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
			rsp_payload->optical_elmt_desc[1].element_flags =
			    cpu_to_be32(2 << 28);

			/* Optical Element Descriptor, Tx Bias Current */
			rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
			rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
			rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
			rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
			rsp_payload->optical_elmt_desc[2].element_flags =
			    cpu_to_be32(3 << 28);

			/* Optical Element Descriptor, Tx Power */
			rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
			rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
			rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
			rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
			rsp_payload->optical_elmt_desc[3].element_flags =
			    cpu_to_be32(4 << 28);

			/* Optical Element Descriptor, Rx Power */
			rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
			rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
			rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
			rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
			rsp_payload->optical_elmt_desc[4].element_flags =
			    cpu_to_be32(5 << 28);
		}

		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
		if (!rval) {
			/* Temperature high/low alarm/warning */
			rsp_payload->optical_elmt_desc[0].element_flags |=
			    cpu_to_be32(
				(sfp[0] >> 7 & 1) << 3 |
				(sfp[0] >> 6 & 1) << 2 |
				(sfp[4] >> 7 & 1) << 1 |
				(sfp[4] >> 6 & 1) << 0);

			/* Voltage high/low alarm/warning */
			rsp_payload->optical_elmt_desc[1].element_flags |=
			    cpu_to_be32(
				(sfp[0] >> 5 & 1) << 3 |
				(sfp[0] >> 4 & 1) << 2 |
				(sfp[4] >> 5 & 1) << 1 |
				(sfp[4] >> 4 & 1) << 0);

			/* Tx Bias Current high/low alarm/warning */
			rsp_payload->optical_elmt_desc[2].element_flags |=
			    cpu_to_be32(
				(sfp[0] >> 3 & 1) << 3 |
				(sfp[0] >> 2 & 1) << 2 |
				(sfp[4] >> 3 & 1) << 1 |
				(sfp[4] >> 2 & 1) << 0);

			/* Tx Power high/low alarm/warning */
			rsp_payload->optical_elmt_desc[3].element_flags |=
			    cpu_to_be32(
				(sfp[0] >> 1 & 1) << 3 |
				(sfp[0] >> 0 & 1) << 2 |
				(sfp[4] >> 1 & 1) << 1 |
				(sfp[4] >> 0 & 1) << 0);

			/* Rx Power high/low alarm/warning */
			rsp_payload->optical_elmt_desc[4].element_flags |=
			    cpu_to_be32(
				(sfp[1] >> 7 & 1) << 3 |
				(sfp[1] >> 6 & 1) << 2 |
				(sfp[5] >> 7 & 1) << 1 |
				(sfp[5] >> 6 & 1) << 0);
		}
	}

6345 6346 6347 6348 6349
	/* Optical Product Data Descriptor */
	rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
	rsp_payload->optical_prod_desc.desc_len =
		cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));

6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382
	if (sfp) {
		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
		if (!rval) {
			memcpy(rsp_payload->optical_prod_desc.vendor_name,
			    sfp + 0,
			    sizeof(rsp_payload->optical_prod_desc.vendor_name));
			memcpy(rsp_payload->optical_prod_desc.part_number,
			    sfp + 20,
			    sizeof(rsp_payload->optical_prod_desc.part_number));
			memcpy(rsp_payload->optical_prod_desc.revision,
			    sfp + 36,
			    sizeof(rsp_payload->optical_prod_desc.revision));
			memcpy(rsp_payload->optical_prod_desc.serial_number,
			    sfp + 48,
			    sizeof(rsp_payload->optical_prod_desc.serial_number));
		}

		memset(sfp, 0, SFP_RTDI_LEN);
		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
		if (!rval) {
			memcpy(rsp_payload->optical_prod_desc.date,
			    sfp + 0,
			    sizeof(rsp_payload->optical_prod_desc.date));
		}
	}

send:
	ql_dbg(ql_dbg_init, vha, 0x0183,
	    "Sending ELS Response to RDP Request...\n");
	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
	    "-------- ELS RSP -------\n");
	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6383
	    rsp_els, sizeof(*rsp_els));
6384 6385 6386
	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
	    "-------- ELS RSP PAYLOAD -------\n");
	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6387
	    rsp_payload, rsp_payload_length);
6388 6389 6390

	rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);

6391
	if (rval) {
6392
		ql_log(ql_log_warn, vha, 0x0188,
6393 6394
		    "%s: iocb failed to execute -> %x\n", __func__, rval);
	} else if (rsp_els->comp_status) {
6395
		ql_log(ql_log_warn, vha, 0x0189,
6396 6397 6398
		    "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
		    __func__, rsp_els->comp_status,
		    rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415
	} else {
		ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
	}

dealloc:
	if (stat)
		dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
		    stat, stat_dma);
	if (sfp)
		dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
		    sfp, sfp_dma);
	if (rsp_payload)
		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
		    rsp_payload, rsp_payload_dma);
	if (rsp_els)
		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
		    rsp_els, rsp_els_dma);
6416
}
6417

6418 6419 6420 6421 6422 6423 6424 6425 6426
void
qla24xx_free_purex_item(struct purex_item *item)
{
	if (item == &item->vha->default_item)
		memset(&item->vha->default_item, 0, sizeof(struct purex_item));
	else
		kfree(item);
}

6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438
void qla24xx_process_purex_list(struct purex_list *list)
{
	struct list_head head = LIST_HEAD_INIT(head);
	struct purex_item *item, *next;
	ulong flags;

	spin_lock_irqsave(&list->lock, flags);
	list_splice_init(&list->head, &head);
	spin_unlock_irqrestore(&list->lock, flags);

	list_for_each_entry_safe(item, next, &head, list) {
		list_del(&item->list);
6439 6440
		item->process_item(item->vha, item);
		qla24xx_free_purex_item(item);
6441
	}
6442 6443
}

6444 6445 6446
/*
 * Context: task, can sleep
 */
6447 6448 6449
void
qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
{
6450 6451 6452 6453
#if 0
	uint16_t options = (requester_id << 15) | BIT_7;
#endif
	uint16_t retry;
6454 6455 6456
	uint32_t data;
	struct qla_hw_data *ha = base_vha->hw;

6457 6458
	might_sleep();

6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473
	/* IDC-unlock implementation using driver-unlock/lock-id
	 * remote registers
	 */
	retry = 0;
retry_unlock:
	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
	    == QLA_SUCCESS) {
		if (data == ha->portnum) {
			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
			/* Clearing lock-id by setting 0xff */
			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
		} else if (retry < 10) {
			/* SV: XXX: IDC unlock retrying needed here? */

			/* Retry for IDC-unlock */
6474
			msleep(QLA83XX_WAIT_LOGIC_MS);
6475 6476
			retry++;
			ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6477
			    "Failed to release IDC lock, retrying=%d\n", retry);
6478 6479 6480 6481
			goto retry_unlock;
		}
	} else if (retry < 10) {
		/* Retry for IDC-unlock */
6482
		msleep(QLA83XX_WAIT_LOGIC_MS);
6483 6484
		retry++;
		ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6485
		    "Failed to read drv-lockid, retrying=%d\n", retry);
6486 6487 6488 6489 6490
		goto retry_unlock;
	}

	return;

6491
#if 0
6492 6493 6494 6495 6496 6497
	/* XXX: IDC-unlock implementation using access-control mbx */
	retry = 0;
retry_unlock2:
	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
		if (retry < 10) {
			/* Retry for IDC-unlock */
6498
			msleep(QLA83XX_WAIT_LOGIC_MS);
6499 6500
			retry++;
			ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6501
			    "Failed to release IDC lock, retrying=%d\n", retry);
6502 6503 6504 6505 6506
			goto retry_unlock2;
		}
	}

	return;
6507
#endif
6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567
}

int
__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
{
	int rval = QLA_SUCCESS;
	struct qla_hw_data *ha = vha->hw;
	uint32_t drv_presence;

	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
	if (rval == QLA_SUCCESS) {
		drv_presence |= (1 << ha->portnum);
		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
		    drv_presence);
	}

	return rval;
}

int
qla83xx_set_drv_presence(scsi_qla_host_t *vha)
{
	int rval = QLA_SUCCESS;

	qla83xx_idc_lock(vha, 0);
	rval = __qla83xx_set_drv_presence(vha);
	qla83xx_idc_unlock(vha, 0);

	return rval;
}

int
__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
{
	int rval = QLA_SUCCESS;
	struct qla_hw_data *ha = vha->hw;
	uint32_t drv_presence;

	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
	if (rval == QLA_SUCCESS) {
		drv_presence &= ~(1 << ha->portnum);
		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
		    drv_presence);
	}

	return rval;
}

int
qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
{
	int rval = QLA_SUCCESS;

	qla83xx_idc_lock(vha, 0);
	rval = __qla83xx_clear_drv_presence(vha);
	qla83xx_idc_unlock(vha, 0);

	return rval;
}

6568
static void
6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579
qla83xx_need_reset_handler(scsi_qla_host_t *vha)
{
	struct qla_hw_data *ha = vha->hw;
	uint32_t drv_ack, drv_presence;
	unsigned long ack_timeout;

	/* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
	ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
	while (1) {
		qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
		qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6580
		if ((drv_ack & drv_presence) == drv_presence)
6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606
			break;

		if (time_after_eq(jiffies, ack_timeout)) {
			ql_log(ql_log_warn, vha, 0xb067,
			    "RESET ACK TIMEOUT! drv_presence=0x%x "
			    "drv_ack=0x%x\n", drv_presence, drv_ack);
			/*
			 * The function(s) which did not ack in time are forced
			 * to withdraw any further participation in the IDC
			 * reset.
			 */
			if (drv_ack != drv_presence)
				qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
				    drv_ack);
			break;
		}

		qla83xx_idc_unlock(vha, 0);
		msleep(1000);
		qla83xx_idc_lock(vha, 0);
	}

	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
	ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
}

6607
static int
6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740
qla83xx_device_bootstrap(scsi_qla_host_t *vha)
{
	int rval = QLA_SUCCESS;
	uint32_t idc_control;

	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
	ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");

	/* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
	__qla83xx_get_idc_control(vha, &idc_control);
	idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
	__qla83xx_set_idc_control(vha, 0);

	qla83xx_idc_unlock(vha, 0);
	rval = qla83xx_restart_nic_firmware(vha);
	qla83xx_idc_lock(vha, 0);

	if (rval != QLA_SUCCESS) {
		ql_log(ql_log_fatal, vha, 0xb06a,
		    "Failed to restart NIC f/w.\n");
		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
		ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
	} else {
		ql_dbg(ql_dbg_p3p, vha, 0xb06c,
		    "Success in restarting nic f/w.\n");
		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
		ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
	}

	return rval;
}

/* Assumes idc_lock always held on entry */
int
qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
{
	struct qla_hw_data *ha = base_vha->hw;
	int rval = QLA_SUCCESS;
	unsigned long dev_init_timeout;
	uint32_t dev_state;

	/* Wait for MAX-INIT-TIMEOUT for the device to go ready */
	dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);

	while (1) {

		if (time_after_eq(jiffies, dev_init_timeout)) {
			ql_log(ql_log_warn, base_vha, 0xb06e,
			    "Initialization TIMEOUT!\n");
			/* Init timeout. Disable further NIC Core
			 * communication.
			 */
			qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
				QLA8XXX_DEV_FAILED);
			ql_log(ql_log_info, base_vha, 0xb06f,
			    "HW State: FAILED.\n");
		}

		qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
		switch (dev_state) {
		case QLA8XXX_DEV_READY:
			if (ha->flags.nic_core_reset_owner)
				qla83xx_idc_audit(base_vha,
				    IDC_AUDIT_COMPLETION);
			ha->flags.nic_core_reset_owner = 0;
			ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
			    "Reset_owner reset by 0x%x.\n",
			    ha->portnum);
			goto exit;
		case QLA8XXX_DEV_COLD:
			if (ha->flags.nic_core_reset_owner)
				rval = qla83xx_device_bootstrap(base_vha);
			else {
			/* Wait for AEN to change device-state */
				qla83xx_idc_unlock(base_vha, 0);
				msleep(1000);
				qla83xx_idc_lock(base_vha, 0);
			}
			break;
		case QLA8XXX_DEV_INITIALIZING:
			/* Wait for AEN to change device-state */
			qla83xx_idc_unlock(base_vha, 0);
			msleep(1000);
			qla83xx_idc_lock(base_vha, 0);
			break;
		case QLA8XXX_DEV_NEED_RESET:
			if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
				qla83xx_need_reset_handler(base_vha);
			else {
				/* Wait for AEN to change device-state */
				qla83xx_idc_unlock(base_vha, 0);
				msleep(1000);
				qla83xx_idc_lock(base_vha, 0);
			}
			/* reset timeout value after need reset handler */
			dev_init_timeout = jiffies +
			    (ha->fcoe_dev_init_timeout * HZ);
			break;
		case QLA8XXX_DEV_NEED_QUIESCENT:
			/* XXX: DEBUG for now */
			qla83xx_idc_unlock(base_vha, 0);
			msleep(1000);
			qla83xx_idc_lock(base_vha, 0);
			break;
		case QLA8XXX_DEV_QUIESCENT:
			/* XXX: DEBUG for now */
			if (ha->flags.quiesce_owner)
				goto exit;

			qla83xx_idc_unlock(base_vha, 0);
			msleep(1000);
			qla83xx_idc_lock(base_vha, 0);
			dev_init_timeout = jiffies +
			    (ha->fcoe_dev_init_timeout * HZ);
			break;
		case QLA8XXX_DEV_FAILED:
			if (ha->flags.nic_core_reset_owner)
				qla83xx_idc_audit(base_vha,
				    IDC_AUDIT_COMPLETION);
			ha->flags.nic_core_reset_owner = 0;
			__qla83xx_clear_drv_presence(base_vha);
			qla83xx_idc_unlock(base_vha, 0);
			qla8xxx_dev_failed_handler(base_vha);
			rval = QLA_FUNCTION_FAILED;
			qla83xx_idc_lock(base_vha, 0);
			goto exit;
		case QLA8XXX_BAD_VALUE:
			qla83xx_idc_unlock(base_vha, 0);
			msleep(1000);
			qla83xx_idc_lock(base_vha, 0);
			break;
		default:
			ql_log(ql_log_warn, base_vha, 0xb071,
6741
			    "Unknown Device State: %x.\n", dev_state);
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			qla83xx_idc_unlock(base_vha, 0);
			qla8xxx_dev_failed_handler(base_vha);
			rval = QLA_FUNCTION_FAILED;
			qla83xx_idc_lock(base_vha, 0);
			goto exit;
		}
	}

exit:
	return rval;
}

6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764
void
qla2x00_disable_board_on_pci_error(struct work_struct *work)
{
	struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
	    board_disable);
	struct pci_dev *pdev = ha->pdev;
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);

	ql_log(ql_log_warn, base_vha, 0x015b,
	    "Disabling adapter.\n");

6765 6766 6767 6768 6769 6770 6771
	if (!atomic_read(&pdev->enable_cnt)) {
		ql_log(ql_log_info, base_vha, 0xfffc,
		    "PCI device disabled, no action req for PCI error=%lx\n",
		    base_vha->pci_flags);
		return;
	}

6772 6773 6774 6775 6776 6777
	/*
	 * if UNLOADING flag is already set, then continue unload,
	 * where it was set first.
	 */
	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
		return;
6778

6779
	qla2x00_wait_for_sess_deletion(base_vha);
6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808

	qla2x00_delete_all_vps(ha, base_vha);

	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);

	qla2x00_dfs_remove(base_vha);

	qla84xx_put_chip(base_vha);

	if (base_vha->timer_active)
		qla2x00_stop_timer(base_vha);

	base_vha->flags.online = 0;

	qla2x00_destroy_deferred_work(ha);

	/*
	 * Do not try to stop beacon blink as it will issue a mailbox
	 * command.
	 */
	qla2x00_free_sysfs_attr(base_vha, false);

	fc_remove_host(base_vha->host);

	scsi_remove_host(base_vha->host);

	base_vha->flags.init_done = 0;
	qla25xx_delete_queues(base_vha);
	qla2x00_free_fcports(base_vha);
6809
	qla2x00_free_irqs(base_vha);
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	qla2x00_mem_free(ha);
	qla82xx_md_free(base_vha);
	qla2x00_free_queues(ha);

	qla2x00_unmap_iobases(ha);

	pci_release_selected_regions(ha->pdev, ha->bars);
	pci_disable_pcie_error_reporting(pdev);
	pci_disable_device(pdev);

6820 6821 6822
	/*
	 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
	 */
6823 6824
}

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6825 6826 6827 6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840
/**************************************************************************
* qla2x00_do_dpc
*   This kernel thread is a task that is schedule by the interrupt handler
*   to perform the background processing for interrupts.
*
* Notes:
* This task always run in the context of a kernel thread.  It
* is kick-off by the driver's detect code and starts up
* up one per adapter. It immediately goes to sleep and waits for
* some fibre event.  When either the interrupt handler or
* the timer routine detects a event it will one of the task
* bits then wake us up.
**************************************************************************/
static int
qla2x00_do_dpc(void *data)
{
6841 6842
	scsi_qla_host_t *base_vha;
	struct qla_hw_data *ha;
6843 6844
	uint32_t online;
	struct qla_qpair *qpair;
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6845

6846 6847
	ha = (struct qla_hw_data *)data;
	base_vha = pci_get_drvdata(ha->pdev);
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6848

6849
	set_user_nice(current, MIN_NICE);
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6850

6851
	set_current_state(TASK_INTERRUPTIBLE);
6852
	while (!kthread_should_stop()) {
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		ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
		    "DPC handler sleeping.\n");
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6855

6856
		schedule();
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6857

6858 6859 6860
		if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
			qla_pci_set_eeh_busy(base_vha);

6861 6862
		if (!base_vha->flags.init_done || ha->flags.mbox_busy)
			goto end_loop;
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6863

6864
		if (ha->flags.eeh_busy) {
6865 6866
			ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
			    "eeh_busy=%d.\n", ha->flags.eeh_busy);
6867
			goto end_loop;
6868 6869
		}

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6870 6871
		ha->dpc_active = 1;

6872 6873 6874
		ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
		    "DPC handler waking up, dpc_flags=0x%lx.\n",
		    base_vha->dpc_flags);
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6875

6876 6877 6878
		if (test_bit(UNLOADING, &base_vha->dpc_flags))
			break;

6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905
		if (IS_P3P_TYPE(ha)) {
			if (IS_QLA8044(ha)) {
				if (test_and_clear_bit(ISP_UNRECOVERABLE,
					&base_vha->dpc_flags)) {
					qla8044_idc_lock(ha);
					qla8044_wr_direct(base_vha,
						QLA8044_CRB_DEV_STATE_INDEX,
						QLA8XXX_DEV_FAILED);
					qla8044_idc_unlock(ha);
					ql_log(ql_log_info, base_vha, 0x4004,
						"HW State: FAILED.\n");
					qla8044_device_state_handler(base_vha);
					continue;
				}

			} else {
				if (test_and_clear_bit(ISP_UNRECOVERABLE,
					&base_vha->dpc_flags)) {
					qla82xx_idc_lock(ha);
					qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
						QLA8XXX_DEV_FAILED);
					qla82xx_idc_unlock(ha);
					ql_log(ql_log_info, base_vha, 0x0151,
						"HW State: FAILED.\n");
					qla82xx_device_state_handler(base_vha);
					continue;
				}
6906 6907 6908 6909 6910
			}

			if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
				&base_vha->dpc_flags)) {

6911 6912
				ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
				    "FCoE context reset scheduled.\n");
6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925
				if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
					&base_vha->dpc_flags))) {
					if (qla82xx_fcoe_ctx_reset(base_vha)) {
						/* FCoE-ctx reset failed.
						 * Escalate to chip-reset
						 */
						set_bit(ISP_ABORT_NEEDED,
							&base_vha->dpc_flags);
					}
					clear_bit(ABORT_ISP_ACTIVE,
						&base_vha->dpc_flags);
				}

6926 6927
				ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
				    "FCoE context reset end.\n");
6928
			}
6929 6930 6931 6932 6933 6934 6935 6936
		} else if (IS_QLAFX00(ha)) {
			if (test_and_clear_bit(ISP_UNRECOVERABLE,
				&base_vha->dpc_flags)) {
				ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
				    "Firmware Reset Recovery\n");
				if (qlafx00_reset_initialize(base_vha)) {
					/* Failed. Abort isp later. */
					if (!test_bit(UNLOADING,
6937
					    &base_vha->dpc_flags)) {
6938 6939 6940 6941 6942
						set_bit(ISP_UNRECOVERABLE,
						    &base_vha->dpc_flags);
						ql_dbg(ql_dbg_dpc, base_vha,
						    0x4021,
						    "Reset Recovery Failed\n");
6943
					}
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				}
			}

			if (test_and_clear_bit(FX00_TARGET_SCAN,
				&base_vha->dpc_flags)) {
				ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
				    "ISPFx00 Target Scan scheduled\n");
				if (qlafx00_rescan_isp(base_vha)) {
					if (!test_bit(UNLOADING,
					    &base_vha->dpc_flags))
						set_bit(ISP_UNRECOVERABLE,
						    &base_vha->dpc_flags);
					ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
					    "ISPFx00 Target Scan Failed\n");
				}
				ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
				    "ISPFx00 Target Scan End\n");
			}
6962 6963 6964 6965 6966 6967 6968 6969
			if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
				&base_vha->dpc_flags)) {
				ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
				    "ISPFx00 Host Info resend scheduled\n");
				qlafx00_fx_disc(base_vha,
				    &base_vha->hw->mr.fcport,
				    FXDISC_REG_HOST_INFO);
			}
6970 6971
		}

6972
		if (test_and_clear_bit(DETECT_SFP_CHANGE,
6973 6974 6975 6976 6977 6978 6979 6980
		    &base_vha->dpc_flags)) {
			/* Semantic:
			 *  - NO-OP -- await next ISP-ABORT. Preferred method
			 *             to minimize disruptions that will occur
			 *             when a forced chip-reset occurs.
			 *  - Force -- ISP-ABORT scheduled.
			 */
			/* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
6981 6982
		}

6983 6984 6985
		if (test_and_clear_bit
		    (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
		    !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6986 6987
			bool do_reset = true;

6988
			switch (base_vha->qlini_mode) {
6989 6990 6991
			case QLA2XXX_INI_MODE_ENABLED:
				break;
			case QLA2XXX_INI_MODE_DISABLED:
6992 6993
				if (!qla_tgt_mode_enabled(base_vha) &&
				    !ha->flags.fw_started)
6994 6995 6996
					do_reset = false;
				break;
			case QLA2XXX_INI_MODE_DUAL:
6997 6998
				if (!qla_dual_mode_enabled(base_vha) &&
				    !ha->flags.fw_started)
6999 7000 7001 7002 7003
					do_reset = false;
				break;
			default:
				break;
			}
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7004

7005
			if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7006
			    &base_vha->dpc_flags))) {
7007
				base_vha->flags.online = 1;
7008 7009
				ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
				    "ISP abort scheduled.\n");
7010
				if (ha->isp_ops->abort_isp(base_vha)) {
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7011 7012
					/* failed. retry later */
					set_bit(ISP_ABORT_NEEDED,
7013
					    &base_vha->dpc_flags);
7014
				}
7015 7016
				clear_bit(ABORT_ISP_ACTIVE,
						&base_vha->dpc_flags);
7017 7018
				ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
				    "ISP abort end.\n");
7019
			}
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7020 7021
		}

7022 7023 7024 7025 7026 7027 7028
		if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
			if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
				qla24xx_process_purex_list
					(&base_vha->purex_list);
				clear_bit(PROCESS_PUREX_IOCB,
				    &base_vha->dpc_flags);
			}
7029 7030
		}

7031 7032
		if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
		    &base_vha->dpc_flags)) {
7033
			qla2x00_update_fcports(base_vha);
7034
		}
7035

7036 7037 7038
		if (IS_QLAFX00(ha))
			goto loop_resync_check;

7039
		if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7040 7041
			ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
			    "Quiescence mode scheduled.\n");
7042 7043 7044 7045 7046
			if (IS_P3P_TYPE(ha)) {
				if (IS_QLA82XX(ha))
					qla82xx_device_state_handler(base_vha);
				if (IS_QLA8044(ha))
					qla8044_device_state_handler(base_vha);
7047 7048 7049 7050
				clear_bit(ISP_QUIESCE_NEEDED,
				    &base_vha->dpc_flags);
				if (!ha->flags.quiesce_owner) {
					qla2x00_perform_loop_resync(base_vha);
7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061
					if (IS_QLA82XX(ha)) {
						qla82xx_idc_lock(ha);
						qla82xx_clear_qsnt_ready(
						    base_vha);
						qla82xx_idc_unlock(ha);
					} else if (IS_QLA8044(ha)) {
						qla8044_idc_lock(ha);
						qla8044_clear_qsnt_ready(
						    base_vha);
						qla8044_idc_unlock(ha);
					}
7062 7063 7064 7065 7066
				}
			} else {
				clear_bit(ISP_QUIESCE_NEEDED,
				    &base_vha->dpc_flags);
				qla2x00_quiesce_io(base_vha);
7067
			}
7068 7069
			ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
			    "Quiescence mode end.\n");
7070 7071
		}

7072
		if (test_and_clear_bit(RESET_MARKER_NEEDED,
7073
				&base_vha->dpc_flags) &&
7074
		    (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
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7075

7076 7077
			ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
			    "Reset marker scheduled.\n");
7078 7079
			qla2x00_rst_aen(base_vha);
			clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7080 7081
			ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
			    "Reset marker end.\n");
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7082 7083 7084
		}

		/* Retry each device up to login retry count */
7085
		if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7086 7087
		    !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
		    atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
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7088

7089 7090 7091 7092 7093
			if (!base_vha->relogin_jif ||
			    time_after_eq(jiffies, base_vha->relogin_jif)) {
				base_vha->relogin_jif = jiffies + HZ;
				clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);

7094
				ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7095
				    "Relogin scheduled.\n");
7096
				qla24xx_post_relogin_work(base_vha);
7097
			}
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7098
		}
7099
loop_resync_check:
7100
		if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
7101
		    &base_vha->dpc_flags)) {
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7102

7103 7104
			ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
			    "Loop resync scheduled.\n");
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7105 7106

			if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7107
			    &base_vha->dpc_flags))) {
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7108

7109
				qla2x00_loop_resync(base_vha);
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7110

7111 7112
				clear_bit(LOOP_RESYNC_ACTIVE,
						&base_vha->dpc_flags);
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7113 7114
			}

7115 7116
			ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
			    "Loop resync end.\n");
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7117 7118
		}

7119 7120 7121
		if (IS_QLAFX00(ha))
			goto intr_on_check;

7122 7123 7124 7125
		if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
		    atomic_read(&base_vha->loop_state) == LOOP_READY) {
			clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
			qla2xxx_flash_npiv_conf(base_vha);
7126 7127
		}

7128
intr_on_check:
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7129
		if (!ha->interrupts_on)
7130
			ha->isp_ops->enable_intrs(ha);
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7131

7132
		if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7133 7134 7135 7136
					&base_vha->dpc_flags)) {
			if (ha->beacon_blink_led == 1)
				ha->isp_ops->beacon_blink(base_vha);
		}
7137

7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153
		/* qpair online check */
		if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
		    &base_vha->dpc_flags)) {
			if (ha->flags.eeh_busy ||
			    ha->flags.pci_channel_io_perm_failure)
				online = 0;
			else
				online = 1;

			mutex_lock(&ha->mq_lock);
			list_for_each_entry(qpair, &base_vha->qp_list,
			    qp_list_elem)
			qpair->online = online;
			mutex_unlock(&ha->mq_lock);
		}

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		if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
				       &base_vha->dpc_flags)) {
			u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;

			if (threshold > ha->orig_fw_xcb_count)
				threshold = ha->orig_fw_xcb_count;

7161
			ql_log(ql_log_info, base_vha, 0xffffff,
7162 7163 7164
			       "SET ZIO Activity exchange threshold to %d.\n",
			       threshold);
			if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7165
				ql_log(ql_log_info, base_vha, 0xffffff,
7166 7167
				       "Unable to SET ZIO Activity exchange threshold to %d.\n",
				       threshold);
7168 7169 7170
			}
		}

7171 7172
		if (!IS_QLAFX00(ha))
			qla2x00_do_dpc_all_vps(base_vha);
7173

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		if (test_and_clear_bit(N2N_LINK_RESET,
			&base_vha->dpc_flags)) {
			qla2x00_lip_reset(base_vha);
		}

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7179
		ha->dpc_active = 0;
7180
end_loop:
7181
		set_current_state(TASK_INTERRUPTIBLE);
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7182
	} /* End of while(1) */
7183
	__set_current_state(TASK_RUNNING);
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7184

7185 7186
	ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
	    "DPC handler exiting.\n");
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	/*
	 * Make sure that nobody tries to wake us up again.
	 */
	ha->dpc_active = 0;

7193 7194 7195
	/* Cleanup any residual CTX SRBs. */
	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);

7196 7197 7198 7199
	return 0;
}

void
7200
qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7201
{
7202
	struct qla_hw_data *ha = vha->hw;
7203 7204
	struct task_struct *t = ha->dpc_thread;

7205
	if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7206
		wake_up_process(t);
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}

/*
*  qla2x00_rst_aen
*      Processes asynchronous reset.
*
* Input:
*      ha  = adapter block pointer.
*/
static void
7217
qla2x00_rst_aen(scsi_qla_host_t *vha)
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7218
{
7219 7220 7221
	if (vha->flags.online && !vha->flags.reset_active &&
	    !atomic_read(&vha->loop_down_timer) &&
	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
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7222
		do {
7223
			clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
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7224 7225 7226 7227 7228

			/*
			 * Issue marker command only when we are going to start
			 * the I/O.
			 */
7229 7230 7231
			vha->marker_needed = 1;
		} while (!atomic_read(&vha->loop_down_timer) &&
		    (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
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7232 7233 7234
	}
}

7235 7236 7237
static bool qla_do_heartbeat(struct scsi_qla_host *vha)
{
	struct qla_hw_data *ha = vha->hw;
7238 7239 7240
	u32 cmpl_cnt;
	u16 i;
	bool do_heartbeat = false;
7241

7242 7243 7244 7245 7246 7247 7248 7249
	/*
	 * Allow do_heartbeat only if we don’t have any active interrupts,
	 * but there are still IOs outstanding with firmware.
	 */
	cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
	if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
	    cmpl_cnt != ha->base_qpair->cmd_cnt) {
		do_heartbeat = true;
7250 7251
		goto skip;
	}
7252
	ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7253 7254

	for (i = 0; i < ha->max_qpairs; i++) {
7255 7256 7257 7258 7259 7260 7261 7262
		if (ha->queue_pair_map[i]) {
			cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
			if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
			    cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
				do_heartbeat = true;
				break;
			}
			ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7263 7264 7265 7266
		}
	}

skip:
7267
	return do_heartbeat;
7268 7269
}

7270
static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7271
{
7272 7273
	struct qla_hw_data *ha = vha->hw;

7274 7275 7276 7277 7278 7279
	if (vha->vp_idx)
		return;

	if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
		return;

7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290
	/*
	 * dpc thread cannot run if heartbeat is running at the same time.
	 * We also do not want to starve heartbeat task. Therefore, do
	 * heartbeat task at least once every 5 seconds.
	 */
	if (dpc_started &&
	    time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
		return;

	if (qla_do_heartbeat(vha)) {
		ha->last_heartbeat_run_jiffies = jiffies;
7291
		queue_work(ha->wq, &ha->heartbeat_work);
7292
	}
7293 7294
}

7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332
static void qla_wind_down_chip(scsi_qla_host_t *vha)
{
	struct qla_hw_data *ha = vha->hw;

	if (!ha->flags.eeh_busy)
		return;
	if (ha->pci_error_state)
		/* system is trying to recover */
		return;

	/*
	 * Current system is not handling PCIE error.  At this point, this is
	 * best effort to wind down the adapter.
	 */
	if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
	    !ha->flags.eeh_flush) {
		ql_log(ql_log_info, vha, 0x9009,
		    "PCI Error detected, attempting to reset hardware.\n");

		ha->isp_ops->reset_chip(vha);
		ha->isp_ops->disable_intrs(ha);

		ha->flags.eeh_flush = EEH_FLUSH_RDY;
		ha->eeh_jif = jiffies;

	} else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
	    time_after_eq(jiffies, ha->eeh_jif +  5 * HZ)) {
		pci_clear_master(ha->pdev);

		/* flush all command */
		qla2x00_abort_isp_cleanup(vha);
		ha->flags.eeh_flush = EEH_FLUSH_DONE;

		ql_log(ql_log_info, vha, 0x900a,
		    "PCI Error handling complete, all IOs aborted.\n");
	}
}

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7333 7334 7335 7336 7337 7338 7339 7340
/**************************************************************************
*   qla2x00_timer
*
* Description:
*   One second timer
*
* Context: Interrupt
***************************************************************************/
7341
void
7342
qla2x00_timer(struct timer_list *t)
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7343
{
7344
	scsi_qla_host_t *vha = from_timer(vha, t, timer);
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7345 7346 7347 7348
	unsigned long	cpu_flags = 0;
	int		start_dpc = 0;
	int		index;
	srb_t		*sp;
7349
	uint16_t        w;
7350
	struct qla_hw_data *ha = vha->hw;
7351
	struct req_que *req;
7352 7353
	unsigned long flags;
	fc_port_t *fcport = NULL;
7354

7355
	if (ha->flags.eeh_busy) {
7356 7357
		qla_wind_down_chip(vha);

7358 7359 7360
		ql_dbg(ql_dbg_timer, vha, 0x6000,
		    "EEH = %d, restarting timer.\n",
		    ha->flags.eeh_busy);
7361 7362 7363 7364
		qla2x00_restart_timer(vha, WATCH_INTERVAL);
		return;
	}

7365 7366 7367 7368 7369
	/*
	 * Hardware read to raise pending EEH errors during mailbox waits. If
	 * the read returns -1 then disable the board.
	 */
	if (!pci_channel_offline(ha->pdev)) {
7370
		pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7371
		qla2x00_check_reg16_for_disconnect(vha, w);
7372
	}
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7373

7374
	/* Make sure qla82xx_watchdog is run only for physical port */
7375
	if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7376 7377
		if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
			start_dpc++;
7378 7379 7380 7381
		if (IS_QLA82XX(ha))
			qla82xx_watchdog(vha);
		else if (IS_QLA8044(ha))
			qla8044_watchdog(vha);
7382 7383
	}

7384 7385 7386
	if (!vha->vp_idx && IS_QLAFX00(ha))
		qlafx00_timer_routine(vha);

7387 7388 7389 7390 7391 7392 7393 7394 7395 7396
	if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
		vha->link_down_time++;

	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
	list_for_each_entry(fcport, &vha->vp_fcports, list) {
		if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
			fcport->tgt_link_down_time++;
	}
	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);

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7397
	/* Loop down handler. */
7398
	if (atomic_read(&vha->loop_down_timer) > 0 &&
7399 7400
	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
	    !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7401
		&& vha->flags.online) {
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7402

7403 7404
		if (atomic_read(&vha->loop_down_timer) ==
		    vha->loop_down_abort_time) {
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7405

7406 7407
			ql_log(ql_log_info, vha, 0x6008,
			    "Loop down - aborting the queues before time expires.\n");
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7408

7409 7410
			if (!IS_QLA2100(ha) && vha->link_down_timeout)
				atomic_set(&vha->loop_state, LOOP_DEAD);
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7411

7412 7413 7414 7415
			/*
			 * Schedule an ISP abort to return any FCP2-device
			 * commands.
			 */
7416
			/* NPIV - scan physical port only */
7417
			if (!vha->vp_idx) {
7418 7419
				spin_lock_irqsave(&ha->hardware_lock,
				    cpu_flags);
7420
				req = ha->req_q_map[0];
7421
				for (index = 1;
7422
				    index < req->num_outstanding_cmds;
7423 7424 7425
				    index++) {
					fc_port_t *sfcp;

7426
					sp = req->outstanding_cmds[index];
7427 7428
					if (!sp)
						continue;
7429 7430
					if (sp->cmd_type != TYPE_SRB)
						continue;
7431
					if (sp->type != SRB_SCSI_CMD)
7432
						continue;
7433
					sfcp = sp->fcport;
7434
					if (!(sfcp->flags & FCF_FCP2_DEVICE))
7435
						continue;
7436

7437 7438 7439 7440 7441
					if (IS_QLA82XX(ha))
						set_bit(FCOE_CTX_RESET_NEEDED,
							&vha->dpc_flags);
					else
						set_bit(ISP_ABORT_NEEDED,
7442
							&vha->dpc_flags);
7443 7444 7445
					break;
				}
				spin_unlock_irqrestore(&ha->hardware_lock,
7446
								cpu_flags);
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7447 7448 7449 7450 7451
			}
			start_dpc++;
		}

		/* if the loop has been down for 4 minutes, reinit adapter */
7452
		if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7453
			if (!(vha->device_flags & DFLG_NO_CABLE)) {
7454
				ql_log(ql_log_warn, vha, 0x6009,
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7455 7456
				    "Loop down - aborting ISP.\n");

7457 7458 7459 7460 7461 7462
				if (IS_QLA82XX(ha))
					set_bit(FCOE_CTX_RESET_NEEDED,
						&vha->dpc_flags);
				else
					set_bit(ISP_ABORT_NEEDED,
						&vha->dpc_flags);
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7463 7464
			}
		}
7465 7466 7467
		ql_dbg(ql_dbg_timer, vha, 0x600a,
		    "Loop down - seconds remaining %d.\n",
		    atomic_read(&vha->loop_down_timer));
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7468
	}
7469 7470
	/* Check if beacon LED needs to be blinked for physical host only */
	if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7471
		/* There is no beacon_blink function for ISP82xx */
7472
		if (!IS_P3P_TYPE(ha)) {
7473 7474 7475
			set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
			start_dpc++;
		}
7476 7477
	}

7478 7479 7480 7481
	/* check if edif running */
	if (vha->hw->flags.edif_enabled)
		qla_edif_timer(vha);

7482
	/* Process any deferred work. */
7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493
	if (!list_empty(&vha->work_list)) {
		unsigned long flags;
		bool q = false;

		spin_lock_irqsave(&vha->work_lock, flags);
		if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
			q = true;
		spin_unlock_irqrestore(&vha->work_lock, flags);
		if (q)
			queue_work(vha->hw->wq, &vha->iocb_work);
	}
7494

7495 7496 7497 7498
	/*
	 * FC-NVME
	 * see if the active AEN count has changed from what was last reported.
	 */
7499
	index = atomic_read(&ha->nvme_active_aen_cnt);
7500
	if (!vha->vp_idx &&
7501
	    (index != ha->nvme_last_rptd_aen) &&
7502 7503
	    ha->zio_mode == QLA_ZIO_MODE_6 &&
	    !ha->flags.host_shutting_down) {
7504
		ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7505
		ql_log(ql_log_info, vha, 0x3002,
7506 7507
		    "nvme: Sched: Set ZIO exchange threshold to %d.\n",
		    ha->nvme_last_rptd_aen);
7508
		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7509 7510 7511 7512
		start_dpc++;
	}

	if (!vha->vp_idx &&
7513 7514
	    atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
	    IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7515 7516 7517 7518
		ql_log(ql_log_info, vha, 0x3002,
		    "Sched: Set ZIO exchange threshold to %d.\n",
		    ha->last_zio_threshold);
		ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7519 7520
		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
		start_dpc++;
7521 7522
	}

7523 7524
	/* borrowing w to signify dpc will run */
	w = 0;
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7525
	/* Schedule the DPC routine if needed */
7526 7527 7528
	if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
	    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
	    test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
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7529
	    start_dpc ||
7530 7531
	    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
	    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7532 7533
	    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
	    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7534
	    test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7535 7536
	    test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
	    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548
		ql_dbg(ql_dbg_timer, vha, 0x600b,
		    "isp_abort_needed=%d loop_resync_needed=%d "
		    "fcport_update_needed=%d start_dpc=%d "
		    "reset_marker_needed=%d",
		    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
		    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
		    test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
		    start_dpc,
		    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
		ql_dbg(ql_dbg_timer, vha, 0x600c,
		    "beacon_blink_needed=%d isp_unrecoverable=%d "
		    "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7549
		    "relogin_needed=%d, Process_purex_iocb=%d.\n",
7550 7551 7552 7553
		    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
		    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
		    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
		    test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7554 7555
		    test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
		    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7556
		qla2xxx_wake_dpc(vha);
7557
		w = 1;
7558
	}
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7559

7560
	qla_heart_beat(vha, w);
7561

7562
	qla2x00_restart_timer(vha, WATCH_INTERVAL);
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7563 7564
}

7565 7566 7567 7568 7569 7570
/* Firmware interface routines. */

#define FW_ISP21XX	0
#define FW_ISP22XX	1
#define FW_ISP2300	2
#define FW_ISP2322	3
7571
#define FW_ISP24XX	4
7572
#define FW_ISP25XX	5
7573
#define FW_ISP81XX	6
7574
#define FW_ISP82XX	7
7575 7576
#define FW_ISP2031	8
#define FW_ISP8031	9
7577
#define FW_ISP27XX	10
7578
#define FW_ISP28XX	11
7579

7580 7581 7582 7583 7584
#define FW_FILE_ISP21XX	"ql2100_fw.bin"
#define FW_FILE_ISP22XX	"ql2200_fw.bin"
#define FW_FILE_ISP2300	"ql2300_fw.bin"
#define FW_FILE_ISP2322	"ql2322_fw.bin"
#define FW_FILE_ISP24XX	"ql2400_fw.bin"
7585
#define FW_FILE_ISP25XX	"ql2500_fw.bin"
7586
#define FW_FILE_ISP81XX	"ql8100_fw.bin"
7587
#define FW_FILE_ISP82XX	"ql8200_fw.bin"
7588 7589
#define FW_FILE_ISP2031	"ql2600_fw.bin"
#define FW_FILE_ISP8031	"ql8300_fw.bin"
7590
#define FW_FILE_ISP27XX	"ql2700_fw.bin"
7591
#define FW_FILE_ISP28XX	"ql2800_fw.bin"
7592

7593

7594
static DEFINE_MUTEX(qla_fw_lock);
7595

7596
static struct fw_blob qla_fw_blobs[] = {
7597 7598 7599 7600 7601
	{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
	{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
	{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
	{ .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
	{ .name = FW_FILE_ISP24XX, },
7602
	{ .name = FW_FILE_ISP25XX, },
7603
	{ .name = FW_FILE_ISP81XX, },
7604
	{ .name = FW_FILE_ISP82XX, },
7605 7606
	{ .name = FW_FILE_ISP2031, },
	{ .name = FW_FILE_ISP8031, },
7607
	{ .name = FW_FILE_ISP27XX, },
7608 7609
	{ .name = FW_FILE_ISP28XX, },
	{ .name = NULL, },
7610 7611 7612
};

struct fw_blob *
7613
qla2x00_request_firmware(scsi_qla_host_t *vha)
7614
{
7615
	struct qla_hw_data *ha = vha->hw;
7616 7617 7618 7619 7620 7621
	struct fw_blob *blob;

	if (IS_QLA2100(ha)) {
		blob = &qla_fw_blobs[FW_ISP21XX];
	} else if (IS_QLA2200(ha)) {
		blob = &qla_fw_blobs[FW_ISP22XX];
7622
	} else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7623
		blob = &qla_fw_blobs[FW_ISP2300];
7624
	} else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7625
		blob = &qla_fw_blobs[FW_ISP2322];
7626
	} else if (IS_QLA24XX_TYPE(ha)) {
7627
		blob = &qla_fw_blobs[FW_ISP24XX];
7628 7629
	} else if (IS_QLA25XX(ha)) {
		blob = &qla_fw_blobs[FW_ISP25XX];
7630 7631
	} else if (IS_QLA81XX(ha)) {
		blob = &qla_fw_blobs[FW_ISP81XX];
7632 7633
	} else if (IS_QLA82XX(ha)) {
		blob = &qla_fw_blobs[FW_ISP82XX];
7634 7635 7636 7637
	} else if (IS_QLA2031(ha)) {
		blob = &qla_fw_blobs[FW_ISP2031];
	} else if (IS_QLA8031(ha)) {
		blob = &qla_fw_blobs[FW_ISP8031];
7638 7639
	} else if (IS_QLA27XX(ha)) {
		blob = &qla_fw_blobs[FW_ISP27XX];
7640 7641
	} else if (IS_QLA28XX(ha)) {
		blob = &qla_fw_blobs[FW_ISP28XX];
7642 7643
	} else {
		return NULL;
7644 7645
	}

7646 7647 7648
	if (!blob->name)
		return NULL;

7649
	mutex_lock(&qla_fw_lock);
7650 7651 7652 7653
	if (blob->fw)
		goto out;

	if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7654 7655
		ql_log(ql_log_warn, vha, 0x0063,
		    "Failed to load firmware image (%s).\n", blob->name);
7656 7657 7658 7659 7660
		blob->fw = NULL;
		blob = NULL;
	}

out:
7661
	mutex_unlock(&qla_fw_lock);
7662 7663 7664 7665 7666 7667
	return blob;
}

static void
qla2x00_release_firmware(void)
{
7668
	struct fw_blob *blob;
7669

7670
	mutex_lock(&qla_fw_lock);
7671 7672
	for (blob = qla_fw_blobs; blob->name; blob++)
		release_firmware(blob->fw);
7673
	mutex_unlock(&qla_fw_lock);
7674 7675
}

7676 7677 7678 7679 7680
static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
{
	struct qla_hw_data *ha = vha->hw;
	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
	struct qla_qpair *qpair = NULL;
7681
	struct scsi_qla_host *vp, *tvp;
7682 7683 7684 7685
	fc_port_t *fcport;
	int i;
	unsigned long flags;

7686 7687
	ql_dbg(ql_dbg_aer, vha, 0x9000,
	       "%s\n", __func__);
7688 7689 7690 7691 7692 7693 7694 7695 7696
	ha->chip_reset++;

	ha->base_qpair->chip_reset = ha->chip_reset;
	for (i = 0; i < ha->max_qpairs; i++) {
		if (ha->queue_pair_map[i])
			ha->queue_pair_map[i]->chip_reset =
			    ha->base_qpair->chip_reset;
	}

7697 7698 7699 7700
	/*
	 * purge mailbox might take a while. Slot Reset/chip reset
	 * will take care of the purge
	 */
7701 7702

	mutex_lock(&ha->mq_lock);
7703
	ha->base_qpair->online = 0;
7704 7705
	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
		qpair->online = 0;
7706
	wmb();
7707 7708
	mutex_unlock(&ha->mq_lock);

7709
	qla2x00_mark_all_devices_lost(vha);
7710 7711

	spin_lock_irqsave(&ha->vport_slock, flags);
7712
	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7713 7714
		atomic_inc(&vp->vref_count);
		spin_unlock_irqrestore(&ha->vport_slock, flags);
7715
		qla2x00_mark_all_devices_lost(vp);
7716 7717 7718 7719 7720 7721 7722 7723 7724 7725
		spin_lock_irqsave(&ha->vport_slock, flags);
		atomic_dec(&vp->vref_count);
	}
	spin_unlock_irqrestore(&ha->vport_slock, flags);

	/* Clear all async request states across all VPs. */
	list_for_each_entry(fcport, &vha->vp_fcports, list)
		fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);

	spin_lock_irqsave(&ha->vport_slock, flags);
7726
	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737
		atomic_inc(&vp->vref_count);
		spin_unlock_irqrestore(&ha->vport_slock, flags);
		list_for_each_entry(fcport, &vp->vp_fcports, list)
			fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
		spin_lock_irqsave(&ha->vport_slock, flags);
		atomic_dec(&vp->vref_count);
	}
	spin_unlock_irqrestore(&ha->vport_slock, flags);
}


7738 7739 7740
static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
{
7741 7742
	scsi_qla_host_t *vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = vha->hw;
7743
	pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7744

7745 7746 7747
	ql_log(ql_log_warn, vha, 0x9000,
	       "PCI error detected, state %x.\n", state);
	ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7748

7749 7750 7751
	if (!atomic_read(&pdev->enable_cnt)) {
		ql_log(ql_log_info, vha, 0xffff,
			"PCI device is disabled,state %x\n", state);
7752 7753
		ret = PCI_ERS_RESULT_NEED_RESET;
		goto out;
7754 7755
	}

7756 7757
	switch (state) {
	case pci_channel_io_normal:
7758
		qla_pci_set_eeh_busy(vha);
7759
		if (ql2xmqsupport || ql2xnvmeenable) {
7760 7761 7762
			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
			qla2xxx_wake_dpc(vha);
		}
7763 7764
		ret = PCI_ERS_RESULT_CAN_RECOVER;
		break;
7765
	case pci_channel_io_frozen:
7766 7767 7768
		qla_pci_set_eeh_busy(vha);
		ret = PCI_ERS_RESULT_NEED_RESET;
		break;
7769
	case pci_channel_io_perm_failure:
7770 7771
		ha->flags.pci_channel_io_perm_failure = 1;
		qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7772
		if (ql2xmqsupport || ql2xnvmeenable) {
7773 7774 7775
			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
			qla2xxx_wake_dpc(vha);
		}
7776
		ret = PCI_ERS_RESULT_DISCONNECT;
7777
	}
7778 7779 7780 7781
out:
	ql_dbg(ql_dbg_aer, vha, 0x600d,
	       "PCI error detected returning [%x].\n", ret);
	return ret;
7782 7783 7784 7785 7786 7787 7788 7789
}

static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
{
	int risc_paused = 0;
	uint32_t stat;
	unsigned long flags;
7790 7791
	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = base_vha->hw;
7792 7793 7794
	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;

7795 7796 7797 7798
	ql_log(ql_log_warn, base_vha, 0x9000,
	       "mmio enabled\n");

	ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7799

7800 7801 7802
	if (IS_QLA82XX(ha))
		return PCI_ERS_RESULT_RECOVERED;

7803 7804 7805 7806 7807 7808
	if (qla2x00_isp_reg_stat(ha)) {
		ql_log(ql_log_info, base_vha, 0x803f,
		    "During mmio enabled, PCI/Register disconnect still detected.\n");
		goto out;
	}

7809 7810
	spin_lock_irqsave(&ha->hardware_lock, flags);
	if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7811
		stat = rd_reg_word(&reg->hccr);
7812 7813 7814
		if (stat & HCCR_RISC_PAUSE)
			risc_paused = 1;
	} else if (IS_QLA23XX(ha)) {
7815
		stat = rd_reg_dword(&reg->u.isp2300.host_status);
7816 7817 7818
		if (stat & HSR_RISC_PAUSED)
			risc_paused = 1;
	} else if (IS_FWI2_CAPABLE(ha)) {
7819
		stat = rd_reg_dword(&reg24->host_status);
7820 7821 7822 7823 7824 7825
		if (stat & HSRX_RISC_PAUSED)
			risc_paused = 1;
	}
	spin_unlock_irqrestore(&ha->hardware_lock, flags);

	if (risc_paused) {
7826 7827
		ql_log(ql_log_info, base_vha, 0x9003,
		    "RISC paused -- mmio_enabled, Dumping firmware.\n");
7828
		qla2xxx_dump_fw(base_vha);
7829
	}
7830
out:
7831 7832 7833 7834
	/* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
	       "mmio enabled returning.\n");
	return PCI_ERS_RESULT_NEED_RESET;
7835 7836 7837 7838 7839 7840
}

static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev *pdev)
{
	pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7841 7842
	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = base_vha->hw;
7843 7844
	int rc;
	struct qla_qpair *qpair = NULL;
7845

7846 7847
	ql_log(ql_log_warn, base_vha, 0x9004,
	       "Slot Reset.\n");
7848

7849
	ha->pci_error_state = QLA_PCI_SLOT_RESET;
7850 7851 7852 7853 7854 7855 7856 7857
	/* Workaround: qla2xxx driver which access hardware earlier
	 * needs error state to be pci_channel_io_online.
	 * Otherwise mailbox command timesout.
	 */
	pdev->error_state = pci_channel_io_normal;

	pci_restore_state(pdev);

7858 7859 7860 7861 7862
	/* pci_restore_state() clears the saved_state flag of the device
	 * save restored state which resets saved_state flag
	 */
	pci_save_state(pdev);

7863 7864 7865 7866
	if (ha->mem_only)
		rc = pci_enable_device_mem(pdev);
	else
		rc = pci_enable_device(pdev);
7867

7868
	if (rc) {
7869
		ql_log(ql_log_warn, base_vha, 0x9005,
7870
		    "Can't re-enable PCI device after reset.\n");
7871
		goto exit_slot_reset;
7872 7873
	}

7874

7875
	if (ha->isp_ops->pci_config(base_vha))
7876 7877
		goto exit_slot_reset;

7878 7879 7880 7881
	mutex_lock(&ha->mq_lock);
	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
		qpair->online = 1;
	mutex_unlock(&ha->mq_lock);
7882

7883
	ha->flags.eeh_busy = 0;
7884
	base_vha->flags.online = 1;
7885
	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7886
	ha->isp_ops->abort_isp(base_vha);
7887
	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7888

7889 7890 7891 7892 7893 7894 7895 7896
	if (qla2x00_isp_reg_stat(ha)) {
		ha->flags.eeh_busy = 1;
		qla_pci_error_cleanup(base_vha);
		ql_log(ql_log_warn, base_vha, 0x9005,
		       "Device unable to recover from PCI error.\n");
	} else {
		ret =  PCI_ERS_RESULT_RECOVERED;
	}
7897

7898
exit_slot_reset:
7899
	ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7900
	    "Slot Reset returning %x.\n", ret);
7901

7902 7903 7904 7905 7906 7907
	return ret;
}

static void
qla2xxx_pci_resume(struct pci_dev *pdev)
{
7908 7909
	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = base_vha->hw;
7910 7911
	int ret;

7912 7913
	ql_log(ql_log_warn, base_vha, 0x900f,
	       "Pci Resume.\n");
7914

7915

7916
	ret = qla2x00_wait_for_hba_online(base_vha);
7917
	if (ret != QLA_SUCCESS) {
7918 7919
		ql_log(ql_log_fatal, base_vha, 0x9002,
		    "The device failed to resume I/O from slot/link_reset.\n");
7920
	}
7921 7922 7923 7924 7925 7926 7927 7928 7929 7930 7931 7932 7933 7934 7935 7936 7937
	ha->pci_error_state = QLA_PCI_RESUME;
	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
	       "Pci Resume returning.\n");
}

void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
{
	struct qla_hw_data *ha = vha->hw;
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
	bool do_cleanup = false;
	unsigned long flags;

	if (ha->flags.eeh_busy)
		return;

	spin_lock_irqsave(&base_vha->work_lock, flags);
	if (!ha->flags.eeh_busy) {
7938 7939 7940
		ha->eeh_jif = jiffies;
		ha->flags.eeh_flush = 0;

7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955 7956 7957 7958 7959 7960 7961 7962 7963
		ha->flags.eeh_busy = 1;
		do_cleanup = true;
	}
	spin_unlock_irqrestore(&base_vha->work_lock, flags);

	if (do_cleanup)
		qla_pci_error_cleanup(base_vha);
}

/*
 * this routine will schedule a task to pause IO from interrupt context
 * if caller sees a PCIE error event (register read = 0xf's)
 */
void qla_schedule_eeh_work(struct scsi_qla_host *vha)
{
	struct qla_hw_data *ha = vha->hw;
	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);

	if (ha->flags.eeh_busy)
		return;

	set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
	qla2xxx_wake_dpc(base_vha);
7964 7965
}

7966 7967 7968 7969 7970 7971 7972 7973 7974 7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016
static void
qla_pci_reset_prepare(struct pci_dev *pdev)
{
	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = base_vha->hw;
	struct qla_qpair *qpair;

	ql_log(ql_log_warn, base_vha, 0xffff,
	    "%s.\n", __func__);

	/*
	 * PCI FLR/function reset is about to reset the
	 * slot. Stop the chip to stop all DMA access.
	 * It is assumed that pci_reset_done will be called
	 * after FLR to resume Chip operation.
	 */
	ha->flags.eeh_busy = 1;
	mutex_lock(&ha->mq_lock);
	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
		qpair->online = 0;
	mutex_unlock(&ha->mq_lock);

	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
	qla2x00_abort_isp_cleanup(base_vha);
	qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
}

static void
qla_pci_reset_done(struct pci_dev *pdev)
{
	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
	struct qla_hw_data *ha = base_vha->hw;
	struct qla_qpair *qpair;

	ql_log(ql_log_warn, base_vha, 0xffff,
	    "%s.\n", __func__);

	/*
	 * FLR just completed by PCI layer. Resume adapter
	 */
	ha->flags.eeh_busy = 0;
	mutex_lock(&ha->mq_lock);
	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
		qpair->online = 1;
	mutex_unlock(&ha->mq_lock);

	base_vha->flags.online = 1;
	ha->isp_ops->abort_isp(base_vha);
	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
}

8017 8018
static int qla2xxx_map_queues(struct Scsi_Host *shost)
{
8019
	int rc;
8020
	scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8021
	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8022

8023
	if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8024
		rc = blk_mq_map_queues(qmap);
8025
	else
8026
		rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
8027
	return rc;
8028 8029
}

8030 8031 8032 8033 8034 8035 8036
struct scsi_host_template qla2xxx_driver_template = {
	.module			= THIS_MODULE,
	.name			= QLA2XXX_DRIVER_NAME,
	.queuecommand		= qla2xxx_queuecommand,

	.eh_timed_out		= fc_eh_timed_out,
	.eh_abort_handler	= qla2xxx_eh_abort,
8037
	.eh_should_retry_cmd	= fc_eh_should_retry_cmd,
8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049 8050 8051 8052 8053 8054 8055
	.eh_device_reset_handler = qla2xxx_eh_device_reset,
	.eh_target_reset_handler = qla2xxx_eh_target_reset,
	.eh_bus_reset_handler	= qla2xxx_eh_bus_reset,
	.eh_host_reset_handler	= qla2xxx_eh_host_reset,

	.slave_configure	= qla2xxx_slave_configure,

	.slave_alloc		= qla2xxx_slave_alloc,
	.slave_destroy		= qla2xxx_slave_destroy,
	.scan_finished		= qla2xxx_scan_finished,
	.scan_start		= qla2xxx_scan_start,
	.change_queue_depth	= scsi_change_queue_depth,
	.map_queues             = qla2xxx_map_queues,
	.this_id		= -1,
	.cmd_per_lun		= 3,
	.sg_tablesize		= SG_ALL,

	.max_sectors		= 0xFFFF,
8056
	.shost_groups		= qla2x00_host_groups,
8057 8058 8059

	.supported_mode		= MODE_INITIATOR,
	.track_queue_depth	= 1,
8060
	.cmd_size		= sizeof(srb_t),
8061 8062
};

8063
static const struct pci_error_handlers qla2xxx_err_handler = {
8064 8065 8066 8067
	.error_detected = qla2xxx_pci_error_detected,
	.mmio_enabled = qla2xxx_pci_mmio_enabled,
	.slot_reset = qla2xxx_pci_slot_reset,
	.resume = qla2xxx_pci_resume,
8068 8069
	.reset_prepare = qla_pci_reset_prepare,
	.reset_done = qla_pci_reset_done,
8070 8071
};

8072
static struct pci_device_id qla2xxx_pci_tbl[] = {
8073 8074 8075 8076 8077 8078 8079 8080 8081
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8082
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8083 8084
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8085
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8086
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8087
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8088
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8089
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8090
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8091
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8092
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8093
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8094
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8095 8096 8097 8098 8099
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8100 8101 8102 8103
	{ 0 },
};
MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);

8104
static struct pci_driver qla2xxx_pci_driver = {
8105
	.name		= QLA2XXX_DRIVER_NAME,
8106 8107 8108
	.driver		= {
		.owner		= THIS_MODULE,
	},
8109
	.id_table	= qla2xxx_pci_tbl,
8110
	.probe		= qla2x00_probe_one,
8111
	.remove		= qla2x00_remove_one,
8112
	.shutdown	= qla2x00_shutdown,
8113
	.err_handler	= &qla2xxx_err_handler,
8114 8115
};

8116
static const struct file_operations apidev_fops = {
8117
	.owner = THIS_MODULE,
8118
	.llseek = noop_llseek,
8119 8120
};

Linus Torvalds's avatar
Linus Torvalds committed
8121 8122 8123 8124 8125 8126
/**
 * qla2x00_module_init - Module initialization.
 **/
static int __init
qla2x00_module_init(void)
{
8127 8128
	int ret = 0;

8129
	BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8130 8131 8132 8133
	BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
	BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
	BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
	BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8134
	BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8135 8136
	BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
	BUILD_BUG_ON(sizeof(request_t) != 64);
8137 8138 8139
	BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
	BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8140
	BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8141
	BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8142 8143 8144 8145 8146 8147 8148
	BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
	BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
	BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
	BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
	BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
	BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
	BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8149
	BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8150 8151 8152 8153 8154
	BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
	BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
	BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
	BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
	BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8155
	BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8156 8157 8158 8159 8160
	BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
	BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
	BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
	BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
	BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8161
	BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
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	BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
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	BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
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	BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
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	BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
	BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
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	BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
	BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
	BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
	BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
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	BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
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	BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
	BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
	BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
	BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
	BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
	BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
	BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
	BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
	BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
	BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
	BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
	BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
	BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
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	BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
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	BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
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	BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
	BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
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	BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
	BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
	BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
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	BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
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	BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
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	BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8202
	BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
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	BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
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	BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
	BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
	BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
	BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
	BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
	BUILD_BUG_ON(sizeof(sw_info_t) != 32);
	BUILD_BUG_ON(sizeof(target_id_t) != 2);
8213

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	qla_trace_init();

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8216
	/* Allocate cache for SRBs. */
8217
	srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8218
	    SLAB_HWCACHE_ALIGN, NULL);
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Linus Torvalds committed
8219
	if (srb_cachep == NULL) {
8220 8221
		ql_log(ql_log_fatal, NULL, 0x0001,
		    "Unable to allocate SRB cache...Failing load!.\n");
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		return -ENOMEM;
	}

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	/* Initialize target kmem_cache and mem_pools */
	ret = qlt_init();
	if (ret < 0) {
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		goto destroy_cache;
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	} else if (ret > 0) {
		/*
		 * If initiator mode is explictly disabled by qlt_init(),
		 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
		 * performing scsi_scan_target() during LOOP UP event.
		 */
		qla2xxx_transport_functions.disable_target_scan = 1;
		qla2xxx_transport_vport_functions.disable_target_scan = 1;
	}

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	/* Derive version string. */
	strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8241
	if (ql2xextended_error_logging)
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		strcat(qla2x00_version_str, "-debug");
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	if (ql2xextended_error_logging == 1)
		ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8245

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	qla2xxx_transport_template =
	    fc_attach_transport(&qla2xxx_transport_functions);
8248
	if (!qla2xxx_transport_template) {
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		ql_log(ql_log_fatal, NULL, 0x0002,
		    "fc_attach_transport failed...Failing load!.\n");
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		ret = -ENODEV;
		goto qlt_exit;
8253
	}
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	apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
	if (apidev_major < 0) {
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		ql_log(ql_log_fatal, NULL, 0x0003,
		    "Unable to register char device %s.\n", QLA2XXX_APIDEV);
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	}

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	qla2xxx_transport_vport_template =
	    fc_attach_transport(&qla2xxx_transport_vport_functions);
	if (!qla2xxx_transport_vport_template) {
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		ql_log(ql_log_fatal, NULL, 0x0004,
		    "fc_attach_transport vport failed...Failing load!.\n");
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		ret = -ENODEV;
		goto unreg_chrdev;
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	}
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	ql_log(ql_log_info, NULL, 0x0005,
	    "QLogic Fibre Channel HBA Driver: %s.\n",
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	    qla2x00_version_str);
8272
	ret = pci_register_driver(&qla2xxx_pci_driver);
8273
	if (ret) {
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		ql_log(ql_log_fatal, NULL, 0x0006,
		    "pci_register_driver failed...ret=%d Failing load!.\n",
		    ret);
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		goto release_vport_transport;
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	}
	return ret;
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release_vport_transport:
	fc_release_transport(qla2xxx_transport_vport_template);

unreg_chrdev:
	if (apidev_major >= 0)
		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
	fc_release_transport(qla2xxx_transport_template);

qlt_exit:
	qlt_exit();

destroy_cache:
	kmem_cache_destroy(srb_cachep);
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	qla_trace_uninit();
8296
	return ret;
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}

/**
 * qla2x00_module_exit - Module cleanup.
 **/
static void __exit
qla2x00_module_exit(void)
{
8305
	pci_unregister_driver(&qla2xxx_pci_driver);
8306
	qla2x00_release_firmware();
8307
	kmem_cache_destroy(ctx_cachep);
8308
	fc_release_transport(qla2xxx_transport_vport_template);
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	if (apidev_major >= 0)
		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
	fc_release_transport(qla2xxx_transport_template);
	qlt_exit();
	kmem_cache_destroy(srb_cachep);
8314
	qla_trace_uninit();
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}

module_init(qla2x00_module_init);
module_exit(qla2x00_module_exit);

MODULE_AUTHOR("QLogic Corporation");
MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
MODULE_LICENSE("GPL");
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MODULE_FIRMWARE(FW_FILE_ISP21XX);
MODULE_FIRMWARE(FW_FILE_ISP22XX);
MODULE_FIRMWARE(FW_FILE_ISP2300);
MODULE_FIRMWARE(FW_FILE_ISP2322);
MODULE_FIRMWARE(FW_FILE_ISP24XX);
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MODULE_FIRMWARE(FW_FILE_ISP25XX);