dp_ctrl.c 53.7 KB
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// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
 */

#define pr_fmt(fmt)	"[drm-dp] %s: " fmt, __func__

#include <linux/types.h>
#include <linux/completion.h>
#include <linux/delay.h>
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#include <linux/phy/phy.h>
#include <linux/phy/phy-dp.h>
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#include <linux/pm_opp.h>
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#include <drm/drm_fixed.h>
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#include <drm/dp/drm_dp_helper.h>
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#include <drm/drm_print.h>
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#include "dp_reg.h"
#include "dp_ctrl.h"
#include "dp_link.h"

#define DP_KHZ_TO_HZ 1000
#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES	(30 * HZ / 1000) /* 30 ms */
#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)

#define DP_CTRL_INTR_READY_FOR_VIDEO     BIT(0)
#define DP_CTRL_INTR_IDLE_PATTERN_SENT  BIT(3)

#define MR_LINK_TRAINING1  0x8
#define MR_LINK_SYMBOL_ERM 0x80
#define MR_LINK_PRBS7 0x100
#define MR_LINK_CUSTOM80 0x200
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#define MR_LINK_TRAINING4  0x40

enum {
	DP_TRAINING_NONE,
	DP_TRAINING_1,
	DP_TRAINING_2,
};
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struct dp_tu_calc_input {
	u64 lclk;        /* 162, 270, 540 and 810 */
	u64 pclk_khz;    /* in KHz */
	u64 hactive;     /* active h-width */
	u64 hporch;      /* bp + fp + pulse */
	int nlanes;      /* no.of.lanes */
	int bpp;         /* bits */
	int pixel_enc;   /* 444, 420, 422 */
	int dsc_en;     /* dsc on/off */
	int async_en;   /* async mode */
	int fec_en;     /* fec */
	int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
	int num_of_dsc_slices; /* number of slices per line */
};

struct dp_vc_tu_mapping_table {
	u32 vic;
	u8 lanes;
	u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
	u8 bpp;
	u8 valid_boundary_link;
	u16 delay_start_link;
	bool boundary_moderation_en;
	u8 valid_lower_boundary_link;
	u8 upper_boundary_count;
	u8 lower_boundary_count;
	u8 tu_size_minus1;
};

struct dp_ctrl_private {
	struct dp_ctrl dp_ctrl;
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	struct drm_device *drm_dev;
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	struct device *dev;
	struct drm_dp_aux *aux;
	struct dp_panel *panel;
	struct dp_link *link;
	struct dp_power *power;
	struct dp_parser *parser;
	struct dp_catalog *catalog;

	struct completion idle_comp;
	struct completion video_comp;
};

static int dp_aux_link_configure(struct drm_dp_aux *aux,
					struct dp_link_info *link)
{
	u8 values[2];
	int err;

	values[0] = drm_dp_link_rate_to_bw_code(link->rate);
	values[1] = link->num_lanes;

	if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
		values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
	if (err < 0)
		return err;

	return 0;
}

void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);

	reinit_completion(&ctrl->idle_comp);
	dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);

	if (!wait_for_completion_timeout(&ctrl->idle_comp,
			IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
		pr_warn("PUSH_IDLE pattern timedout\n");

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	drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
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}

static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
{
	u32 config = 0, tbd;
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	const u8 *dpcd = ctrl->panel->dpcd;
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	/* Default-> LSCLK DIV: 1/4 LCLK  */
	config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);

	/* Scrambler reset enable */
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	if (drm_dp_alternate_scrambler_reset_cap(dpcd))
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		config |= DP_CONFIGURATION_CTRL_ASSR;

	tbd = dp_link_get_test_bits_depth(ctrl->link,
			ctrl->panel->dp_mode.bpp);

	if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
		pr_debug("BIT_DEPTH not set. Configure default\n");
		tbd = DP_TEST_BIT_DEPTH_8;
	}

	config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;

	/* Num of Lanes */
	config |= ((ctrl->link->link_params.num_lanes - 1)
			<< DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);

	if (drm_dp_enhanced_frame_cap(dpcd))
		config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;

	config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */

	/* sync clock & static Mvid */
	config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
	config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;

	dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
}

static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
{
	u32 cc, tb;

	dp_catalog_ctrl_lane_mapping(ctrl->catalog);
	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);

	dp_ctrl_config_ctrl(ctrl);

	tb = dp_link_get_test_bits_depth(ctrl->link,
		ctrl->panel->dp_mode.bpp);
	cc = dp_link_get_colorimetry_config(ctrl->link);
	dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
	dp_panel_timing_cfg(ctrl->panel);
}

/*
 * The structure and few functions present below are IP/Hardware
 * specific implementation. Most of the implementation will not
 * have coding comments
 */
struct tu_algo_data {
	s64 lclk_fp;
	s64 pclk_fp;
	s64 lwidth;
	s64 lwidth_fp;
	s64 hbp_relative_to_pclk;
	s64 hbp_relative_to_pclk_fp;
	int nlanes;
	int bpp;
	int pixelEnc;
	int dsc_en;
	int async_en;
	int bpc;

	uint delay_start_link_extra_pixclk;
	int extra_buffer_margin;
	s64 ratio_fp;
	s64 original_ratio_fp;

	s64 err_fp;
	s64 n_err_fp;
	s64 n_n_err_fp;
	int tu_size;
	int tu_size_desired;
	int tu_size_minus1;

	int valid_boundary_link;
	s64 resulting_valid_fp;
	s64 total_valid_fp;
	s64 effective_valid_fp;
	s64 effective_valid_recorded_fp;
	int n_tus;
	int n_tus_per_lane;
	int paired_tus;
	int remainder_tus;
	int remainder_tus_upper;
	int remainder_tus_lower;
	int extra_bytes;
	int filler_size;
	int delay_start_link;

	int extra_pclk_cycles;
	int extra_pclk_cycles_in_link_clk;
	s64 ratio_by_tu_fp;
	s64 average_valid2_fp;
	int new_valid_boundary_link;
	int remainder_symbols_exist;
	int n_symbols;
	s64 n_remainder_symbols_per_lane_fp;
	s64 last_partial_tu_fp;
	s64 TU_ratio_err_fp;

	int n_tus_incl_last_incomplete_tu;
	int extra_pclk_cycles_tmp;
	int extra_pclk_cycles_in_link_clk_tmp;
	int extra_required_bytes_new_tmp;
	int filler_size_tmp;
	int lower_filler_size_tmp;
	int delay_start_link_tmp;

	bool boundary_moderation_en;
	int boundary_mod_lower_err;
	int upper_boundary_count;
	int lower_boundary_count;
	int i_upper_boundary_count;
	int i_lower_boundary_count;
	int valid_lower_boundary_link;
	int even_distribution_BF;
	int even_distribution_legacy;
	int even_distribution;
	int min_hblank_violated;
	s64 delay_start_time_fp;
	s64 hbp_time_fp;
	s64 hactive_time_fp;
	s64 diff_abs_fp;

	s64 ratio;
};

static int _tu_param_compare(s64 a, s64 b)
{
	u32 a_sign;
	u32 b_sign;
	s64 a_temp, b_temp, minus_1;

	if (a == b)
		return 0;

	minus_1 = drm_fixp_from_fraction(-1, 1);

	a_sign = (a >> 32) & 0x80000000 ? 1 : 0;

	b_sign = (b >> 32) & 0x80000000 ? 1 : 0;

	if (a_sign > b_sign)
		return 2;
	else if (b_sign > a_sign)
		return 1;

	if (!a_sign && !b_sign) { /* positive */
		if (a > b)
			return 1;
		else
			return 2;
	} else { /* negative */
		a_temp = drm_fixp_mul(a, minus_1);
		b_temp = drm_fixp_mul(b, minus_1);

		if (a_temp > b_temp)
			return 2;
		else
			return 1;
	}
}

static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
					struct tu_algo_data *tu)
{
	int nlanes = in->nlanes;
	int dsc_num_slices = in->num_of_dsc_slices;
	int dsc_num_bytes  = 0;
	int numerator;
	s64 pclk_dsc_fp;
	s64 dwidth_dsc_fp;
	s64 hbp_dsc_fp;

	int tot_num_eoc_symbols = 0;
	int tot_num_hor_bytes   = 0;
	int tot_num_dummy_bytes = 0;
	int dwidth_dsc_bytes    = 0;
	int  eoc_bytes           = 0;

	s64 temp1_fp, temp2_fp, temp3_fp;

	tu->lclk_fp              = drm_fixp_from_fraction(in->lclk, 1);
	tu->pclk_fp              = drm_fixp_from_fraction(in->pclk_khz, 1000);
	tu->lwidth               = in->hactive;
	tu->hbp_relative_to_pclk = in->hporch;
	tu->nlanes               = in->nlanes;
	tu->bpp                  = in->bpp;
	tu->pixelEnc             = in->pixel_enc;
	tu->dsc_en               = in->dsc_en;
	tu->async_en             = in->async_en;
	tu->lwidth_fp            = drm_fixp_from_fraction(in->hactive, 1);
	tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);

	if (tu->pixelEnc == 420) {
		temp1_fp = drm_fixp_from_fraction(2, 1);
		tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
		tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
		tu->hbp_relative_to_pclk_fp =
				drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
	}

	if (tu->pixelEnc == 422) {
		switch (tu->bpp) {
		case 24:
			tu->bpp = 16;
			tu->bpc = 8;
			break;
		case 30:
			tu->bpp = 20;
			tu->bpc = 10;
			break;
		default:
			tu->bpp = 16;
			tu->bpc = 8;
			break;
		}
	} else {
		tu->bpc = tu->bpp/3;
	}

	if (!in->dsc_en)
		goto fec_check;

	temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
	temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
	temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
	temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);

	temp1_fp = drm_fixp_from_fraction(8, 1);
	temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);

	numerator = drm_fixp2int(temp3_fp);

	dsc_num_bytes  = numerator / dsc_num_slices;
	eoc_bytes           = dsc_num_bytes % nlanes;
	tot_num_eoc_symbols = nlanes * dsc_num_slices;
	tot_num_hor_bytes   = dsc_num_bytes * dsc_num_slices;
	tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;

	if (dsc_num_bytes == 0)
		pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);

	dwidth_dsc_bytes = (tot_num_hor_bytes +
				tot_num_eoc_symbols +
				(eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));

	dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);

	temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
	temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
	pclk_dsc_fp = temp1_fp;

	temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
	temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
	hbp_dsc_fp = temp2_fp;

	/* output */
	tu->pclk_fp = pclk_dsc_fp;
	tu->lwidth_fp = dwidth_dsc_fp;
	tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;

fec_check:
	if (in->fec_en) {
		temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
		tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
	}
}

static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
{
	s64 temp1_fp, temp2_fp, temp, temp1, temp2;
	int compare_result_1, compare_result_2, compare_result_3;

	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);

	tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);

	temp = (tu->i_upper_boundary_count *
				tu->new_valid_boundary_link +
				tu->i_lower_boundary_count *
				(tu->new_valid_boundary_link-1));
	tu->average_valid2_fp = drm_fixp_from_fraction(temp,
					(tu->i_upper_boundary_count +
					tu->i_lower_boundary_count));

	temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
	temp2_fp = tu->lwidth_fp;
	temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
	temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
	tu->n_tus = drm_fixp2int(temp2_fp);
	if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
		tu->n_tus += 1;

	temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
	temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
	temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
	temp2_fp = temp1_fp - temp2_fp;
	temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
	temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
	tu->n_remainder_symbols_per_lane_fp = temp2_fp;

	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	tu->last_partial_tu_fp =
			drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
					temp1_fp);

	if (tu->n_remainder_symbols_per_lane_fp != 0)
		tu->remainder_symbols_exist = 1;
	else
		tu->remainder_symbols_exist = 0;

	temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
	tu->n_tus_per_lane = drm_fixp2int(temp1_fp);

	tu->paired_tus = (int)((tu->n_tus_per_lane) /
					(tu->i_upper_boundary_count +
					 tu->i_lower_boundary_count));

	tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
						(tu->i_upper_boundary_count +
						tu->i_lower_boundary_count);

	if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
		tu->remainder_tus_upper = tu->i_upper_boundary_count;
		tu->remainder_tus_lower = tu->remainder_tus -
						tu->i_upper_boundary_count;
	} else {
		tu->remainder_tus_upper = tu->remainder_tus;
		tu->remainder_tus_lower = 0;
	}

	temp = tu->paired_tus * (tu->i_upper_boundary_count *
				tu->new_valid_boundary_link +
				tu->i_lower_boundary_count *
				(tu->new_valid_boundary_link - 1)) +
				(tu->remainder_tus_upper *
				 tu->new_valid_boundary_link) +
				(tu->remainder_tus_lower *
				(tu->new_valid_boundary_link - 1));
	tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);

	if (tu->remainder_symbols_exist) {
		temp1_fp = tu->total_valid_fp +
				tu->n_remainder_symbols_per_lane_fp;
		temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
		temp2_fp = temp2_fp + tu->last_partial_tu_fp;
		temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
	} else {
		temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
		temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
	}
	tu->effective_valid_fp = temp1_fp;

	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
	tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;

	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
	tu->n_err_fp = tu->average_valid2_fp - temp2_fp;

	tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;

	temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
	temp2_fp = tu->lwidth_fp;
	temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
	temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);

	if (temp2_fp)
		tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
	else
		tu->n_tus_incl_last_incomplete_tu = 0;

	temp1 = 0;
	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
	temp1_fp = tu->average_valid2_fp - temp2_fp;
	temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
	temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);

	if (temp1_fp)
		temp1 = drm_fixp2int_ceil(temp1_fp);

	temp = tu->i_upper_boundary_count * tu->nlanes;
	temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
	temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
	temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
	temp2_fp = temp1_fp - temp2_fp;
	temp1_fp = drm_fixp_from_fraction(temp, 1);
	temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);

	if (temp2_fp)
		temp2 = drm_fixp2int_ceil(temp2_fp);
	else
		temp2 = 0;
	tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);

	temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
	temp2_fp = drm_fixp_from_fraction(
	tu->extra_required_bytes_new_tmp, 1);
	temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);

	if (temp1_fp)
		tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
	else
		tu->extra_pclk_cycles_tmp = 0;

	temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
	temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
	temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);

	if (temp1_fp)
		tu->extra_pclk_cycles_in_link_clk_tmp =
						drm_fixp2int_ceil(temp1_fp);
	else
		tu->extra_pclk_cycles_in_link_clk_tmp = 0;

	tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;

	tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;

	tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
					tu->lower_filler_size_tmp +
					tu->extra_buffer_margin;

	temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
	tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);

	compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
	if (compare_result_1 == 2)
		compare_result_1 = 1;
	else
		compare_result_1 = 0;

	compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
	if (compare_result_2 == 2)
		compare_result_2 = 1;
	else
		compare_result_2 = 0;

	compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
					tu->delay_start_time_fp);
	if (compare_result_3 == 2)
		compare_result_3 = 0;
	else
		compare_result_3 = 1;

	if (((tu->even_distribution == 1) ||
			((tu->even_distribution_BF == 0) &&
			(tu->even_distribution_legacy == 0))) &&
			tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
			compare_result_2 &&
			(compare_result_1 || (tu->min_hblank_violated == 1)) &&
			(tu->new_valid_boundary_link - 1) > 0 &&
			compare_result_3 &&
			(tu->delay_start_link_tmp <= 1023)) {
		tu->upper_boundary_count = tu->i_upper_boundary_count;
		tu->lower_boundary_count = tu->i_lower_boundary_count;
		tu->err_fp = tu->n_n_err_fp;
		tu->boundary_moderation_en = true;
		tu->tu_size_desired = tu->tu_size;
		tu->valid_boundary_link = tu->new_valid_boundary_link;
		tu->effective_valid_recorded_fp = tu->effective_valid_fp;
		tu->even_distribution_BF = 1;
		tu->delay_start_link = tu->delay_start_link_tmp;
	} else if (tu->boundary_mod_lower_err == 0) {
		compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
							tu->diff_abs_fp);
		if (compare_result_1 == 2)
			tu->boundary_mod_lower_err = 1;
	}
}

606 607 608
static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl,
				struct dp_tu_calc_input *in,
				struct dp_vc_tu_mapping_table *tu_table)
609
{
610
	struct tu_algo_data *tu;
611 612 613 614 615 616 617 618 619 620 621 622 623 624
	int compare_result_1, compare_result_2;
	u64 temp = 0;
	s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;

	s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
	s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
	s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
	s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);

	u8 DP_BRUTE_FORCE = 1;
	s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
	uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
	uint HBLANK_MARGIN = 4;

625 626
	tu = kzalloc(sizeof(*tu), GFP_KERNEL);
	if (!tu)
627
		return;
628

629
	dp_panel_update_tu_timings(in, tu);
630

631
	tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
632 633

	temp1_fp = drm_fixp_from_fraction(4, 1);
634 635 636
	temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
	temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
	tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
637

638 639 640
	temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
	temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
	temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
641
	temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
	tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);

	tu->original_ratio_fp = tu->ratio_fp;
	tu->boundary_moderation_en = false;
	tu->upper_boundary_count = 0;
	tu->lower_boundary_count = 0;
	tu->i_upper_boundary_count = 0;
	tu->i_lower_boundary_count = 0;
	tu->valid_lower_boundary_link = 0;
	tu->even_distribution_BF = 0;
	tu->even_distribution_legacy = 0;
	tu->even_distribution = 0;
	tu->delay_start_time_fp = 0;

	tu->err_fp = drm_fixp_from_fraction(1000, 1);
	tu->n_err_fp = 0;
	tu->n_n_err_fp = 0;

	tu->ratio = drm_fixp2int(tu->ratio_fp);
	temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
	div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
663
	if (temp2_fp != 0 &&
664 665 666 667 668
			!tu->ratio && tu->dsc_en == 0) {
		tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
		tu->ratio = drm_fixp2int(tu->ratio_fp);
		if (tu->ratio)
			tu->ratio_fp = drm_fixp_from_fraction(1, 1);
669 670
	}

671 672
	if (tu->ratio > 1)
		tu->ratio = 1;
673

674
	if (tu->ratio == 1)
675 676
		goto tu_size_calc;

677
	compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
678 679 680 681 682
	if (!compare_result_1 || compare_result_1 == 1)
		compare_result_1 = 1;
	else
		compare_result_1 = 0;

683
	compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
684 685 686 687 688
	if (!compare_result_2 || compare_result_2 == 2)
		compare_result_2 = 1;
	else
		compare_result_2 = 0;

689
	if (tu->dsc_en && compare_result_1 && compare_result_2) {
690
		HBLANK_MARGIN += 4;
691 692
		drm_dbg_dp(ctrl->drm_dev,
			"increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
693 694 695
	}

tu_size_calc:
696 697 698
	for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
		temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
		temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
699 700
		temp = drm_fixp2int_ceil(temp2_fp);
		temp1_fp = drm_fixp_from_fraction(temp, 1);
701
		tu->n_err_fp = temp1_fp - temp2_fp;
702

703 704 705
		if (tu->n_err_fp < tu->err_fp) {
			tu->err_fp = tu->n_err_fp;
			tu->tu_size_desired = tu->tu_size;
706 707 708
		}
	}

709
	tu->tu_size_minus1 = tu->tu_size_desired - 1;
710

711 712 713
	temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
	temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
	tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
714

715 716
	temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
	temp2_fp = tu->lwidth_fp;
717 718
	temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);

719
	temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
720
	temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
721
	tu->n_tus = drm_fixp2int(temp2_fp);
722
	if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
723
		tu->n_tus += 1;
724

725
	tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
726 727 728 729

	drm_dbg_dp(ctrl->drm_dev,
			"n_sym = %d, num_of_tus = %d\n",
			tu->valid_boundary_link, tu->n_tus);
730

731 732 733
	temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
	temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
	temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
734
	temp2_fp = temp1_fp - temp2_fp;
735
	temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
736 737 738 739
	temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);

	temp = drm_fixp2int(temp2_fp);
	if (temp && temp2_fp)
740
		tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
741
	else
742
		tu->extra_bytes = 0;
743

744 745
	temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
	temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
746 747 748
	temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);

	if (temp && temp1_fp)
749
		tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
750
	else
751
		tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
752

753 754
	temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
	temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
755 756 757
	temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);

	if (temp1_fp)
758
		tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
759
	else
760
		tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
761

762
	tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
763

764 765
	temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
	tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
766

767 768
	tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
				tu->filler_size + tu->extra_buffer_margin;
769

770 771
	tu->resulting_valid_fp =
			drm_fixp_from_fraction(tu->valid_boundary_link, 1);
772

773 774 775
	temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
	temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
	tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
776 777

	temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
778 779
	temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
	tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
780

781 782
	temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
	tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
783

784 785
	compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
					tu->delay_start_time_fp);
786
	if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
787
		tu->min_hblank_violated = 1;
788

789
	tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
790

791 792
	compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
						tu->delay_start_time_fp);
793
	if (compare_result_2 == 2)
794
		tu->min_hblank_violated = 1;
795

796
	tu->delay_start_time_fp = 0;
797 798 799

	/* brute force */

800 801
	tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
	tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
802

803 804 805
	temp = drm_fixp2int(tu->diff_abs_fp);
	if (!temp && tu->diff_abs_fp <= 0xffff)
		tu->diff_abs_fp = 0;
806 807

	/* if(diff_abs < 0) diff_abs *= -1 */
808 809
	if (tu->diff_abs_fp < 0)
		tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
810

811 812 813 814
	tu->boundary_mod_lower_err = 0;
	if ((tu->diff_abs_fp != 0 &&
			((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
			 (tu->even_distribution_legacy == 0) ||
815
			 (DP_BRUTE_FORCE == 1))) ||
816
			(tu->min_hblank_violated == 1)) {
817
		do {
818
			tu->err_fp = drm_fixp_from_fraction(1000, 1);
819

820
			temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
821
			temp2_fp = drm_fixp_from_fraction(
822
					tu->delay_start_link_extra_pixclk, 1);
823 824 825
			temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);

			if (temp1_fp)
826
				tu->extra_buffer_margin =
827 828
					drm_fixp2int_ceil(temp1_fp);
			else
829
				tu->extra_buffer_margin = 0;
830

831 832
			temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
			temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
833 834

			if (temp1_fp)
835
				tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
836
			else
837 838 839 840 841 842 843 844 845 846
				tu->n_symbols = 0;

			for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
				for (tu->i_upper_boundary_count = 1;
					tu->i_upper_boundary_count <= 15;
					tu->i_upper_boundary_count++) {
					for (tu->i_lower_boundary_count = 1;
						tu->i_lower_boundary_count <= 15;
						tu->i_lower_boundary_count++) {
						_tu_valid_boundary_calc(tu);
847 848 849
					}
				}
			}
850 851 852 853
			tu->delay_start_link_extra_pixclk--;
		} while (tu->boundary_moderation_en != true &&
			tu->boundary_mod_lower_err == 1 &&
			tu->delay_start_link_extra_pixclk != 0);
854

855
		if (tu->boundary_moderation_en == true) {
856
			temp1_fp = drm_fixp_from_fraction(
857 858 859 860
					(tu->upper_boundary_count *
					tu->valid_boundary_link +
					tu->lower_boundary_count *
					(tu->valid_boundary_link - 1)), 1);
861
			temp2_fp = drm_fixp_from_fraction(
862 863 864
					(tu->upper_boundary_count +
					tu->lower_boundary_count), 1);
			tu->resulting_valid_fp =
865 866 867
					drm_fixp_div(temp1_fp, temp2_fp);

			temp1_fp = drm_fixp_from_fraction(
868 869 870
					tu->tu_size_desired, 1);
			tu->ratio_by_tu_fp =
				drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
871

872 873
			tu->valid_lower_boundary_link =
				tu->valid_boundary_link - 1;
874

875 876
			temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
			temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
877
			temp2_fp = drm_fixp_div(temp1_fp,
878 879
						tu->resulting_valid_fp);
			tu->n_tus = drm_fixp2int(temp2_fp);
880

881 882
			tu->tu_size_minus1 = tu->tu_size_desired - 1;
			tu->even_distribution_BF = 1;
883 884

			temp1_fp =
885
				drm_fixp_from_fraction(tu->tu_size_desired, 1);
886
			temp2_fp =
887 888
				drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
			tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
889 890 891
		}
	}

892
	temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
893 894 895 896 897 898

	if (temp2_fp)
		temp = drm_fixp2int_ceil(temp2_fp);
	else
		temp = 0;

899 900 901
	temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
	temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
	temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
902 903 904 905 906
	temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
	temp1_fp = drm_fixp_from_fraction(temp, 1);
	temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
	temp = drm_fixp2int(temp2_fp);

907 908
	if (tu->async_en)
		tu->delay_start_link += (int)temp;
909

910 911
	temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
	tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
912 913

	/* OUTPUTS */
914 915 916 917 918 919 920
	tu_table->valid_boundary_link       = tu->valid_boundary_link;
	tu_table->delay_start_link          = tu->delay_start_link;
	tu_table->boundary_moderation_en    = tu->boundary_moderation_en;
	tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
	tu_table->upper_boundary_count      = tu->upper_boundary_count;
	tu_table->lower_boundary_count      = tu->lower_boundary_count;
	tu_table->tu_size_minus1            = tu->tu_size_minus1;
921

922
	drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
923
				tu_table->valid_boundary_link);
924
	drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
925
				tu_table->delay_start_link);
926
	drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
927
			tu_table->boundary_moderation_en);
928
	drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
929
			tu_table->valid_lower_boundary_link);
930
	drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
931
			tu_table->upper_boundary_count);
932
	drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
933
			tu_table->lower_boundary_count);
934 935
	drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
			tu_table->tu_size_minus1);
936 937

	kfree(tu);
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960
}

static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
		struct dp_vc_tu_mapping_table *tu_table)
{
	struct dp_tu_calc_input in;
	struct drm_display_mode *drm_mode;

	drm_mode = &ctrl->panel->dp_mode.drm_mode;

	in.lclk = ctrl->link->link_params.rate / 1000;
	in.pclk_khz = drm_mode->clock;
	in.hactive = drm_mode->hdisplay;
	in.hporch = drm_mode->htotal - drm_mode->hdisplay;
	in.nlanes = ctrl->link->link_params.num_lanes;
	in.bpp = ctrl->panel->dp_mode.bpp;
	in.pixel_enc = 444;
	in.dsc_en = 0;
	in.async_en = 0;
	in.fec_en = 0;
	in.num_of_dsc_slices = 0;
	in.compress_ratio = 100;

961
	_dp_ctrl_calc_tu(ctrl, &in, tu_table);
962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996
}

static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
{
	u32 dp_tu = 0x0;
	u32 valid_boundary = 0x0;
	u32 valid_boundary2 = 0x0;
	struct dp_vc_tu_mapping_table tu_calc_table;

	dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);

	dp_tu |= tu_calc_table.tu_size_minus1;
	valid_boundary |= tu_calc_table.valid_boundary_link;
	valid_boundary |= (tu_calc_table.delay_start_link << 16);

	valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
	valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
	valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);

	if (tu_calc_table.boundary_moderation_en)
		valid_boundary2 |= BIT(0);

	pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
			dp_tu, valid_boundary, valid_boundary2);

	dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
				dp_tu, valid_boundary, valid_boundary2);
}

static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
{
	int ret = 0;

	if (!wait_for_completion_timeout(&ctrl->video_comp,
				WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
997
		DRM_ERROR("wait4video timedout\n");
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011
		ret = -ETIMEDOUT;
	}
	return ret;
}

static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
{
	struct dp_link *link = ctrl->link;
	int ret = 0, lane, lane_cnt;
	u8 buf[4];
	u32 max_level_reached = 0;
	u32 voltage_swing_level = link->phy_params.v_level;
	u32 pre_emphasis_level = link->phy_params.p_level;

1012 1013 1014
	drm_dbg_dp(ctrl->drm_dev,
		"voltage level: %d emphasis level: %d\n",
			voltage_swing_level, pre_emphasis_level);
1015 1016 1017 1018 1019 1020
	ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
		voltage_swing_level, pre_emphasis_level);

	if (ret)
		return ret;

1021
	if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1022 1023
		drm_dbg_dp(ctrl->drm_dev,
				"max. voltage swing level reached %d\n",
1024 1025 1026 1027
				voltage_swing_level);
		max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
	}

1028
	if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1029 1030
		drm_dbg_dp(ctrl->drm_dev,
				"max. pre-emphasis level reached %d\n",
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
				pre_emphasis_level);
		max_level_reached  |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
	}

	pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;

	lane_cnt = ctrl->link->link_params.num_lanes;
	for (lane = 0; lane < lane_cnt; lane++)
		buf[lane] = voltage_swing_level | pre_emphasis_level
				| max_level_reached;

1042 1043
	drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
			voltage_swing_level | pre_emphasis_level);
1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
	ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
					buf, lane_cnt);
	if (ret == lane_cnt)
		ret = 0;

	return ret;
}

static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
		u8 pattern)
{
	u8 buf;
	int ret = 0;

1058
	drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1059 1060

	buf = pattern;
1061 1062 1063 1064 1065

	if (pattern && pattern != DP_TRAINING_PATTERN_4)
		buf |= DP_LINK_SCRAMBLING_DISABLE;

	ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1066 1067 1068 1069 1070 1071
	return ret == 1;
}

static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
				    u8 *link_status)
{
1072
	int ret = 0, len;
1073

1074 1075 1076 1077
	len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
	if (len != DP_LINK_STATUS_SIZE) {
		DRM_ERROR("DP link status read failed, err: %d\n", len);
		ret = -EINVAL;
1078 1079
	}

1080
	return ret;
1081 1082
}

1083
static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1084
			int *training_step)
1085 1086 1087
{
	int tries, old_v_level, ret = 0;
	u8 link_status[DP_LINK_STATUS_SIZE];
1088
	int const maximum_retries = 4;
1089 1090 1091

	dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);

1092 1093
	*training_step = DP_TRAINING_1;

1094
	ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1095 1096 1097 1098
	if (ret)
		return ret;
	dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
		DP_LINK_SCRAMBLING_DISABLE);
1099

1100 1101 1102 1103 1104 1105 1106
	ret = dp_ctrl_update_vx_px(ctrl);
	if (ret)
		return ret;

	tries = 0;
	old_v_level = ctrl->link->phy_params.v_level;
	for (tries = 0; tries < maximum_retries; tries++) {
1107
		drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1108 1109 1110 1111 1112 1113 1114

		ret = dp_ctrl_read_link_status(ctrl, link_status);
		if (ret)
			return ret;

		if (drm_dp_clock_recovery_ok(link_status,
			ctrl->link->link_params.num_lanes)) {
1115
			return 0;
1116 1117
		}

1118
		if (ctrl->link->phy_params.v_level >=
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
			DP_TRAIN_VOLTAGE_SWING_MAX) {
			DRM_ERROR_RATELIMITED("max v_level reached\n");
			return -EAGAIN;
		}

		if (old_v_level != ctrl->link->phy_params.v_level) {
			tries = 0;
			old_v_level = ctrl->link->phy_params.v_level;
		}

		dp_link_adjust_levels(ctrl->link, link_status);
		ret = dp_ctrl_update_vx_px(ctrl);
		if (ret)
			return ret;
	}

	DRM_ERROR("max tries reached\n");
	return -ETIMEDOUT;
}

1139
static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1140
{
1141 1142
	int ret = 0;

1143 1144 1145 1146 1147 1148 1149 1150
	switch (ctrl->link->link_params.rate) {
	case 810000:
		ctrl->link->link_params.rate = 540000;
		break;
	case 540000:
		ctrl->link->link_params.rate = 270000;
		break;
	case 270000:
1151 1152
		ctrl->link->link_params.rate = 162000;
		break;
1153 1154
	case 162000:
	default:
1155
		ret = -EINVAL;
1156
		break;
1157
	}
1158

1159 1160 1161 1162
	if (!ret) {
		drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
				ctrl->link->link_params.rate);
	}
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179

	return ret;
}

static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
{

	if (ctrl->link->link_params.num_lanes == 1)
		return -1;

	ctrl->link->link_params.num_lanes /= 2;
	ctrl->link->link_params.rate = ctrl->panel->link_info.rate;

	ctrl->link->phy_params.p_level = 0;
	ctrl->link->phy_params.v_level = 0;

	return 0;
1180 1181 1182 1183 1184
}

static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
{
	dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1185
	drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1186 1187
}

1188
static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1189
			int *training_step)
1190 1191
{
	int tries = 0, ret = 0;
1192 1193
	u8 pattern;
	u32 state_ctrl_bit;
1194 1195 1196 1197 1198
	int const maximum_retries = 5;
	u8 link_status[DP_LINK_STATUS_SIZE];

	dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);

1199 1200
	*training_step = DP_TRAINING_2;

1201 1202 1203 1204
	if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
		pattern = DP_TRAINING_PATTERN_4;
		state_ctrl_bit = 4;
	} else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1205
		pattern = DP_TRAINING_PATTERN_3;
1206 1207
		state_ctrl_bit = 3;
	} else {
1208
		pattern = DP_TRAINING_PATTERN_2;
1209 1210
		state_ctrl_bit = 2;
	}
1211

1212
	ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1213 1214 1215 1216 1217 1218
	if (ret)
		return ret;

	dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);

	for (tries = 0; tries <= maximum_retries; tries++) {
1219
		drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1220 1221 1222 1223 1224 1225

		ret = dp_ctrl_read_link_status(ctrl, link_status);
		if (ret)
			return ret;

		if (drm_dp_channel_eq_ok(link_status,
1226 1227 1228
			ctrl->link->link_params.num_lanes)) {
			return 0;
		}
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239

		dp_link_adjust_levels(ctrl->link, link_status);
		ret = dp_ctrl_update_vx_px(ctrl);
		if (ret)
			return ret;

	}

	return -ETIMEDOUT;
}

1240 1241 1242
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);

static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1243
			int *training_step)
1244 1245
{
	int ret = 0;
1246
	const u8 *dpcd = ctrl->panel->dpcd;
1247
	u8 encoding = DP_SET_ANSI_8B10B;
1248
	u8 ssc;
1249
	u8 assr;
1250 1251 1252 1253 1254 1255 1256 1257 1258
	struct dp_link_info link_info = {0};

	dp_ctrl_config_ctrl(ctrl);

	link_info.num_lanes = ctrl->link->link_params.num_lanes;
	link_info.rate = ctrl->link->link_params.rate;
	link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;

	dp_aux_link_configure(ctrl->aux, &link_info);
1259 1260 1261 1262 1263 1264

	if (drm_dp_max_downspread(dpcd)) {
		ssc = DP_SPREAD_AMP_0_5;
		drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
	}

1265 1266 1267
	drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
				&encoding, 1);

1268 1269 1270 1271 1272 1273
	if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
		assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
		drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
				&assr, 1);
	}

1274
	ret = dp_ctrl_link_train_1(ctrl, training_step);
1275 1276 1277 1278 1279 1280
	if (ret) {
		DRM_ERROR("link training #1 failed. ret=%d\n", ret);
		goto end;
	}

	/* print success info as this is a result of user initiated action */
1281
	drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1282

1283
	ret = dp_ctrl_link_train_2(ctrl, training_step);
1284 1285 1286 1287 1288 1289
	if (ret) {
		DRM_ERROR("link training #2 failed. ret=%d\n", ret);
		goto end;
	}

	/* print success info as this is a result of user initiated action */
1290
	drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1291 1292 1293 1294 1295 1296 1297

end:
	dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);

	return ret;
}

1298
static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1299
			int *training_step)
1300 1301 1302 1303 1304 1305 1306 1307 1308
{
	int ret = 0;

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);

	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
		return ret;

	/*
1309 1310 1311
	 * As part of previous calls, DP controller state might have
	 * transitioned to PUSH_IDLE. In order to start transmitting
	 * a link training pattern, we have to first do soft reset.
1312 1313
	 */

1314
	ret = dp_ctrl_link_train(ctrl, training_step);
1315 1316 1317 1318 1319

	return ret;
}

static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1320
			enum dp_pm_type module, char *name, unsigned long rate)
1321
{
1322 1323
	u32 num = ctrl->parser->mp[module].num_clk;
	struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1324 1325 1326 1327 1328 1329

	while (num && strcmp(cfg->clk_name, name)) {
		num--;
		cfg++;
	}

1330 1331
	drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
						rate, name);
1332 1333 1334 1335

	if (num)
		cfg->rate = rate;
	else
1336
		DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1337 1338 1339 1340 1341 1342
				name, rate);
}

static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
{
	int ret = 0;
1343 1344 1345
	struct dp_io *dp_io = &ctrl->parser->io;
	struct phy *phy = dp_io->phy;
	struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1346
	const u8 *dpcd = ctrl->panel->dpcd;
1347

1348 1349
	opts_dp->lanes = ctrl->link->link_params.num_lanes;
	opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1350
	opts_dp->ssc = drm_dp_max_downspread(dpcd);
1351
	dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1352 1353 1354 1355
					ctrl->link->link_params.rate * 1000);

	phy_configure(phy, &dp_io->phy_opts);
	phy_power_on(phy);
1356 1357 1358 1359 1360

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
	if (ret)
		DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);

1361
	drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
		ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);

	return ret;
}

static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
{
	int ret = 0;

	dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1372
					ctrl->dp_ctrl.pixel_rate * 1000);
1373 1374 1375 1376 1377

	ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
	if (ret)
		DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);

1378
	drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1379 1380
			ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);

1381 1382 1383
	return ret;
}

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
{
	struct dp_ctrl_private *ctrl;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);

	dp_catalog_ctrl_reset(ctrl->catalog);

	if (enable)
		dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
}

void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1397 1398
{
	struct dp_ctrl_private *ctrl;
1399 1400
	struct dp_io *dp_io;
	struct phy *phy;
1401 1402

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1403 1404
	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;
1405 1406

	dp_catalog_ctrl_phy_reset(ctrl->catalog);
1407
	phy_init(phy);
1408 1409

	drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1410
			phy, phy->init_count, phy->power_count);
1411 1412
}

1413
void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1414 1415
{
	struct dp_ctrl_private *ctrl;
1416 1417
	struct dp_io *dp_io;
	struct phy *phy;
1418 1419

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1420 1421
	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;
1422

1423
	dp_catalog_ctrl_phy_reset(ctrl->catalog);
1424
	phy_exit(phy);
1425
	drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1426
			phy, phy->init_count, phy->power_count);
1427 1428 1429 1430
}

static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
{
1431
	const u8 *dpcd = ctrl->panel->dpcd;
1432 1433 1434 1435 1436 1437

	/*
	 * For better interop experience, used a fixed NVID=0x8000
	 * whenever connected to a VGA dongle downstream.
	 */
	if (drm_dp_is_branch(dpcd))
1438 1439
		return (drm_dp_has_quirk(&ctrl->panel->desc,
					 DP_DPCD_QUIRK_CONSTANT_N));
1440 1441 1442 1443 1444 1445 1446

	return false;
}

static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
	int ret = 0;
1447 1448 1449
	struct dp_io *dp_io = &ctrl->parser->io;
	struct phy *phy = dp_io->phy;
	struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1450 1451

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1452 1453
	opts_dp->lanes = ctrl->link->link_params.num_lanes;
	phy_configure(phy, &dp_io->phy_opts);
1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
	/*
	 * Disable and re-enable the mainlink clock since the
	 * link clock might have been adjusted as part of the
	 * link maintenance.
	 */
	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
	if (ret) {
		DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
		return ret;
	}
1464
	phy_power_off(phy);
1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
	/* hw recommended delay before re-enabling clocks */
	msleep(20);

	ret = dp_ctrl_enable_mainlink_clocks(ctrl);
	if (ret) {
		DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
		return ret;
	}

	return ret;
}

1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495
static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
	struct dp_io *dp_io;
	struct phy *phy;
	int ret;

	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);

	dp_catalog_ctrl_reset(ctrl->catalog);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
	if (ret) {
		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
	}

	phy_power_off(phy);
1496 1497

	/* aux channel down, reinit phy */
1498
	phy_exit(phy);
1499
	phy_init(phy);
1500

1501
	drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1502
			phy, phy->init_count, phy->power_count);
1503 1504 1505
	return 0;
}

1506 1507 1508
static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
{
	int ret = 0;
1509
	int training_step = DP_TRAINING_NONE;
1510 1511 1512

	dp_ctrl_push_idle(&ctrl->dp_ctrl);

1513 1514 1515
	ctrl->link->phy_params.p_level = 0;
	ctrl->link->phy_params.v_level = 0;

1516 1517
	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;

1518
	ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1519 1520
	if (ret)
		goto end;
1521

1522 1523 1524 1525 1526 1527
	dp_ctrl_clear_training_pattern(ctrl);

	dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);

	ret = dp_ctrl_wait4video_ready(ctrl);
end:
1528 1529 1530 1531 1532 1533 1534 1535
	return ret;
}

static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
{
	int ret = 0;

	if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1536 1537
		drm_dbg_dp(ctrl->drm_dev,
			"no test pattern selected by sink\n");
1538 1539 1540 1541 1542 1543 1544 1545
		return ret;
	}

	/*
	 * The global reset will need DP link related clocks to be
	 * running. Add the global reset just before disabling the
	 * link clocks and core clocks.
	 */
1546
	ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl);
1547 1548 1549 1550 1551
	if (ret) {
		DRM_ERROR("failed to disable DP controller\n");
		return ret;
	}

1552 1553 1554 1555 1556
	ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
	if (!ret)
		ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
	else
		DRM_ERROR("failed to enable DP link controller\n");
1557 1558 1559 1560 1561 1562 1563 1564 1565 1566

	return ret;
}

static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
{
	bool success = false;
	u32 pattern_sent = 0x0;
	u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;

1567
	drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1568 1569 1570 1571 1572 1573 1574 1575

	if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
			ctrl->link->phy_params.v_level,
			ctrl->link->phy_params.p_level)) {
		DRM_ERROR("Failed to set v/p levels\n");
		return false;
	}
	dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1576
	dp_ctrl_update_vx_px(ctrl);
1577 1578 1579 1580 1581 1582
	dp_link_send_test_response(ctrl->link);

	pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);

	switch (pattern_sent) {
	case MR_LINK_TRAINING1:
1583 1584
		success = (pattern_requested ==
				DP_PHY_TEST_PATTERN_D10_2);
1585 1586
		break;
	case MR_LINK_SYMBOL_ERM:
1587 1588 1589 1590
		success = ((pattern_requested ==
			DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
				(pattern_requested ==
				DP_PHY_TEST_PATTERN_CP2520));
1591 1592
		break;
	case MR_LINK_PRBS7:
1593 1594
		success = (pattern_requested ==
				DP_PHY_TEST_PATTERN_PRBS7);
1595 1596
		break;
	case MR_LINK_CUSTOM80:
1597 1598 1599 1600 1601 1602
		success = (pattern_requested ==
				DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
		break;
	case MR_LINK_TRAINING4:
		success = (pattern_requested ==
				DP_PHY_TEST_PATTERN_SEL_MASK);
1603 1604 1605 1606 1607
		break;
	default:
		success = false;
	}

1608 1609
	drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
		success ? "success" : "failed", pattern_requested);
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
	return success;
}

void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;
	u32 sink_request = 0x0;

	if (!dp_ctrl) {
		DRM_ERROR("invalid input\n");
		return;
	}

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
	sink_request = ctrl->link->sink_request;

	if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1627
		drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1628 1629 1630 1631 1632 1633
		if (dp_ctrl_process_phy_test_request(ctrl)) {
			DRM_ERROR("process phy_test_req failed\n");
			return;
		}
	}

1634
	if (sink_request & DP_LINK_STATUS_UPDATED) {
1635
		if (dp_ctrl_link_maintenance(ctrl)) {
1636
			DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1637 1638
			return;
		}
1639
	}
1640 1641 1642 1643 1644 1645 1646 1647 1648 1649

	if (sink_request & DP_TEST_LINK_TRAINING) {
		dp_link_send_test_response(ctrl->link);
		if (dp_ctrl_link_maintenance(ctrl)) {
			DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
			return;
		}
	}
}

1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
static bool dp_ctrl_clock_recovery_any_ok(
			const u8 link_status[DP_LINK_STATUS_SIZE],
			int lane_count)
{
	int reduced_cnt;

	if (lane_count <= 1)
		return false;

	/*
	 * only interested in the lane number after reduced
	 * lane_count = 4, then only interested in 2 lanes
	 * lane_count = 2, then only interested in 1 lane
	 */
	reduced_cnt = lane_count >> 1;

	return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
}

1669 1670 1671 1672 1673 1674 1675 1676 1677 1678
static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
{
	u8 link_status[DP_LINK_STATUS_SIZE];
	int num_lanes = ctrl->link->link_params.num_lanes;

	dp_ctrl_read_link_status(ctrl, link_status);

	return drm_dp_channel_eq_ok(link_status, num_lanes);
}

1679
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1680 1681 1682 1683
{
	int rc = 0;
	struct dp_ctrl_private *ctrl;
	u32 rate = 0;
1684
	int link_train_max_retries = 5;
1685
	u32 const phy_cts_pixel_clk_khz = 148500;
1686
	u8 link_status[DP_LINK_STATUS_SIZE];
1687
	unsigned int training_step;
1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698

	if (!dp_ctrl)
		return -EINVAL;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);

	rate = ctrl->panel->link_info.rate;

	dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);

	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1699 1700
		drm_dbg_dp(ctrl->drm_dev,
				"using phy test link parameters\n");
1701 1702 1703 1704 1705 1706 1707 1708 1709
		if (!ctrl->panel->dp_mode.drm_mode.clock)
			ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
	} else {
		ctrl->link->link_params.rate = rate;
		ctrl->link->link_params.num_lanes =
			ctrl->panel->link_info.num_lanes;
		ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
	}

1710 1711 1712
	drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
		ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
		ctrl->dp_ctrl.pixel_rate);
1713

1714 1715 1716
	ctrl->link->phy_params.p_level = 0;
	ctrl->link->phy_params.v_level = 0;

1717 1718 1719 1720
	rc = dp_ctrl_enable_mainlink_clocks(ctrl);
	if (rc)
		return rc;

1721
	while (--link_train_max_retries) {
1722 1723 1724 1725 1726 1727
		rc = dp_ctrl_reinitialize_mainlink(ctrl);
		if (rc) {
			DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
					rc);
			break;
		}
1728 1729

		training_step = DP_TRAINING_NONE;
1730
		rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1731 1732
		if (rc == 0) {
			/* training completed successfully */
1733
			break;
1734 1735
		} else if (training_step == DP_TRAINING_1) {
			/* link train_1 failed */
1736
			if (!dp_catalog_link_is_connected(ctrl->catalog))
1737
				break;
1738 1739

			dp_ctrl_read_link_status(ctrl, link_status);
1740

1741 1742
			rc = dp_ctrl_link_rate_down_shift(ctrl);
			if (rc < 0) { /* already in RBR = 1.6G */
1743 1744
				if (dp_ctrl_clock_recovery_any_ok(link_status,
					ctrl->link->link_params.num_lanes)) {
1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
					/*
					 * some lanes are ready,
					 * reduce lane number
					 */
					rc = dp_ctrl_link_lane_down_shift(ctrl);
					if (rc < 0) { /* lane == 1 already */
						/* end with failure */
						break;
					}
				} else {
					/* end with failure */
					break; /* lane == 1 already */
				}
			}
		} else if (training_step == DP_TRAINING_2) {
1760 1761
			/* link train_2 failed */
			if (!dp_catalog_link_is_connected(ctrl->catalog))
1762 1763
				break;

1764 1765 1766 1767 1768 1769 1770 1771
			dp_ctrl_read_link_status(ctrl, link_status);

			if (!drm_dp_clock_recovery_ok(link_status,
					ctrl->link->link_params.num_lanes))
				rc = dp_ctrl_link_rate_down_shift(ctrl);
			else
				rc = dp_ctrl_link_lane_down_shift(ctrl);

1772 1773 1774 1775
			if (rc < 0) {
				/* end with failure */
				break; /* lane == 1 already */
			}
1776 1777 1778

			/* stop link training before start re training  */
			dp_ctrl_clear_training_pattern(ctrl);
1779
		}
1780 1781 1782
	}

	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1783 1784
		return rc;

1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796
	if (rc == 0) {  /* link train successfully */
		/*
		 * do not stop train pattern here
		 * stop link training at on_stream
		 * to pass compliance test
		 */
	} else  {
		/*
		 * link training failed
		 * end txing train pattern here
		 */
		dp_ctrl_clear_training_pattern(ctrl);
1797

1798 1799 1800
		dp_ctrl_deinitialize_mainlink(ctrl);
		rc = -ECONNRESET;
	}
1801 1802 1803 1804

	return rc;
}

1805 1806 1807 1808 1809 1810 1811
static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
{
	int training_step = DP_TRAINING_NONE;

	return dp_ctrl_setup_main_link(ctrl, &training_step);
}

1812 1813 1814 1815 1816
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
{
	int ret = 0;
	bool mainlink_ready = false;
	struct dp_ctrl_private *ctrl;
1817
	unsigned long pixel_rate_orig;
1818 1819 1820 1821 1822 1823 1824 1825

	if (!dp_ctrl)
		return -EINVAL;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);

	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;

1826 1827 1828 1829
	pixel_rate_orig = ctrl->dp_ctrl.pixel_rate;
	if (dp_ctrl->wide_bus_en)
		ctrl->dp_ctrl.pixel_rate >>= 1;

1830
	drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841
		ctrl->link->link_params.rate,
		ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);

	if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
		ret = dp_ctrl_enable_mainlink_clocks(ctrl);
		if (ret) {
			DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
			goto end;
		}
	}

1842 1843 1844 1845 1846 1847
	if (!dp_ctrl_channel_eq_ok(ctrl))
		dp_ctrl_link_retrain(ctrl);

	/* stop txing train pattern to end link training */
	dp_ctrl_clear_training_pattern(ctrl);

1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862
	ret = dp_ctrl_enable_stream_clocks(ctrl);
	if (ret) {
		DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
		goto end;
	}

	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
		dp_ctrl_send_phy_test_pattern(ctrl);
		return 0;
	}

	/*
	 * Set up transfer unit values and set controller state to send
	 * video.
	 */
1863 1864
	reinit_completion(&ctrl->video_comp);

1865 1866 1867 1868
	dp_ctrl_configure_source_params(ctrl);

	dp_catalog_ctrl_config_msa(ctrl->catalog,
		ctrl->link->link_params.rate,
1869
		pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
1870 1871 1872 1873 1874 1875 1876 1877 1878 1879

	dp_ctrl_setup_tr_unit(ctrl);

	dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);

	ret = dp_ctrl_wait4video_ready(ctrl);
	if (ret)
		return ret;

	mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1880 1881
	drm_dbg_dp(ctrl->drm_dev,
		"mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1882 1883 1884 1885 1886

end:
	return ret;
}

1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;
	struct dp_io *dp_io;
	struct phy *phy;
	int ret;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;

	/* set dongle to D3 (power off) mode */
	dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);

1903 1904 1905 1906 1907 1908
	if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
		ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
		if (ret) {
			DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
			return ret;
		}
1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922
	}

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
	if (ret) {
		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
		return ret;
	}

	phy_power_off(phy);

	/* aux channel down, reinit phy */
	phy_exit(phy);
	phy_init(phy);

1923
	drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1924
			phy, phy->init_count, phy->power_count);
1925 1926 1927
	return ret;
}

1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956
int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;
	struct dp_io *dp_io;
	struct phy *phy;
	int ret;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
	if (ret) {
		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
	}

	DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
		phy, phy->init_count, phy->power_count);

	phy_power_off(phy);

	DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
		phy, phy->init_count, phy->power_count);

	return ret;
}

1957 1958 1959
int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;
1960 1961
	struct dp_io *dp_io;
	struct phy *phy;
1962 1963 1964 1965 1966 1967
	int ret = 0;

	if (!dp_ctrl)
		return -EINVAL;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1968 1969
	dp_io = &ctrl->parser->io;
	phy = dp_io->phy;
1970 1971

	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1972

1973
	dp_catalog_ctrl_reset(ctrl->catalog);
1974 1975 1976 1977 1978

	ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
	if (ret)
		DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);

1979 1980
	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
	if (ret) {
1981
		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1982 1983
	}

1984
	phy_power_off(phy);
1985
	drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1986
			phy, phy->init_count, phy->power_count);
1987

1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
	return ret;
}

void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
{
	struct dp_ctrl_private *ctrl;
	u32 isr;

	if (!dp_ctrl)
		return;

	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);

	isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);

	if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2004
		drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2005 2006 2007 2008
		complete(&ctrl->video_comp);
	}

	if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2009
		drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
		complete(&ctrl->idle_comp);
	}
}

struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
			struct dp_panel *panel,	struct drm_dp_aux *aux,
			struct dp_power *power, struct dp_catalog *catalog,
			struct dp_parser *parser)
{
	struct dp_ctrl_private *ctrl;
2020
	int ret;
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033

	if (!dev || !panel || !aux ||
	    !link || !catalog) {
		DRM_ERROR("invalid input\n");
		return ERR_PTR(-EINVAL);
	}

	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl) {
		DRM_ERROR("Mem allocation failure\n");
		return ERR_PTR(-ENOMEM);
	}

2034 2035
	ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
	if (ret) {
2036
		dev_err(dev, "invalid DP OPP table in device tree\n");
2037 2038
		/* caller do PTR_ERR(opp_table) */
		return (struct dp_ctrl *)ERR_PTR(ret);
2039 2040 2041
	}

	/* OPP table is optional */
2042 2043
	ret = devm_pm_opp_of_add_table(dev);
	if (ret)
2044 2045
		dev_err(dev, "failed to add DP OPP table\n");

2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
	init_completion(&ctrl->idle_comp);
	init_completion(&ctrl->video_comp);

	/* in parameters */
	ctrl->parser   = parser;
	ctrl->panel    = panel;
	ctrl->power    = power;
	ctrl->aux      = aux;
	ctrl->link     = link;
	ctrl->catalog  = catalog;
	ctrl->dev      = dev;

	return &ctrl->dp_ctrl;
}