intel_hdmi.c 94.2 KB
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/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/delay.h>
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#include <linux/hdmi.h>
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#include <linux/i2c.h>
#include <linux/slab.h>
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#include <linux/string_helpers.h>
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#include <drm/display/drm_hdcp_helper.h>
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#include <drm/display/drm_hdmi_helper.h>
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#include <drm/display/drm_scdc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
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#include <drm/intel_lpe_audio.h>
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#include "i915_debugfs.h"
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_atomic.h"
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#include "intel_connector.h"
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#include "intel_ddi.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_dp.h"
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#include "intel_gmbus.h"
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#include "intel_hdcp.h"
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#include "intel_hdcp_regs.h"
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#include "intel_hdmi.h"
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#include "intel_lspcon.h"
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#include "intel_panel.h"
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#include "intel_snps_phy.h"
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static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
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{
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	return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
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}

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static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
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	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
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	u32 enabled_bits;
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	enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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	drm_WARN(&dev_priv->drm,
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		 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
		 "HDMI port enabled, expecting disabled\n");
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}

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static void
assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
				     enum transcoder cpu_transcoder)
{
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	drm_WARN(&dev_priv->drm,
		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
		 TRANS_DDI_FUNC_ENABLE,
		 "HDMI transcoder function enabled, expecting disabled\n");
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}

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static u32 g4x_infoframe_index(unsigned int type)
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{
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	switch (type) {
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	case HDMI_PACKET_TYPE_GAMUT_METADATA:
		return VIDEO_DIP_SELECT_GAMUT;
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	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_SELECT_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_SELECT_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_SELECT_VENDOR;
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	default:
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		MISSING_CASE(type);
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		return 0;
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	}
}

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static u32 g4x_infoframe_enable(unsigned int type)
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{
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	switch (type) {
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	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
		return VIDEO_DIP_ENABLE_GCP;
	case HDMI_PACKET_TYPE_GAMUT_METADATA:
		return VIDEO_DIP_ENABLE_GAMUT;
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	case DP_SDP_VSC:
		return 0;
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	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VENDOR;
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	case HDMI_INFOFRAME_TYPE_DRM:
		return 0;
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	default:
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		MISSING_CASE(type);
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		return 0;
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	}
}

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static u32 hsw_infoframe_enable(unsigned int type)
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{
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	switch (type) {
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	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
		return VIDEO_DIP_ENABLE_GCP_HSW;
	case HDMI_PACKET_TYPE_GAMUT_METADATA:
		return VIDEO_DIP_ENABLE_GMP_HSW;
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	case DP_SDP_VSC:
		return VIDEO_DIP_ENABLE_VSC_HSW;
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	case DP_SDP_PPS:
		return VDIP_ENABLE_PPS;
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	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI_HSW;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD_HSW;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VS_HSW;
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	case HDMI_INFOFRAME_TYPE_DRM:
		return VIDEO_DIP_ENABLE_DRM_GLK;
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	default:
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		MISSING_CASE(type);
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		return 0;
	}
}

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static i915_reg_t
hsw_dip_data_reg(struct drm_i915_private *dev_priv,
		 enum transcoder cpu_transcoder,
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		 unsigned int type,
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		 int i)
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{
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	switch (type) {
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	case HDMI_PACKET_TYPE_GAMUT_METADATA:
		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
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	case DP_SDP_VSC:
		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
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	case DP_SDP_PPS:
		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
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	case HDMI_INFOFRAME_TYPE_AVI:
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		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
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	case HDMI_INFOFRAME_TYPE_VENDOR:
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		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
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	case HDMI_INFOFRAME_TYPE_DRM:
		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
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	default:
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		MISSING_CASE(type);
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		return INVALID_MMIO_REG;
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	}
}

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static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
			     unsigned int type)
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{
	switch (type) {
	case DP_SDP_VSC:
		return VIDEO_DIP_VSC_DATA_SIZE;
	case DP_SDP_PPS:
		return VIDEO_DIP_PPS_DATA_SIZE;
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	case HDMI_PACKET_TYPE_GAMUT_METADATA:
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		if (DISPLAY_VER(dev_priv) >= 11)
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			return VIDEO_DIP_GMP_DATA_SIZE;
		else
			return VIDEO_DIP_DATA_SIZE;
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	default:
		return VIDEO_DIP_DATA_SIZE;
	}
}

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static void g4x_write_infoframe(struct intel_encoder *encoder,
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				const struct intel_crtc_state *crtc_state,
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				unsigned int type,
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				const void *frame, ssize_t len)
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{
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	const u32 *data = frame;
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
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	int i;
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	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
		 "Writing DIP with CTL reg disabled\n");
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
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	for (i = 0; i < len; i += 4) {
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		intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
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		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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		intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
	intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
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}

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static void g4x_read_infoframe(struct intel_encoder *encoder,
			       const struct intel_crtc_state *crtc_state,
			       unsigned int type,
			       void *frame, ssize_t len)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	u32 val, *data = frame;
	int i;

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	val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

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	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
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	for (i = 0; i < len; i += 4)
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		*data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
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}

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static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
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				  const struct intel_crtc_state *pipe_config)
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{
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
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	if ((val & VIDEO_DIP_ENABLE) == 0)
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		return 0;
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	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
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		return 0;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
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}

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static void ibx_write_infoframe(struct intel_encoder *encoder,
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				const struct intel_crtc_state *crtc_state,
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				unsigned int type,
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				const void *frame, ssize_t len)
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{
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	const u32 *data = frame;
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
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	u32 val = intel_de_read(dev_priv, reg);
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	int i;
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	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
		 "Writing DIP with CTL reg disabled\n");
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	intel_de_write(dev_priv, reg, val);
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	for (i = 0; i < len; i += 4) {
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		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
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			       *data);
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		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
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}

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static void ibx_read_infoframe(struct intel_encoder *encoder,
			       const struct intel_crtc_state *crtc_state,
			       unsigned int type,
			       void *frame, ssize_t len)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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	u32 val, *data = frame;
	int i;

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	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

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	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
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	for (i = 0; i < len; i += 4)
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		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
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}

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static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
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				  const struct intel_crtc_state *pipe_config)
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{
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
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	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
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	u32 val = intel_de_read(dev_priv, reg);
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	if ((val & VIDEO_DIP_ENABLE) == 0)
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		return 0;
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	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
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		return 0;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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static void cpt_write_infoframe(struct intel_encoder *encoder,
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				const struct intel_crtc_state *crtc_state,
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				unsigned int type,
352
				const void *frame, ssize_t len)
353
{
354
	const u32 *data = frame;
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
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	u32 val = intel_de_read(dev_priv, reg);
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	int i;
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	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
		 "Writing DIP with CTL reg disabled\n");
363

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
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	if (type != HDMI_INFOFRAME_TYPE_AVI)
		val &= ~g4x_infoframe_enable(type);
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	intel_de_write(dev_priv, reg, val);
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	for (i = 0; i < len; i += 4) {
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		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
376
			       *data);
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		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
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}
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static void cpt_read_infoframe(struct intel_encoder *encoder,
			       const struct intel_crtc_state *crtc_state,
			       unsigned int type,
			       void *frame, ssize_t len)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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	u32 val, *data = frame;
	int i;

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	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

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	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
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	for (i = 0; i < len; i += 4)
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		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
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}

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static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
413
				  const struct intel_crtc_state *pipe_config)
414
{
415
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
416
	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
417
	u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
418

419
	if ((val & VIDEO_DIP_ENABLE) == 0)
420
		return 0;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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static void vlv_write_infoframe(struct intel_encoder *encoder,
428
				const struct intel_crtc_state *crtc_state,
429
				unsigned int type,
430
				const void *frame, ssize_t len)
431
{
432
	const u32 *data = frame;
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
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	u32 val = intel_de_read(dev_priv, reg);
437
	int i;
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	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
		 "Writing DIP with CTL reg disabled\n");
441

442
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
443
	val |= g4x_infoframe_index(type);
444

445
	val &= ~g4x_infoframe_enable(type);
446

447
	intel_de_write(dev_priv, reg, val);
448 449

	for (i = 0; i < len; i += 4) {
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		intel_de_write(dev_priv,
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			       VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
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		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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		intel_de_write(dev_priv,
457
			       VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
458

459
	val |= g4x_infoframe_enable(type);
460
	val &= ~VIDEO_DIP_FREQ_MASK;
461
	val |= VIDEO_DIP_FREQ_VSYNC;
462

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	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
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}

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static void vlv_read_infoframe(struct intel_encoder *encoder,
			       const struct intel_crtc_state *crtc_state,
			       unsigned int type,
			       void *frame, ssize_t len)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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	u32 val, *data = frame;
	int i;

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	val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

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	intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
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	for (i = 0; i < len; i += 4)
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		*data++ = intel_de_read(dev_priv,
				        VLV_TVIDEO_DIP_DATA(crtc->pipe));
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}

489
static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
490
				  const struct intel_crtc_state *pipe_config)
491
{
492
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
493
	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
494
	u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
495

496
	if ((val & VIDEO_DIP_ENABLE) == 0)
497
		return 0;
498

499
	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
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		return 0;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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void hsw_write_infoframe(struct intel_encoder *encoder,
			 const struct intel_crtc_state *crtc_state,
			 unsigned int type,
			 const void *frame, ssize_t len)
511
{
512
	const u32 *data = frame;
513
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
514
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
515
	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
516
	int data_size;
517
	int i;
518
	u32 val = intel_de_read(dev_priv, ctl_reg);
519

520 521
	data_size = hsw_dip_data_size(dev_priv, type);

522
	drm_WARN_ON(&dev_priv->drm, len > data_size);
523

524
	val &= ~hsw_infoframe_enable(type);
525
	intel_de_write(dev_priv, ctl_reg, val);
526 527

	for (i = 0; i < len; i += 4) {
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		intel_de_write(dev_priv,
			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
			       *data);
531 532
		data++;
	}
533
	/* Write every possible data byte to force correct ECC calculation. */
534
	for (; i < data_size; i += 4)
535 536 537
		intel_de_write(dev_priv,
			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
			       0);
538

539 540 541 542 543
	/* Wa_14013475917 */
	if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
	    type == DP_SDP_VSC)
		return;

544
	val |= hsw_infoframe_enable(type);
545 546
	intel_de_write(dev_priv, ctl_reg, val);
	intel_de_posting_read(dev_priv, ctl_reg);
547 548
}

549 550 551
void hsw_read_infoframe(struct intel_encoder *encoder,
			const struct intel_crtc_state *crtc_state,
			unsigned int type, void *frame, ssize_t len)
552 553 554
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
555
	u32 *data = frame;
556 557 558
	int i;

	for (i = 0; i < len; i += 4)
559 560
		*data++ = intel_de_read(dev_priv,
				        hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
561 562
}

563
static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
564
				  const struct intel_crtc_state *pipe_config)
565
{
566
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 568
	u32 val = intel_de_read(dev_priv,
				HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 570 571 572 573 574
	u32 mask;

	mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);

575
	if (DISPLAY_VER(dev_priv) >= 10)
576
		mask |= VIDEO_DIP_ENABLE_DRM_GLK;
577

578
	return val & mask;
579 580
}

581 582 583 584 585 586 587
static const u8 infoframe_type_to_idx[] = {
	HDMI_PACKET_TYPE_GENERAL_CONTROL,
	HDMI_PACKET_TYPE_GAMUT_METADATA,
	DP_SDP_VSC,
	HDMI_INFOFRAME_TYPE_AVI,
	HDMI_INFOFRAME_TYPE_SPD,
	HDMI_INFOFRAME_TYPE_VENDOR,
588
	HDMI_INFOFRAME_TYPE_DRM,
589 590
};

591 592 593 594 595 596 597 598 599 600 601 602
u32 intel_hdmi_infoframe_enable(unsigned int type)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
		if (infoframe_type_to_idx[i] == type)
			return BIT(i);
	}

	return 0;
}

603 604 605 606
u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
				  const struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
607
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628
	u32 val, ret = 0;
	int i;

	val = dig_port->infoframes_enabled(encoder, crtc_state);

	/* map from hardware bits to dip idx */
	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
		unsigned int type = infoframe_type_to_idx[i];

		if (HAS_DDI(dev_priv)) {
			if (val & hsw_infoframe_enable(type))
				ret |= BIT(i);
		} else {
			if (val & g4x_infoframe_enable(type))
				ret |= BIT(i);
		}
	}

	return ret;
}

629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645
/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */
646
static void intel_write_infoframe(struct intel_encoder *encoder,
647
				  const struct intel_crtc_state *crtc_state,
648 649
				  enum hdmi_infoframe_type type,
				  const union hdmi_infoframe *frame)
650
{
651
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
652
	u8 buffer[VIDEO_DIP_DATA_SIZE];
653
	ssize_t len;
654

655 656 657 658
	if ((crtc_state->infoframes.enable &
	     intel_hdmi_infoframe_enable(type)) == 0)
		return;

659
	if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
660 661
		return;

662
	/* see comment above for the reason for this offset */
663
	len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
664
	if (drm_WARN_ON(encoder->base.dev, len < 0))
665 666 667
		return;

	/* Insert the 'hole' (see big comment above) at position 3 */
668
	memmove(&buffer[0], &buffer[1], 3);
669 670
	buffer[3] = 0;
	len++;
671

672
	dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673 674
}

675 676 677 678 679
void intel_read_infoframe(struct intel_encoder *encoder,
			  const struct intel_crtc_state *crtc_state,
			  enum hdmi_infoframe_type type,
			  union hdmi_infoframe *frame)
{
680
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
681 682 683 684 685 686 687
	u8 buffer[VIDEO_DIP_DATA_SIZE];
	int ret;

	if ((crtc_state->infoframes.enable &
	     intel_hdmi_infoframe_enable(type)) == 0)
		return;

688
	dig_port->read_infoframe(encoder, crtc_state,
689 690 691 692 693 694 695 696
				       type, buffer, sizeof(buffer));

	/* Fill the 'hole' (see big comment above) at position 3 */
	memmove(&buffer[1], &buffer[0], 3);

	/* see comment above for the reason for this offset */
	ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
	if (ret) {
697
		drm_dbg_kms(encoder->base.dev,
698
			    "Failed to unpack infoframe type 0x%02x\n", type);
699 700 701 702
		return;
	}

	if (frame->any.type != type)
703
		drm_dbg_kms(encoder->base.dev,
704 705
			    "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
			    frame->any.type, type);
706 707
}

708 709 710 711
static bool
intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
				 struct intel_crtc_state *crtc_state,
				 struct drm_connector_state *conn_state)
712
{
713
	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
714
	const struct drm_display_mode *adjusted_mode =
715
		&crtc_state->hw.adjusted_mode;
716
	struct drm_connector *connector = conn_state->connector;
717
	int ret;
718

719 720 721 722 723 724 725
	if (!crtc_state->has_infoframe)
		return true;

	crtc_state->infoframes.enable |=
		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);

	ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726
						       adjusted_mode);
727 728
	if (ret)
		return false;
729

730
	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
731
		frame->colorspace = HDMI_COLORSPACE_YUV420;
732
	else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
733
		frame->colorspace = HDMI_COLORSPACE_YUV444;
734
	else
735
		frame->colorspace = HDMI_COLORSPACE_RGB;
736

737
	drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
738

739
	/* nonsense combination */
740 741
	drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
742

743 744 745 746 747 748 749 750 751 752
	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
		drm_hdmi_avi_infoframe_quant_range(frame, connector,
						   adjusted_mode,
						   crtc_state->limited_color_range ?
						   HDMI_QUANTIZATION_RANGE_LIMITED :
						   HDMI_QUANTIZATION_RANGE_FULL);
	} else {
		frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
		frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
	}
753

754
	drm_hdmi_avi_infoframe_content_type(frame, conn_state);
755

756
	/* TODO: handle pixel repetition for YCBCR420 outputs */
757 758

	ret = hdmi_avi_infoframe_check(frame);
759
	if (drm_WARN_ON(encoder->base.dev, ret))
760 761 762
		return false;

	return true;
763 764
}

765 766 767 768
static bool
intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
				 struct intel_crtc_state *crtc_state,
				 struct drm_connector_state *conn_state)
769
{
770
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
771
	struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
772 773
	int ret;

774 775
	if (!crtc_state->has_infoframe)
		return true;
776

777 778
	crtc_state->infoframes.enable |=
		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
779

780 781 782 783 784
	if (IS_DGFX(i915))
		ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
	else
		ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");

785
	if (drm_WARN_ON(encoder->base.dev, ret))
786 787 788 789 790
		return false;

	frame->sdi = HDMI_SPD_SDI_PC;

	ret = hdmi_spd_infoframe_check(frame);
791
	if (drm_WARN_ON(encoder->base.dev, ret))
792 793 794
		return false;

	return true;
795 796
}

797 798 799 800 801 802 803 804 805
static bool
intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
				  struct intel_crtc_state *crtc_state,
				  struct drm_connector_state *conn_state)
{
	struct hdmi_vendor_infoframe *frame =
		&crtc_state->infoframes.hdmi.vendor.hdmi;
	const struct drm_display_info *info =
		&conn_state->connector->display_info;
806 807
	int ret;

808 809 810 811 812 813 814
	if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
		return true;

	crtc_state->infoframes.enable |=
		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);

	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
815
							  conn_state->connector,
816
							  &crtc_state->hw.adjusted_mode);
817
	if (drm_WARN_ON(encoder->base.dev, ret))
818
		return false;
819

820
	ret = hdmi_vendor_infoframe_check(frame);
821
	if (drm_WARN_ON(encoder->base.dev, ret))
822 823 824
		return false;

	return true;
825 826
}

827 828 829 830 831 832 833 834 835
static bool
intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
				 struct intel_crtc_state *crtc_state,
				 struct drm_connector_state *conn_state)
{
	struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int ret;

836
	if (DISPLAY_VER(dev_priv) < 10)
837 838 839 840 841 842 843 844 845 846 847 848 849
		return true;

	if (!crtc_state->has_infoframe)
		return true;

	if (!conn_state->hdr_output_metadata)
		return true;

	crtc_state->infoframes.enable |=
		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);

	ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
	if (ret < 0) {
850 851
		drm_dbg_kms(&dev_priv->drm,
			    "couldn't set HDR metadata in infoframe\n");
852 853 854 855
		return false;
	}

	ret = hdmi_drm_infoframe_check(frame);
856
	if (drm_WARN_ON(&dev_priv->drm, ret))
857 858 859 860 861
		return false;

	return true;
}

862
static void g4x_set_infoframes(struct intel_encoder *encoder,
863
			       bool enable,
864 865
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state)
866
{
867
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
868 869
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
870
	i915_reg_t reg = VIDEO_DIP_CTL;
871
	u32 val = intel_de_read(dev_priv, reg);
872
	u32 port = VIDEO_DIP_PORT(encoder->port);
873

874 875
	assert_hdmi_port_disabled(intel_hdmi);

876 877 878 879 880 881 882 883 884 885 886
	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

887
	if (!enable) {
888 889
		if (!(val & VIDEO_DIP_ENABLE))
			return;
890
		if (port != (val & VIDEO_DIP_PORT_MASK)) {
891 892 893
			drm_dbg_kms(&dev_priv->drm,
				    "video DIP still enabled on port %c\n",
				    (val & VIDEO_DIP_PORT_MASK) >> 29);
894 895 896 897
			return;
		}
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
898 899
		intel_de_write(dev_priv, reg, val);
		intel_de_posting_read(dev_priv, reg);
900 901 902
		return;
	}

903 904
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
905 906 907
			drm_dbg_kms(&dev_priv->drm,
				    "video DIP already enabled on port %c\n",
				    (val & VIDEO_DIP_PORT_MASK) >> 29);
908
			return;
909 910 911 912 913
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

914
	val |= VIDEO_DIP_ENABLE;
915 916
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
917

918 919
	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
920

921 922 923 924 925 926 927 928 929
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_AVI,
			      &crtc_state->infoframes.avi);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_SPD,
			      &crtc_state->infoframes.spd);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_VENDOR,
			      &crtc_state->infoframes.hdmi);
930 931
}

932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974
/*
 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 *
 * From HDMI specification 1.4a:
 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 *   phase of 0
 */
static bool gcp_default_phase_possible(int pipe_bpp,
				       const struct drm_display_mode *mode)
{
	unsigned int pixels_per_group;

	switch (pipe_bpp) {
	case 30:
		/* 4 pixels in 5 clocks */
		pixels_per_group = 4;
		break;
	case 36:
		/* 2 pixels in 3 clocks */
		pixels_per_group = 2;
		break;
	case 48:
		/* 1 pixel in 2 clocks */
		pixels_per_group = 1;
		break;
	default:
		/* phase information not relevant for 8bpc */
		return false;
	}

	return mode->crtc_hdisplay % pixels_per_group == 0 &&
		mode->crtc_htotal % pixels_per_group == 0 &&
		mode->crtc_hblank_start % pixels_per_group == 0 &&
		mode->crtc_hblank_end % pixels_per_group == 0 &&
		mode->crtc_hsync_start % pixels_per_group == 0 &&
		mode->crtc_hsync_end % pixels_per_group == 0 &&
		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
		 mode->crtc_htotal/2 % pixels_per_group == 0);
}

975
static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
976 977
					 const struct intel_crtc_state *crtc_state,
					 const struct drm_connector_state *conn_state)
978
{
979
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
980
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
981
	i915_reg_t reg;
982 983 984 985

	if ((crtc_state->infoframes.enable &
	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
		return false;
986 987

	if (HAS_DDI(dev_priv))
988
		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
989
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
990
		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
991
	else if (HAS_PCH_SPLIT(dev_priv))
992 993 994 995
		reg = TVIDEO_DIP_GCP(crtc->pipe);
	else
		return false;

996
	intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
997 998 999 1000

	return true;
}

1001 1002 1003 1004
void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
				   struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
	i915_reg_t reg;

	if ((crtc_state->infoframes.enable &
	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
		return;

	if (HAS_DDI(dev_priv))
		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
	else if (HAS_PCH_SPLIT(dev_priv))
		reg = TVIDEO_DIP_GCP(crtc->pipe);
	else
		return;

1021
	crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1022 1023
}

1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
					     struct intel_crtc_state *crtc_state,
					     struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
		return;

	crtc_state->infoframes.enable |=
		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);

1036 1037
	/* Indicate color indication for deep color mode */
	if (crtc_state->pipe_bpp > 24)
1038
		crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1039

1040
	/* Enable default_phase whenever the display mode is suitably aligned */
1041
	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1042
				       &crtc_state->hw.adjusted_mode))
1043
		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1044 1045
}

1046
static void ibx_set_infoframes(struct intel_encoder *encoder,
1047
			       bool enable,
1048 1049
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state)
1050
{
1051
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1052
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1053 1054
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1055
	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1056
	u32 val = intel_de_read(dev_priv, reg);
1057
	u32 port = VIDEO_DIP_PORT(encoder->port);
1058

1059 1060
	assert_hdmi_port_disabled(intel_hdmi);

1061 1062 1063
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

1064
	if (!enable) {
1065 1066
		if (!(val & VIDEO_DIP_ENABLE))
			return;
1067 1068 1069
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1070 1071
		intel_de_write(dev_priv, reg, val);
		intel_de_posting_read(dev_priv, reg);
1072 1073 1074
		return;
	}

1075
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1076 1077 1078
		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
			 "DIP already enabled on port %c\n",
			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1079 1080 1081 1082
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

1083
	val |= VIDEO_DIP_ENABLE;
1084 1085 1086
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1087

1088
	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1089 1090
		val |= VIDEO_DIP_ENABLE_GCP;

1091 1092
	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
1093

1094 1095 1096 1097 1098 1099 1100 1101 1102
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_AVI,
			      &crtc_state->infoframes.avi);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_SPD,
			      &crtc_state->infoframes.spd);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_VENDOR,
			      &crtc_state->infoframes.hdmi);
1103 1104
}

1105
static void cpt_set_infoframes(struct intel_encoder *encoder,
1106
			       bool enable,
1107 1108
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state)
1109
{
1110
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1111
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1112
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1113
	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1114
	u32 val = intel_de_read(dev_priv, reg);
1115

1116 1117
	assert_hdmi_port_disabled(intel_hdmi);

1118 1119 1120
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

1121
	if (!enable) {
1122 1123
		if (!(val & VIDEO_DIP_ENABLE))
			return;
1124 1125 1126
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1127 1128
		intel_de_write(dev_priv, reg, val);
		intel_de_posting_read(dev_priv, reg);
1129 1130 1131
		return;
	}

1132 1133
	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1134
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1135
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1136

1137
	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1138 1139
		val |= VIDEO_DIP_ENABLE_GCP;

1140 1141
	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
1142

1143 1144 1145 1146 1147 1148 1149 1150 1151
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_AVI,
			      &crtc_state->infoframes.avi);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_SPD,
			      &crtc_state->infoframes.spd);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_VENDOR,
			      &crtc_state->infoframes.hdmi);
1152 1153
}

1154
static void vlv_set_infoframes(struct intel_encoder *encoder,
1155
			       bool enable,
1156 1157
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state)
1158
{
1159
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1160
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1161
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1162
	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1163
	u32 val = intel_de_read(dev_priv, reg);
1164
	u32 port = VIDEO_DIP_PORT(encoder->port);
1165

1166 1167
	assert_hdmi_port_disabled(intel_hdmi);

1168 1169 1170
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

1171
	if (!enable) {
1172 1173
		if (!(val & VIDEO_DIP_ENABLE))
			return;
1174 1175 1176
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1177 1178
		intel_de_write(dev_priv, reg, val);
		intel_de_posting_read(dev_priv, reg);
1179 1180 1181
		return;
	}

1182
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1183 1184 1185
		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
			 "DIP already enabled on port %c\n",
			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1186 1187 1188 1189
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

1190
	val |= VIDEO_DIP_ENABLE;
1191 1192 1193
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1194

1195
	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1196 1197
		val |= VIDEO_DIP_ENABLE_GCP;

1198 1199
	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
1200

1201 1202 1203 1204 1205 1206 1207 1208 1209
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_AVI,
			      &crtc_state->infoframes.avi);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_SPD,
			      &crtc_state->infoframes.spd);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_VENDOR,
			      &crtc_state->infoframes.hdmi);
1210 1211
}

1212
static void hsw_set_infoframes(struct intel_encoder *encoder,
1213
			       bool enable,
1214 1215
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state)
1216
{
1217
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1218
	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1219
	u32 val = intel_de_read(dev_priv, reg);
1220

1221 1222
	assert_hdmi_transcoder_func_disabled(dev_priv,
					     crtc_state->cpu_transcoder);
1223

1224 1225
	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1226 1227
		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
		 VIDEO_DIP_ENABLE_DRM_GLK);
1228

1229
	if (!enable) {
1230 1231
		intel_de_write(dev_priv, reg, val);
		intel_de_posting_read(dev_priv, reg);
1232 1233 1234
		return;
	}

1235
	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1236 1237
		val |= VIDEO_DIP_ENABLE_GCP_HSW;

1238 1239
	intel_de_write(dev_priv, reg, val);
	intel_de_posting_read(dev_priv, reg);
1240

1241 1242 1243 1244 1245 1246 1247 1248 1249
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_AVI,
			      &crtc_state->infoframes.avi);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_SPD,
			      &crtc_state->infoframes.spd);
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_VENDOR,
			      &crtc_state->infoframes.hdmi);
1250 1251 1252
	intel_write_infoframe(encoder, crtc_state,
			      HDMI_INFOFRAME_TYPE_DRM,
			      &crtc_state->infoframes.drm);
1253 1254
}

1255 1256
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
{
1257
	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1258
	struct i2c_adapter *adapter;
1259 1260 1261 1262

	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
		return;

1263 1264
	adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);

1265 1266
	drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
		    enable ? "Enabling" : "Disabling");
1267

1268
	drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1269 1270
}

1271
static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1272 1273
				unsigned int offset, void *buffer, size_t size)
{
1274 1275
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_hdmi *hdmi = &dig_port->hdmi;
1276
	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299
							      hdmi->ddc_bus);
	int ret;
	u8 start = offset & 0xff;
	struct i2c_msg msgs[] = {
		{
			.addr = DRM_HDCP_DDC_ADDR,
			.flags = 0,
			.len = 1,
			.buf = &start,
		},
		{
			.addr = DRM_HDCP_DDC_ADDR,
			.flags = I2C_M_RD,
			.len = size,
			.buf = buffer
		}
	};
	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
	if (ret == ARRAY_SIZE(msgs))
		return 0;
	return ret >= 0 ? -EIO : ret;
}

1300
static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1301 1302
				 unsigned int offset, void *buffer, size_t size)
{
1303 1304
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_hdmi *hdmi = &dig_port->hdmi;
1305
	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
							      hdmi->ddc_bus);
	int ret;
	u8 *write_buf;
	struct i2c_msg msg;

	write_buf = kzalloc(size + 1, GFP_KERNEL);
	if (!write_buf)
		return -ENOMEM;

	write_buf[0] = offset & 0xff;
	memcpy(&write_buf[1], buffer, size);

	msg.addr = DRM_HDCP_DDC_ADDR;
	msg.flags = 0,
	msg.len = size + 1,
	msg.buf = write_buf;

	ret = i2c_transfer(adapter, &msg, 1);
	if (ret == 1)
1325 1326 1327 1328 1329 1330
		ret = 0;
	else if (ret >= 0)
		ret = -EIO;

	kfree(write_buf);
	return ret;
1331 1332 1333
}

static
1334
int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1335 1336
				  u8 *an)
{
1337 1338
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_hdmi *hdmi = &dig_port->hdmi;
1339
	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1340 1341 1342
							      hdmi->ddc_bus);
	int ret;

1343
	ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1344 1345
				    DRM_HDCP_AN_LEN);
	if (ret) {
1346 1347
		drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
			    ret);
1348 1349 1350 1351 1352
		return ret;
	}

	ret = intel_gmbus_output_aksv(adapter);
	if (ret < 0) {
1353
		drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1354 1355 1356 1357 1358
		return ret;
	}
	return 0;
}

1359
static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1360 1361
				     u8 *bksv)
{
1362
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1363

1364
	int ret;
1365
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1366 1367
				   DRM_HDCP_KSV_LEN);
	if (ret)
1368 1369
		drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
			    ret);
1370 1371 1372 1373
	return ret;
}

static
1374
int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1375 1376
				 u8 *bstatus)
{
1377
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1378

1379
	int ret;
1380
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1381 1382
				   bstatus, DRM_HDCP_BSTATUS_LEN);
	if (ret)
1383 1384
		drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
			    ret);
1385 1386 1387 1388
	return ret;
}

static
1389
int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1390 1391
				     bool *repeater_present)
{
1392
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1393 1394 1395
	int ret;
	u8 val;

1396
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1397
	if (ret) {
1398 1399
		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
			    ret);
1400 1401 1402 1403 1404 1405 1406
		return ret;
	}
	*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
	return 0;
}

static
1407
int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1408 1409
				  u8 *ri_prime)
{
1410
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1411

1412
	int ret;
1413
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1414 1415
				   ri_prime, DRM_HDCP_RI_LEN);
	if (ret)
1416 1417
		drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
			    ret);
1418 1419 1420 1421
	return ret;
}

static
1422
int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1423 1424
				   bool *ksv_ready)
{
1425
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1426 1427 1428
	int ret;
	u8 val;

1429
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1430
	if (ret) {
1431 1432
		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
			    ret);
1433 1434 1435 1436 1437 1438 1439
		return ret;
	}
	*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
	return 0;
}

static
1440
int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1441 1442
				  int num_downstream, u8 *ksv_fifo)
{
1443
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1444
	int ret;
1445
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1446 1447
				   ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
	if (ret) {
1448 1449
		drm_dbg_kms(&i915->drm,
			    "Read ksv fifo over DDC failed (%d)\n", ret);
1450 1451 1452 1453 1454 1455
		return ret;
	}
	return 0;
}

static
1456
int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1457 1458
				      int i, u32 *part)
{
1459
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1460 1461 1462 1463 1464
	int ret;

	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
		return -EINVAL;

1465
	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1466 1467
				   part, DRM_HDCP_V_PRIME_PART_LEN);
	if (ret)
1468 1469
		drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
			    i, ret);
1470 1471 1472
	return ret;
}

1473 1474
static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
					   enum transcoder cpu_transcoder)
1475 1476
{
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1477
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1478
	struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1479 1480 1481 1482
	u32 scanline;
	int ret;

	for (;;) {
1483
		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1484 1485 1486 1487 1488
		if (scanline > 100 && scanline < 200)
			break;
		usleep_range(25, 50);
	}

1489 1490
	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
					 false, TRANS_DDI_HDCP_SIGNALLING);
1491
	if (ret) {
1492 1493
		drm_err(&dev_priv->drm,
			"Disable HDCP signalling failed (%d)\n", ret);
1494 1495
		return ret;
	}
1496 1497 1498

	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
					 true, TRANS_DDI_HDCP_SIGNALLING);
1499
	if (ret) {
1500 1501
		drm_err(&dev_priv->drm,
			"Enable HDCP signalling failed (%d)\n", ret);
1502 1503 1504 1505 1506 1507
		return ret;
	}

	return 0;
}

1508
static
1509
int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1510
				      enum transcoder cpu_transcoder,
1511 1512
				      bool enable)
{
1513
	struct intel_hdmi *hdmi = &dig_port->hdmi;
1514 1515
	struct intel_connector *connector = hdmi->attached_connector;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1516 1517 1518 1519 1520
	int ret;

	if (!enable)
		usleep_range(6, 60); /* Bspec says >= 6us */

1521 1522 1523
	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
					 cpu_transcoder, enable,
					 TRANS_DDI_HDCP_SIGNALLING);
1524
	if (ret) {
1525 1526
		drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
			enable ? "Enable" : "Disable", ret);
1527 1528
		return ret;
	}
1529 1530 1531 1532 1533 1534

	/*
	 * WA: To fix incorrect positioning of the window of
	 * opportunity and enc_en signalling in KABYLAKE.
	 */
	if (IS_KABYLAKE(dev_priv) && enable)
1535 1536
		return kbl_repositioning_enc_en_signal(connector,
						       cpu_transcoder);
1537

1538 1539 1540 1541
	return 0;
}

static
1542 1543
bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
				     struct intel_connector *connector)
1544
{
1545 1546
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;
1547
	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1548 1549 1550 1551 1552 1553
	int ret;
	union {
		u32 reg;
		u8 shim[DRM_HDCP_RI_LEN];
	} ri;

1554
	ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1555 1556 1557
	if (ret)
		return false;

1558
	intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1559 1560

	/* Wait for Ri prime match */
1561 1562
	if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
		      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1563
		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1564
		drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1565 1566
			intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
							port)));
1567 1568 1569 1570 1571
		return false;
	}
	return true;
}

1572
static
1573 1574
bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
				struct intel_connector *connector)
1575
{
1576
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1577 1578 1579
	int retry;

	for (retry = 0; retry < 3; retry++)
1580
		if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1581 1582 1583 1584 1585 1586
			return true;

	drm_err(&i915->drm, "Link check failed\n");
	return false;
}

1587
struct hdcp2_hdmi_msg_timeout {
1588
	u8 msg_id;
1589
	u16 timeout;
1590 1591
};

1592
static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1593 1594 1595 1596 1597
	{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
	{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
	{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
	{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
	{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1598
};
1599 1600

static
1601
int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1602
				    u8 *rx_status)
1603
{
1604
	return intel_hdmi_hdcp_read(dig_port,
1605 1606 1607 1608 1609 1610 1611 1612 1613
				    HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
				    rx_status,
				    HDCP_2_2_HDMI_RXSTATUS_LEN);
}

static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
{
	int i;

1614 1615 1616 1617 1618 1619 1620 1621 1622
	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
		if (is_paired)
			return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
		else
			return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
	}

	for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
		if (hdcp2_msg_timeout[i].msg_id == msg_id)
1623
			return hdcp2_msg_timeout[i].timeout;
1624
	}
1625 1626 1627 1628

	return -EINVAL;
}

1629
static int
1630
hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1631 1632
			      u8 msg_id, bool *msg_ready,
			      ssize_t *msg_sz)
1633
{
1634
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1635 1636 1637
	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
	int ret;

1638
	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1639
	if (ret < 0) {
1640 1641
		drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
			    ret);
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657
		return ret;
	}

	*msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
		  rx_status[0]);

	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
		*msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
			     *msg_sz);
	else
		*msg_ready = *msg_sz;

	return 0;
}

static ssize_t
1658
intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1659 1660
			      u8 msg_id, bool paired)
{
1661
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1662 1663 1664 1665 1666 1667 1668 1669
	bool msg_ready = false;
	int timeout, ret;
	ssize_t msg_sz = 0;

	timeout = get_hdcp2_msg_timeout(msg_id, paired);
	if (timeout < 0)
		return timeout;

1670
	ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1671 1672 1673 1674 1675
							     msg_id, &msg_ready,
							     &msg_sz),
			 !ret && msg_ready && msg_sz, timeout * 1000,
			 1000, 5 * 1000);
	if (ret)
1676 1677
		drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
			    msg_id, ret, timeout);
1678 1679 1680 1681 1682

	return ret ? ret : msg_sz;
}

static
1683
int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1684 1685 1686 1687 1688
			       void *buf, size_t size)
{
	unsigned int offset;

	offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1689
	return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1690 1691 1692
}

static
1693
int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1694 1695
			      u8 msg_id, void *buf, size_t size)
{
1696 1697
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_hdmi *hdmi = &dig_port->hdmi;
1698 1699 1700 1701
	struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
	unsigned int offset;
	ssize_t ret;

1702
	ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1703 1704 1705 1706 1707 1708 1709 1710 1711
					    hdcp->is_paired);
	if (ret < 0)
		return ret;

	/*
	 * Available msg size should be equal to or lesser than the
	 * available buffer.
	 */
	if (ret > size) {
1712 1713 1714
		drm_dbg_kms(&i915->drm,
			    "msg_sz(%zd) is more than exp size(%zu)\n",
			    ret, size);
1715
		return -EINVAL;
1716 1717 1718
	}

	offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1719
	ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1720
	if (ret)
1721 1722
		drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
			    msg_id, ret);
1723 1724 1725 1726 1727

	return ret;
}

static
1728 1729
int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
				struct intel_connector *connector)
1730 1731 1732 1733
{
	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
	int ret;

1734
	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
	if (ret)
		return ret;

	/*
	 * Re-auth request and Link Integrity Failures are represented by
	 * same bit. i.e reauth_req.
	 */
	if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
		ret = HDCP_REAUTH_REQUEST;
	else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
		ret = HDCP_TOPOLOGY_CHANGE;

	return ret;
}

static
1751
int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1752 1753 1754 1755 1756 1757
			     bool *capable)
{
	u8 hdcp2_version;
	int ret;

	*capable = false;
1758
	ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1759 1760 1761 1762 1763 1764 1765
				   &hdcp2_version, sizeof(hdcp2_version));
	if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
		*capable = true;

	return ret;
}

1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776
static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
	.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
	.read_bksv = intel_hdmi_hdcp_read_bksv,
	.read_bstatus = intel_hdmi_hdcp_read_bstatus,
	.repeater_present = intel_hdmi_hdcp_repeater_present,
	.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
	.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
	.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
	.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
	.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
	.check_link = intel_hdmi_hdcp_check_link,
1777 1778 1779 1780 1781
	.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
	.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
	.check_2_2_link	= intel_hdmi_hdcp2_check_link,
	.hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
	.protocol = HDCP_PROTOCOL_HDMI,
1782 1783
};

1784
static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1785
{
1786
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1787
	int max_tmds_clock, vbt_max_tmds_clock;
1788

1789
	if (DISPLAY_VER(dev_priv) >= 10)
1790
		max_tmds_clock = 594000;
1791
	else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1792
		max_tmds_clock = 300000;
1793
	else if (DISPLAY_VER(dev_priv) >= 5)
1794
		max_tmds_clock = 225000;
1795
	else
1796 1797
		max_tmds_clock = 165000;

1798 1799 1800
	vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
	if (vbt_max_tmds_clock)
		max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1801 1802

	return max_tmds_clock;
1803 1804
}

1805 1806 1807 1808 1809 1810 1811
static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
				const struct drm_connector_state *conn_state)
{
	return hdmi->has_hdmi_sink &&
		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
}

1812 1813 1814 1815 1816
static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
{
	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
}

1817
static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1818
				 bool respect_downstream_limits,
1819
				 bool has_hdmi_sink)
1820
{
1821 1822
	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1823 1824

	if (respect_downstream_limits) {
1825 1826 1827
		struct intel_connector *connector = hdmi->attached_connector;
		const struct drm_display_info *info = &connector->base.display_info;

1828 1829 1830
		if (hdmi->dp_dual_mode.max_tmds_clock)
			max_tmds_clock = min(max_tmds_clock,
					     hdmi->dp_dual_mode.max_tmds_clock);
1831 1832 1833 1834

		if (info->max_tmds_clock)
			max_tmds_clock = min(max_tmds_clock,
					     info->max_tmds_clock);
1835
		else if (!has_hdmi_sink)
1836 1837 1838 1839 1840 1841
			max_tmds_clock = min(max_tmds_clock, 165000);
	}

	return max_tmds_clock;
}

1842 1843
static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1844
		      int clock, bool respect_downstream_limits,
1845
		      bool has_hdmi_sink)
1846
{
1847
	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1848
	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1849 1850 1851

	if (clock < 25000)
		return MODE_CLOCK_LOW;
1852 1853
	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
					  has_hdmi_sink))
1854 1855
		return MODE_CLOCK_HIGH;

1856 1857 1858 1859 1860
	/* GLK DPLL can't generate 446-480 MHz */
	if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
		return MODE_CLOCK_RANGE;

	/* BXT/GLK DPLL can't generate 223-240 MHz */
1861 1862
	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
	    clock > 223333 && clock < 240000)
1863 1864 1865
		return MODE_CLOCK_RANGE;

	/* CHV DPLL can't generate 216-240 MHz */
1866
	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1867 1868
		return MODE_CLOCK_RANGE;

1869 1870 1871 1872 1873 1874 1875 1876
	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
		return MODE_CLOCK_RANGE;

	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
		return MODE_CLOCK_RANGE;

1877 1878 1879 1880 1881 1882 1883 1884 1885 1886
	/*
	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
	 * set of link rates.
	 *
	 * FIXME: We will hopefully get an algorithmic way of programming
	 * the MPLLB for HDMI in the future.
	 */
	if (IS_DG2(dev_priv))
		return intel_snps_phy_check_hdmi_link_rate(clock);

1887 1888 1889
	return MODE_OK;
}

1890
int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1891
{
1892 1893 1894 1895
	/* YCBCR420 TMDS rate requirement is half the pixel clock */
	if (ycbcr420_output)
		clock /= 2;

1896 1897 1898 1899 1900
	/*
	 * Need to adjust the port link by:
	 *  1.5x for 12bpc
	 *  1.25x for 10bpc
	 */
1901
	return DIV_ROUND_CLOSEST(clock * bpc, 8);
1902 1903
}

1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920
static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
{
	switch (bpc) {
	case 12:
		return !HAS_GMCH(i915);
	case 10:
		return DISPLAY_VER(i915) >= 11;
	case 8:
		return true;
	default:
		MISSING_CASE(bpc);
		return false;
	}
}

static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
					 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1921 1922 1923 1924 1925 1926
{
	const struct drm_display_info *info = &connector->display_info;
	const struct drm_hdmi_info *hdmi = &info->hdmi;

	switch (bpc) {
	case 12:
1927 1928 1929
		if (!has_hdmi_sink)
			return false;

1930 1931 1932
		if (ycbcr420_output)
			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
		else
1933
			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1934
	case 10:
1935 1936 1937
		if (!has_hdmi_sink)
			return false;

1938 1939 1940
		if (ycbcr420_output)
			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
		else
1941
			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1942 1943 1944 1945 1946 1947 1948 1949
	case 8:
		return true;
	default:
		MISSING_CASE(bpc);
		return false;
	}
}

1950
static enum drm_mode_status
1951 1952
intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
			    bool has_hdmi_sink, bool ycbcr420_output)
1953
{
1954
	struct drm_i915_private *i915 = to_i915(connector->dev);
1955
	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976
	enum drm_mode_status status = MODE_OK;
	int bpc;

	/*
	 * Try all color depths since valid port clock range
	 * can have holes. Any mode that can be used with at
	 * least one color depth is accepted.
	 */
	for (bpc = 12; bpc >= 8; bpc -= 2) {
		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);

		if (!intel_hdmi_source_bpc_possible(i915, bpc))
			continue;

		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
			continue;

		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
		if (status == MODE_OK)
			return MODE_OK;
	}
1977

1978 1979
	/* can never happen */
	drm_WARN_ON(&i915->drm, status == MODE_OK);
1980 1981 1982 1983

	return status;
}

1984 1985 1986
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
		      struct drm_display_mode *mode)
1987
{
1988
	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1989
	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1990
	enum drm_mode_status status;
1991
	int clock = mode->clock;
1992
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1993
	bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1994
	bool ycbcr_420_only;
1995

1996 1997 1998
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

1999 2000 2001 2002 2003 2004
	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
		clock *= 2;

	if (clock > max_dotclk)
		return MODE_CLOCK_HIGH;

2005 2006 2007
	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
		if (!has_hdmi_sink)
			return MODE_CLOCK_LOW;
2008
		clock *= 2;
2009
	}
2010

2011 2012 2013 2014 2015 2016 2017 2018 2019
	/*
	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
	 * enumerated only if FRL is supported. Current platforms do not support
	 * FRL so prune the higher resolution modes that require doctclock more
	 * than 600MHz.
	 */
	if (clock > 600000)
		return MODE_CLOCK_HIGH;

2020
	ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2021

2022
	status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2023 2024 2025 2026 2027
	if (status != MODE_OK) {
		if (ycbcr_420_only ||
		    !connector->ycbcr_420_allowed ||
		    !drm_mode_is_420_also(&connector->display_info, mode))
			return status;
2028

2029
		status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2030 2031
		if (status != MODE_OK)
			return status;
2032
	}
2033

2034
	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2035 2036
}

2037 2038
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
			     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2039
{
2040
	struct drm_atomic_state *state = crtc_state->uapi.state;
2041 2042 2043
	struct drm_connector_state *connector_state;
	struct drm_connector *connector;
	int i;
2044

2045
	for_each_new_connector_in_state(state, connector, connector_state, i) {
2046
		if (connector_state->crtc != crtc_state->uapi.crtc)
2047 2048
			continue;

2049
		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2050
			return false;
2051 2052
	}

2053 2054 2055
	return true;
}

2056
static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2057 2058 2059 2060 2061 2062
{
	struct drm_i915_private *dev_priv =
		to_i915(crtc_state->uapi.crtc->dev);
	const struct drm_display_mode *adjusted_mode =
		&crtc_state->hw.adjusted_mode;

2063 2064 2065
	if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
		return false;

2066
	/* Display Wa_1405510057:icl,ehl */
2067
	if (intel_hdmi_is_ycbcr420(crtc_state) &&
2068
	    bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2069 2070
	    (adjusted_mode->crtc_hblank_end -
	     adjusted_mode->crtc_hblank_start) % 8 == 2)
2071 2072
		return false;

2073 2074
	return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
				       intel_hdmi_is_ycbcr420(crtc_state));
2075 2076
}

2077 2078
static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
				  struct intel_crtc_state *crtc_state,
2079
				  int clock, bool respect_downstream_limits)
2080
{
2081
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2082
	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2083 2084
	int bpc;

2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
	/*
	 * pipe_bpp could already be below 8bpc due to FDI
	 * bandwidth constraints. HDMI minimum is 8bpc however.
	 */
	bpc = max(crtc_state->pipe_bpp / 3, 8);

	/*
	 * We will never exceed downstream TMDS clock limits while
	 * attempting deep color. If the user insists on forcing an
	 * out of spec mode they will have to be satisfied with 8bpc.
	 */
	if (!respect_downstream_limits)
		bpc = 8;

	for (; bpc >= 8; bpc -= 2) {
		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);

		if (hdmi_bpc_possible(crtc_state, bpc) &&
		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
					  respect_downstream_limits,
					  crtc_state->has_hdmi_sink) == MODE_OK)
2106 2107 2108
			return bpc;
	}

2109
	return -EINVAL;
2110 2111 2112
}

static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2113 2114
				    struct intel_crtc_state *crtc_state,
				    bool respect_downstream_limits)
2115
{
2116
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2117
	const struct drm_display_mode *adjusted_mode =
2118
		&crtc_state->hw.adjusted_mode;
2119 2120 2121 2122 2123
	int bpc, clock = adjusted_mode->crtc_clock;

	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		clock *= 2;

2124 2125 2126 2127
	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
				     respect_downstream_limits);
	if (bpc < 0)
		return bpc;
2128

2129 2130
	crtc_state->port_clock =
		intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2131 2132 2133 2134

	/*
	 * pipe_bpp could already be below 8bpc due to
	 * FDI bandwidth constraints. We shouldn't bump it
2135
	 * back up to the HDMI minimum 8bpc in that case.
2136
	 */
2137
	crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2138

2139 2140 2141
	drm_dbg_kms(&i915->drm,
		    "picking %d bpc for HDMI output (pipe bpp: %d)\n",
		    bpc, crtc_state->pipe_bpp);
2142 2143 2144 2145

	return 0;
}

2146 2147
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
				    const struct drm_connector_state *conn_state)
2148 2149 2150 2151
{
	const struct intel_digital_connector_state *intel_conn_state =
		to_intel_digital_connector_state(conn_state);
	const struct drm_display_mode *adjusted_mode =
2152
		&crtc_state->hw.adjusted_mode;
2153

2154 2155 2156 2157 2158 2159 2160 2161 2162 2163
	/*
	 * Our YCbCr output is always limited range.
	 * crtc_state->limited_color_range only applies to RGB,
	 * and it must never be set for YCbCr or we risk setting
	 * some conflicting bits in PIPECONF which will mess up
	 * the colors on the monitor.
	 */
	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
		return false;

2164 2165 2166 2167 2168 2169 2170 2171 2172 2173
	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
		/* See CEA-861-E - 5.1 Default Encoding Parameters */
		return crtc_state->has_hdmi_sink &&
			drm_default_rgb_quant_range(adjusted_mode) ==
			HDMI_QUANTIZATION_RANGE_LIMITED;
	} else {
		return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
	}
}

2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190
static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
				 const struct intel_crtc_state *crtc_state,
				 const struct drm_connector_state *conn_state)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	const struct intel_digital_connector_state *intel_conn_state =
		to_intel_digital_connector_state(conn_state);

	if (!crtc_state->has_hdmi_sink)
		return false;

	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
		return intel_hdmi->has_audio;
	else
		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}

2191
static enum intel_output_format
2192 2193
intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
			 struct intel_connector *connector,
2194 2195
			 bool ycbcr_420_output)
{
2196 2197 2198
	if (!crtc_state->has_hdmi_sink)
		return INTEL_OUTPUT_FORMAT_RGB;

2199 2200 2201 2202 2203 2204
	if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
		return INTEL_OUTPUT_FORMAT_YCBCR420;
	else
		return INTEL_OUTPUT_FORMAT_RGB;
}

2205 2206
static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
					    struct intel_crtc_state *crtc_state,
2207 2208
					    const struct drm_connector_state *conn_state,
					    bool respect_downstream_limits)
2209
{
2210
	struct intel_connector *connector = to_intel_connector(conn_state->connector);
2211
	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2212 2213 2214
	const struct drm_display_info *info = &connector->base.display_info;
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
	bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2215 2216
	int ret;

2217 2218
	crtc_state->output_format =
		intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
2219 2220 2221 2222

	if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
		drm_dbg_kms(&i915->drm,
			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2223 2224 2225
		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
	}

2226
	ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2227
	if (ret) {
2228
		if (intel_hdmi_is_ycbcr420(crtc_state) ||
2229 2230
		    !connector->base.ycbcr_420_allowed ||
		    !drm_mode_is_420_also(info, adjusted_mode))
2231 2232
			return ret;

2233
		crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
2234
		ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2235
	}
2236 2237 2238 2239

	return ret;
}

2240 2241 2242 2243 2244 2245
static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
{
	return crtc_state->uapi.encoder_mask &&
		!is_power_of_2(crtc_state->uapi.encoder_mask);
}

2246 2247 2248
int intel_hdmi_compute_config(struct intel_encoder *encoder,
			      struct intel_crtc_state *pipe_config,
			      struct drm_connector_state *conn_state)
2249
{
2250
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2251
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2252
	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2253 2254
	struct drm_connector *connector = conn_state->connector;
	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2255
	int ret;
2256

2257
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2258
		return -EINVAL;
2259

2260
	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2261 2262 2263
	pipe_config->has_hdmi_sink =
		intel_has_hdmi_sink(intel_hdmi, conn_state) &&
		!intel_hdmi_is_cloned(pipe_config);
2264

2265 2266 2267
	if (pipe_config->has_hdmi_sink)
		pipe_config->has_infoframe = true;

2268
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2269 2270
		pipe_config->pixel_multiplier = 2;

2271 2272
	pipe_config->has_audio =
		intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2273

2274 2275 2276 2277 2278
	/*
	 * Try to respect downstream TMDS clock limits first, if
	 * that fails assume the user might know something we don't.
	 */
	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2279
	if (ret)
2280 2281 2282 2283 2284
		ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
	if (ret) {
		drm_dbg_kms(&dev_priv->drm,
			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
			    pipe_config->hw.adjusted_mode.crtc_clock);
2285
		return ret;
2286
	}
2287

2288
	if (intel_hdmi_is_ycbcr420(pipe_config)) {
2289
		ret = intel_panel_fitting(pipe_config, conn_state);
2290 2291 2292 2293 2294 2295 2296
		if (ret)
			return ret;
	}

	pipe_config->limited_color_range =
		intel_hdmi_limited_color_range(pipe_config, conn_state);

2297 2298 2299
	if (conn_state->picture_aspect_ratio)
		adjusted_mode->picture_aspect_ratio =
			conn_state->picture_aspect_ratio;
2300

2301 2302
	pipe_config->lane_count = 4;

2303
	if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2304 2305 2306 2307 2308 2309 2310 2311 2312
		if (scdc->scrambling.low_rates)
			pipe_config->hdmi_scrambling = true;

		if (pipe_config->port_clock > 340000) {
			pipe_config->hdmi_scrambling = true;
			pipe_config->hdmi_high_tmds_clock_ratio = true;
		}
	}

2313 2314
	intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
					 conn_state);
2315 2316

	if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2317
		drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2318 2319 2320 2321
		return -EINVAL;
	}

	if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2322
		drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2323 2324 2325 2326
		return -EINVAL;
	}

	if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2327
		drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2328 2329 2330
		return -EINVAL;
	}

2331
	if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2332
		drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2333 2334 2335
		return -EINVAL;
	}

2336
	return 0;
2337 2338
}

2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	/*
	 * Give a hand to buggy BIOSen which forget to turn
	 * the TMDS output buffers back on after a reboot.
	 */
	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
}

2350 2351
static void
intel_hdmi_unset_edid(struct drm_connector *connector)
2352
{
2353
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2354

2355 2356 2357
	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;

2358 2359 2360
	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;

2361 2362 2363 2364
	kfree(to_intel_connector(connector)->detect_edid);
	to_intel_connector(connector)->detect_edid = NULL;
}

2365
static void
2366
intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2367 2368
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2369
	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2370
	enum port port = hdmi_to_dig_port(hdmi)->base.port;
2371 2372
	struct i2c_adapter *adapter =
		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2373
	enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2374

2375 2376 2377 2378 2379 2380 2381
	/*
	 * Type 1 DVI adaptors are not required to implement any
	 * registers, so we can't always detect their presence.
	 * Ideally we should be able to check the state of the
	 * CONFIG1 pin, but no such luck on our hardware.
	 *
	 * The only method left to us is to check the VBT to see
2382
	 * if the port is a dual mode capable DP port.
2383 2384
	 */
	if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2385
		if (!connector->force &&
2386
		    intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2387 2388
			drm_dbg_kms(&dev_priv->drm,
				    "Assuming DP dual mode adaptor presence based on VBT\n");
2389 2390 2391 2392 2393 2394 2395
			type = DRM_DP_DUAL_MODE_TYPE1_DVI;
		} else {
			type = DRM_DP_DUAL_MODE_NONE;
		}
	}

	if (type == DRM_DP_DUAL_MODE_NONE)
2396 2397 2398 2399
		return;

	hdmi->dp_dual_mode.type = type;
	hdmi->dp_dual_mode.max_tmds_clock =
2400
		drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2401

2402 2403 2404 2405
	drm_dbg_kms(&dev_priv->drm,
		    "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
		    drm_dp_get_dual_mode_type_name(type),
		    hdmi->dp_dual_mode.max_tmds_clock);
2406 2407 2408 2409 2410 2411 2412 2413

	/* Older VBTs are often buggy and can't be trusted :( Play it safe. */
	if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
	    !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
		drm_dbg_kms(&dev_priv->drm,
			    "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
		hdmi->dp_dual_mode.max_tmds_clock = 0;
	}
2414 2415
}

2416
static bool
2417
intel_hdmi_set_edid(struct drm_connector *connector)
2418 2419
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2420
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2421
	intel_wakeref_t wakeref;
2422
	struct edid *edid;
2423
	bool connected = false;
2424
	struct i2c_adapter *i2c;
2425

2426
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2427

2428 2429 2430 2431 2432
	i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);

	edid = drm_get_edid(connector, i2c);

	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2433 2434
		drm_dbg_kms(&dev_priv->drm,
			    "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2435 2436 2437 2438
		intel_gmbus_force_bit(i2c, true);
		edid = drm_get_edid(connector, i2c);
		intel_gmbus_force_bit(i2c, false);
	}
2439

2440 2441 2442
	to_intel_connector(connector)->detect_edid = edid;
	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2443
		intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2444

2445 2446
		intel_hdmi_dp_dual_mode_detect(connector);

2447
		connected = true;
2448 2449
	}

2450 2451
	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);

2452 2453
	cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);

2454 2455 2456
	return connected;
}

2457 2458
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
2459
{
2460
	enum drm_connector_status status = connector_status_disconnected;
2461
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2462
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2463
	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2464
	intel_wakeref_t wakeref;
2465

2466 2467
	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
		    connector->base.id, connector->name);
2468

2469 2470 2471
	if (!INTEL_DISPLAY_ENABLED(dev_priv))
		return connector_status_disconnected;

2472
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2473

2474
	if (DISPLAY_VER(dev_priv) >= 11 &&
2475 2476 2477
	    !intel_digital_port_connected(encoder))
		goto out;

2478
	intel_hdmi_unset_edid(connector);
2479

2480
	if (intel_hdmi_set_edid(connector))
2481
		status = connector_status_connected;
2482

2483
out:
2484
	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2485

2486 2487 2488
	if (status != connector_status_connected)
		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);

2489 2490 2491 2492 2493 2494
	/*
	 * Make sure the refs for power wells enabled during detect are
	 * dropped to avoid a new detect cycle triggered by HPD polling.
	 */
	intel_display_power_flush_work(dev_priv);

2495
	return status;
2496 2497
}

2498 2499
static void
intel_hdmi_force(struct drm_connector *connector)
2500
{
2501 2502 2503 2504
	struct drm_i915_private *i915 = to_i915(connector->dev);

	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
		    connector->base.id, connector->name);
2505

2506
	intel_hdmi_unset_edid(connector);
2507

2508 2509
	if (connector->status != connector_status_connected)
		return;
2510

2511
	intel_hdmi_set_edid(connector);
2512
}
2513

2514 2515 2516 2517 2518 2519 2520
static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct edid *edid;

	edid = to_intel_connector(connector)->detect_edid;
	if (edid == NULL)
		return 0;
2521

2522
	return intel_connector_update_modes(connector, edid);
2523 2524
}

2525 2526 2527 2528
static struct i2c_adapter *
intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2529
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2530 2531 2532 2533 2534 2535

	return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
}

static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
{
2536
	struct drm_i915_private *i915 = to_i915(connector->dev);
2537 2538 2539 2540 2541 2542 2543
	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
	struct kobject *i2c_kobj = &adapter->dev.kobj;
	struct kobject *connector_kobj = &connector->kdev->kobj;
	int ret;

	ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
	if (ret)
2544
		drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555
}

static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
{
	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
	struct kobject *i2c_kobj = &adapter->dev.kobj;
	struct kobject *connector_kobj = &connector->kdev->kobj;

	sysfs_remove_link(connector_kobj, i2c_kobj->name);
}

2556 2557 2558 2559 2560 2561 2562 2563 2564
static int
intel_hdmi_connector_register(struct drm_connector *connector)
{
	int ret;

	ret = intel_connector_register(connector);
	if (ret)
		return ret;

2565 2566
	intel_hdmi_create_i2c_symlink(connector);

2567 2568 2569
	return ret;
}

2570
static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2571
{
2572
	struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2573 2574

	cec_notifier_conn_unregister(n);
2575

2576 2577 2578 2579
	intel_hdmi_remove_i2c_symlink(connector);
	intel_connector_unregister(connector);
}

2580 2581
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.detect = intel_hdmi_detect,
2582
	.force = intel_hdmi_force,
2583
	.fill_modes = drm_helper_probe_single_connector_modes,
2584 2585
	.atomic_get_property = intel_digital_connector_atomic_get_property,
	.atomic_set_property = intel_digital_connector_atomic_set_property,
2586
	.late_register = intel_hdmi_connector_register,
2587
	.early_unregister = intel_hdmi_connector_unregister,
2588
	.destroy = intel_connector_destroy,
2589
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2590
	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
2591 2592 2593 2594 2595
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
2596
	.atomic_check = intel_digital_connector_atomic_check,
2597 2598
};

2599 2600 2601
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
2602 2603
	struct drm_i915_private *dev_priv = to_i915(connector->dev);

2604
	intel_attach_force_audio_property(connector);
2605
	intel_attach_broadcast_rgb_property(connector);
2606
	intel_attach_aspect_ratio_property(connector);
2607

2608
	intel_attach_hdmi_colorspace_property(connector);
2609
	drm_connector_attach_content_type_property(connector);
2610

2611
	if (DISPLAY_VER(dev_priv) >= 10)
2612
		drm_connector_attach_hdr_output_metadata_property(connector);
2613

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Rodrigo Vivi committed
2614
	if (!HAS_GMCH(dev_priv))
2615
		drm_connector_attach_max_bpc_property(connector, 8, 12);
2616 2617
}

2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631
/*
 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
 * @encoder: intel_encoder
 * @connector: drm_connector
 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
 *  or reset the high tmds clock ratio for scrambling
 * @scrambling: bool to Indicate if the function needs to set or reset
 *  sink scrambling
 *
 * This function handles scrambling on HDMI 2.0 capable sinks.
 * If required clock rate is > 340 Mhz && scrambling is supported by sink
 * it enables scrambling. This should be called before enabling the HDMI
 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
 * detect a scrambled clock within 100 ms.
2632 2633 2634
 *
 * Returns:
 * True on success, false on failure.
2635
 */
2636
bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2637 2638 2639 2640
				       struct drm_connector *connector,
				       bool high_tmds_clock_ratio,
				       bool scrambling)
{
2641
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2642
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2643
	struct drm_scrambling *sink_scrambling =
2644 2645 2646
		&connector->display_info.hdmi.scdc.scrambling;
	struct i2c_adapter *adapter =
		intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2647 2648

	if (!sink_scrambling->supported)
2649
		return true;
2650

2651 2652 2653
	drm_dbg_kms(&dev_priv->drm,
		    "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
		    connector->base.id, connector->name,
2654
		    str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2655

2656 2657 2658 2659
	/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
	return drm_scdc_set_high_tmds_clock_ratio(adapter,
						  high_tmds_clock_ratio) &&
		drm_scdc_set_scrambling(adapter, scrambling);
2660 2661
}

2662
static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2663 2664 2665
{
	u8 ddc_pin;

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	switch (port) {
	case PORT_B:
		ddc_pin = GMBUS_PIN_DPB;
		break;
	case PORT_C:
		ddc_pin = GMBUS_PIN_DPC;
		break;
	case PORT_D:
		ddc_pin = GMBUS_PIN_DPD_CHV;
		break;
	default:
		MISSING_CASE(port);
		ddc_pin = GMBUS_PIN_DPB;
		break;
2680
	}
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	return ddc_pin;
}

static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
	u8 ddc_pin;
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	switch (port) {
	case PORT_B:
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		ddc_pin = GMBUS_PIN_1_BXT;
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		break;
	case PORT_C:
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		ddc_pin = GMBUS_PIN_2_BXT;
		break;
	default:
		MISSING_CASE(port);
		ddc_pin = GMBUS_PIN_1_BXT;
		break;
	}
	return ddc_pin;
}

static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
			      enum port port)
{
	u8 ddc_pin;

	switch (port) {
	case PORT_B:
		ddc_pin = GMBUS_PIN_1_BXT;
		break;
	case PORT_C:
		ddc_pin = GMBUS_PIN_2_BXT;
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		break;
	case PORT_D:
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		ddc_pin = GMBUS_PIN_4_CNP;
		break;
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	case PORT_F:
		ddc_pin = GMBUS_PIN_3_BXT;
		break;
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	default:
		MISSING_CASE(port);
		ddc_pin = GMBUS_PIN_1_BXT;
		break;
	}
	return ddc_pin;
}

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static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
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	enum phy phy = intel_port_to_phy(dev_priv, port);
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	if (intel_phy_is_combo(dev_priv, phy))
		return GMBUS_PIN_1_BXT + port;
	else if (intel_phy_is_tc(dev_priv, phy))
		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);

2738
	drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2739
	return GMBUS_PIN_2_BXT;
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}

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static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
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	enum phy phy = intel_port_to_phy(dev_priv, port);
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	u8 ddc_pin;

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	switch (phy) {
	case PHY_A:
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		ddc_pin = GMBUS_PIN_1_BXT;
		break;
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	case PHY_B:
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		ddc_pin = GMBUS_PIN_2_BXT;
		break;
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	case PHY_C:
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		ddc_pin = GMBUS_PIN_9_TC1_ICP;
		break;
	default:
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		MISSING_CASE(phy);
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		ddc_pin = GMBUS_PIN_1_BXT;
		break;
	}
	return ddc_pin;
}

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static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
	enum phy phy = intel_port_to_phy(dev_priv, port);

	WARN_ON(port == PORT_C);

	/*
	 * Pin mapping for RKL depends on which PCH is present.  With TGP, the
	 * final two outputs use type-c pins, even though they're actually
	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
	 * all outputs.
	 */
	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;

	return GMBUS_PIN_1_BXT + phy;
}

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static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
{
	enum phy phy = intel_port_to_phy(i915, port);

	drm_WARN_ON(&i915->drm, port == PORT_A);

	/*
	 * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
	 * final two outputs use type-c pins, even though they're actually
	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
	 * all outputs.
	 */
	if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;

	return GMBUS_PIN_1_BXT + phy;
}

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static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
	return intel_port_to_phy(dev_priv, port) + 1;
}

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static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
{
	enum phy phy = intel_port_to_phy(dev_priv, port);

	WARN_ON(port == PORT_B || port == PORT_C);

	/*
	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
	 * except first combo output.
	 */
	if (phy == PHY_A)
		return GMBUS_PIN_1_BXT;

	return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
}

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static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
			      enum port port)
{
	u8 ddc_pin;

	switch (port) {
	case PORT_B:
		ddc_pin = GMBUS_PIN_DPB;
		break;
	case PORT_C:
		ddc_pin = GMBUS_PIN_DPC;
		break;
	case PORT_D:
		ddc_pin = GMBUS_PIN_DPD;
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		break;
	default:
		MISSING_CASE(port);
		ddc_pin = GMBUS_PIN_DPB;
		break;
	}
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	return ddc_pin;
}

2845
static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2846
{
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	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum port port = encoder->port;
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	u8 ddc_pin;

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	ddc_pin = intel_bios_alternate_ddc_pin(encoder);
	if (ddc_pin) {
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		drm_dbg_kms(&dev_priv->drm,
			    "Using DDC pin 0x%x for port %c (VBT)\n",
			    ddc_pin, port_name(port));
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		return ddc_pin;
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	}

2859
	if (IS_ALDERLAKE_S(dev_priv))
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		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
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		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
	else if (IS_ROCKETLAKE(dev_priv))
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		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
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	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
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		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
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Ville Syrjälä committed
2867
	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
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		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
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	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
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	else if (HAS_PCH_CNP(dev_priv))
		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
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	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
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		ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
	else if (IS_CHERRYVIEW(dev_priv))
		ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
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	else
		ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
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	drm_dbg_kms(&dev_priv->drm,
		    "Using DDC pin 0x%x for port %c (platform default)\n",
		    ddc_pin, port_name(port));
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	return ddc_pin;
}

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void intel_infoframe_init(struct intel_digital_port *dig_port)
2888 2889
{
	struct drm_i915_private *dev_priv =
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		to_i915(dig_port->base.base.dev);
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	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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		dig_port->write_infoframe = vlv_write_infoframe;
		dig_port->read_infoframe = vlv_read_infoframe;
		dig_port->set_infoframes = vlv_set_infoframes;
		dig_port->infoframes_enabled = vlv_infoframes_enabled;
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	} else if (IS_G4X(dev_priv)) {
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		dig_port->write_infoframe = g4x_write_infoframe;
		dig_port->read_infoframe = g4x_read_infoframe;
		dig_port->set_infoframes = g4x_set_infoframes;
		dig_port->infoframes_enabled = g4x_infoframes_enabled;
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	} else if (HAS_DDI(dev_priv)) {
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		if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
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			dig_port->write_infoframe = lspcon_write_infoframe;
			dig_port->read_infoframe = lspcon_read_infoframe;
			dig_port->set_infoframes = lspcon_set_infoframes;
			dig_port->infoframes_enabled = lspcon_infoframes_enabled;
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		} else {
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			dig_port->write_infoframe = hsw_write_infoframe;
			dig_port->read_infoframe = hsw_read_infoframe;
			dig_port->set_infoframes = hsw_set_infoframes;
			dig_port->infoframes_enabled = hsw_infoframes_enabled;
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		}
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	} else if (HAS_PCH_IBX(dev_priv)) {
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		dig_port->write_infoframe = ibx_write_infoframe;
		dig_port->read_infoframe = ibx_read_infoframe;
		dig_port->set_infoframes = ibx_set_infoframes;
		dig_port->infoframes_enabled = ibx_infoframes_enabled;
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	} else {
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		dig_port->write_infoframe = cpt_write_infoframe;
		dig_port->read_infoframe = cpt_read_infoframe;
		dig_port->set_infoframes = cpt_set_infoframes;
		dig_port->infoframes_enabled = cpt_infoframes_enabled;
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	}
}

2927
void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2928
			       struct intel_connector *intel_connector)
2929
{
2930
	struct drm_connector *connector = &intel_connector->base;
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	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
	struct intel_encoder *intel_encoder = &dig_port->base;
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	struct drm_device *dev = intel_encoder->base.dev;
2934
	struct drm_i915_private *dev_priv = to_i915(dev);
2935
	struct i2c_adapter *ddc;
2936
	enum port port = intel_encoder->port;
2937
	struct cec_connector_info conn_info;
2938

2939 2940 2941
	drm_dbg_kms(&dev_priv->drm,
		    "Adding HDMI connector on [ENCODER:%d:%s]\n",
		    intel_encoder->base.base.id, intel_encoder->base.name);
2942

2943
	if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2944 2945
		return;

2946
	if (drm_WARN(dev, dig_port->max_lanes < 4,
2947
		     "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2948
		     dig_port->max_lanes, intel_encoder->base.base.id,
2949
		     intel_encoder->base.name))
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		return;

2952
	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
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	ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);

	drm_connector_init_with_ddc(dev, connector,
				    &intel_hdmi_connector_funcs,
				    DRM_MODE_CONNECTOR_HDMIA,
				    ddc);
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	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

2961 2962
	connector->interlace_allowed = true;
	connector->stereo_allowed = true;
2963

2964
	if (DISPLAY_VER(dev_priv) >= 10)
2965 2966
		connector->ycbcr_420_allowed = true;

2967
	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2968

2969
	if (HAS_DDI(dev_priv))
2970 2971 2972
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
2973 2974 2975

	intel_hdmi_add_properties(intel_hdmi, connector);

2976 2977 2978
	intel_connector_attach_encoder(intel_connector, intel_encoder);
	intel_hdmi->attached_connector = intel_connector;

2979
	if (is_hdcp_supported(dev_priv, port)) {
2980
		int ret = intel_hdcp_init(intel_connector, dig_port,
2981 2982
					  &intel_hdmi_hdcp_shim);
		if (ret)
2983 2984
			drm_dbg_kms(&dev_priv->drm,
				    "HDCP init failed, skipping.\n");
2985 2986
	}

2987 2988 2989 2990
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
2991
	if (IS_G45(dev_priv)) {
2992 2993 2994
		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
		               (temp & ~0xf) | 0xd);
2995
	}
2996

2997 2998 2999 3000 3001
	cec_fill_conn_info_from_drm(&conn_info, connector);

	intel_hdmi->cec_notifier =
		cec_notifier_conn_register(dev->dev, port_identifier(port),
					   &conn_info);
3002
	if (!intel_hdmi->cec_notifier)
3003
		drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3004 3005
}

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/*
 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
 * @vactive: Vactive of a display mode
 *
 * @return: appropriate dsc slice height for a given mode.
 */
int intel_hdmi_dsc_get_slice_height(int vactive)
{
	int slice_height;

	/*
	 * Slice Height determination : HDMI2.1 Section 7.7.5.2
	 * Select smallest slice height >=96, that results in a valid PPS and
	 * requires minimum padding lines required for final slice.
	 *
	 * Assumption : Vactive is even.
	 */
	for (slice_height = 96; slice_height <= vactive; slice_height += 2)
		if (vactive % slice_height == 0)
			return slice_height;

	return 0;
}

/*
 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
 * and dsc decoder capabilities
 *
 * @crtc_state: intel crtc_state
 * @src_max_slices: maximum slices supported by the DSC encoder
 * @src_max_slice_width: maximum slice width supported by DSC encoder
 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
 *
 * @return: num of dsc slices that can be supported by the dsc encoder
 * and decoder.
 */
int
intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
			      int src_max_slices, int src_max_slice_width,
			      int hdmi_max_slices, int hdmi_throughput)
{
/* Pixel rates in KPixels/sec */
#define HDMI_DSC_PEAK_PIXEL_RATE		2720000
/*
 * Rates at which the source and sink are required to process pixels in each
 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
 */
#define HDMI_DSC_MAX_ENC_THROUGHPUT_0		340000
#define HDMI_DSC_MAX_ENC_THROUGHPUT_1		400000

/* Spec limits the slice width to 2720 pixels */
#define MAX_HDMI_SLICE_WIDTH			2720
	int kslice_adjust;
	int adjusted_clk_khz;
	int min_slices;
	int target_slices;
	int max_throughput; /* max clock freq. in khz per slice */
	int max_slice_width;
	int slice_width;
	int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;

	if (!hdmi_throughput)
		return 0;

	/*
	 * Slice Width determination : HDMI2.1 Section 7.7.5.1
	 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
	 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
	 * dividing adjusted clock value by 10.
	 */
	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
		kslice_adjust = 10;
	else
		kslice_adjust = 5;

	/*
	 * As per spec, the rate at which the source and the sink process
	 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
	 * This depends upon the pixel clock rate and output formats
	 * (kslice adjust).
	 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
	 * at max 340MHz, otherwise they can be processed at max 400MHz.
	 */

	adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);

	if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
	else
		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;

	/*
	 * Taking into account the sink's capability for maximum
	 * clock per slice (in MHz) as read from HF-VSDB.
	 */
	max_throughput = min(max_throughput, hdmi_throughput * 1000);

	min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
	max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);

	/*
	 * Keep on increasing the num of slices/line, starting from min_slices
	 * per line till we get such a number, for which the slice_width is
	 * just less than max_slice_width. The slices/line selected should be
	 * less than or equal to the max horizontal slices that the combination
	 * of PCON encoder and HDMI decoder can support.
	 */
	slice_width = max_slice_width;

	do {
		if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
			target_slices = 1;
		else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
			target_slices = 2;
		else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
			target_slices = 4;
		else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
			target_slices = 8;
		else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
			target_slices = 12;
		else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
			target_slices = 16;
		else
			return 0;

		slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
		if (slice_width >= max_slice_width)
			min_slices = target_slices + 1;
	} while (slice_width >= max_slice_width);

	return target_slices;
}

/*
 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
 * source and sink capabilities.
 *
 * @src_fraction_bpp: fractional bpp supported by the source
 * @slice_width: dsc slice width supported by the source and sink
 * @num_slices: num of slices supported by the source and sink
 * @output_format: video output format
 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
 *
 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
 */
int
intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
		       int output_format, bool hdmi_all_bpp,
		       int hdmi_max_chunk_bytes)
{
	int max_dsc_bpp, min_dsc_bpp;
	int target_bytes;
	bool bpp_found = false;
	int bpp_decrement_x16;
	int bpp_target;
	int bpp_target_x16;

	/*
	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
	 * Start with the max bpp and keep on decrementing with
	 * fractional bpp, if supported by PCON DSC encoder
	 *
	 * for each bpp we check if no of bytes can be supported by HDMI sink
	 */

	/* Assuming: bpc as 8*/
	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
		min_dsc_bpp = 6;
		max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
	} else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
		   output_format == INTEL_OUTPUT_FORMAT_RGB) {
		min_dsc_bpp = 8;
		max_dsc_bpp = 3 * 8; /* 3*bpc */
	} else {
		/* Assuming 4:2:2 encoding */
		min_dsc_bpp = 7;
		max_dsc_bpp = 2 * 8; /* 2*bpc */
	}

	/*
	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
	 * Section 7.7.34 : Source shall not enable compressed Video
	 * Transport with bpp_target settings above 12 bpp unless
	 * DSC_all_bpp is set to 1.
	 */
	if (!hdmi_all_bpp)
		max_dsc_bpp = min(max_dsc_bpp, 12);

	/*
	 * The Sink has a limit of compressed data in bytes for a scanline,
	 * as described in max_chunk_bytes field in HFVSDB block of edid.
	 * The no. of bytes depend on the target bits per pixel that the
	 * source configures. So we start with the max_bpp and calculate
	 * the target_chunk_bytes. We keep on decrementing the target_bpp,
	 * till we get the target_chunk_bytes just less than what the sink's
	 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
	 *
	 * The decrement is according to the fractional support from PCON DSC
	 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
	 *
	 * bpp_target_x16 = bpp_target * 16
	 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
	 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
	 */

	bpp_target = max_dsc_bpp;

	/* src does not support fractional bpp implies decrement by 16 for bppx16 */
	if (!src_fractional_bpp)
		src_fractional_bpp = 1;
	bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
	bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;

	while (bpp_target_x16 > (min_dsc_bpp * 16)) {
		int bpp;

		bpp = DIV_ROUND_UP(bpp_target_x16, 16);
		target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
		if (target_bytes <= hdmi_max_chunk_bytes) {
			bpp_found = true;
			break;
		}
		bpp_target_x16 -= bpp_decrement_x16;
	}
	if (bpp_found)
		return bpp_target_x16;

	return 0;
}