intel_crt.c 28.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

27
#include <linux/dmi.h>
28
#include <linux/i2c.h>
29
#include <linux/slab.h>
30
#include <drm/drmP.h>
31
#include <drm/drm_atomic_helper.h>
32 33 34
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
35
#include "intel_drv.h"
36
#include <drm/i915_drm.h>
37 38
#include "i915_drv.h"

39 40 41 42 43 44 45 46
/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
			   ADPA_CRT_HOTPLUG_ENABLE)

47 48
struct intel_crt {
	struct intel_encoder base;
49 50 51
	/* DPMS state is stored in the connector, which we need in the
	 * encoder's enable/disable callbacks */
	struct intel_connector *connector;
52
	bool force_hotplug_required;
53
	i915_reg_t adpa_reg;
54 55
};

56
static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
57
{
58
	return container_of(encoder, struct intel_crt, base);
59 60
}

61
static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
62
{
63
	return intel_encoder_to_crt(intel_attached_encoder(connector));
64 65
}

66 67
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
68
{
69
	struct drm_device *dev = encoder->base.dev;
70
	struct drm_i915_private *dev_priv = to_i915(dev);
71 72
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	u32 tmp;
73
	bool ret;
74

75 76
	if (!intel_display_power_get_if_enabled(dev_priv,
						encoder->power_domain))
77 78
		return false;

79 80
	ret = false;

81 82 83
	tmp = I915_READ(crt->adpa_reg);

	if (!(tmp & ADPA_DAC_ENABLE))
84
		goto out;
85

86
	if (HAS_PCH_CPT(dev_priv))
87 88 89 90
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);

91 92
	ret = true;
out:
93
	intel_display_power_put(dev_priv, encoder->power_domain);
94 95

	return ret;
96 97
}

98
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
99
{
100
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	u32 tmp, flags = 0;

	tmp = I915_READ(crt->adpa_reg);

	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;

	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

116 117 118 119
	return flags;
}

static void intel_crt_get_config(struct intel_encoder *encoder,
120
				 struct intel_crtc_state *pipe_config)
121
{
122 123
	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);

124
	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
125

126
	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
127 128
}

129
static void hsw_crt_get_config(struct intel_encoder *encoder,
130
			       struct intel_crtc_state *pipe_config)
131
{
132 133
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

134 135
	intel_ddi_get_config(encoder, pipe_config);

136
	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
137 138 139
					      DRM_MODE_FLAG_NHSYNC |
					      DRM_MODE_FLAG_PVSYNC |
					      DRM_MODE_FLAG_NVSYNC);
140
	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
141 142

	pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
143 144
}

145 146
/* Note: The caller is required to filter out dpms modes not supported by the
 * platform. */
147
static void intel_crt_set_dpms(struct intel_encoder *encoder,
148
			       const struct intel_crtc_state *crtc_state,
149
			       int mode)
150
{
151
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
152
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
153 154
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
155 156
	u32 adpa;

157
	if (INTEL_GEN(dev_priv) >= 5)
158 159 160
		adpa = ADPA_HOTPLUG_BITS;
	else
		adpa = 0;
161

162 163 164 165 166 167
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;

	/* For CPT allow 3 pipe config, for others just use A or B */
168
	if (HAS_PCH_LPT(dev_priv))
169
		; /* Those bits don't exist here */
170
	else if (HAS_PCH_CPT(dev_priv))
171 172 173 174 175 176
		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
	else if (crtc->pipe == 0)
		adpa |= ADPA_PIPE_A_SELECT;
	else
		adpa |= ADPA_PIPE_B_SELECT;

177
	if (!HAS_PCH_SPLIT(dev_priv))
178
		I915_WRITE(BCLRPAT(crtc->pipe), 0);
179

180
	switch (mode) {
181
	case DRM_MODE_DPMS_ON:
182
		adpa |= ADPA_DAC_ENABLE;
183 184
		break;
	case DRM_MODE_DPMS_STANDBY:
185
		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
186 187
		break;
	case DRM_MODE_DPMS_SUSPEND:
188
		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
189 190
		break;
	case DRM_MODE_DPMS_OFF:
191
		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
192 193 194
		break;
	}

195
	I915_WRITE(crt->adpa_reg, adpa);
196
}
197

198
static void intel_disable_crt(struct intel_encoder *encoder,
199 200
			      const struct intel_crtc_state *old_crtc_state,
			      const struct drm_connector_state *old_conn_state)
201
{
202
	intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
203 204
}

205
static void pch_disable_crt(struct intel_encoder *encoder,
206 207
			    const struct intel_crtc_state *old_crtc_state,
			    const struct drm_connector_state *old_conn_state)
208 209 210
{
}

211
static void pch_post_disable_crt(struct intel_encoder *encoder,
212 213
				 const struct intel_crtc_state *old_crtc_state,
				 const struct drm_connector_state *old_conn_state)
214
{
215
	intel_disable_crt(encoder, old_crtc_state, old_conn_state);
216
}
217

218 219 220 221 222 223 224 225 226 227 228 229 230
static void hsw_disable_crt(struct intel_encoder *encoder,
			    const struct intel_crtc_state *old_crtc_state,
			    const struct drm_connector_state *old_conn_state)
{
	struct drm_crtc *crtc = old_crtc_state->base.crtc;
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	WARN_ON(!intel_crtc->config->has_pch_encoder);

	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}

231
static void hsw_post_disable_crt(struct intel_encoder *encoder,
232 233
				 const struct intel_crtc_state *old_crtc_state,
				 const struct drm_connector_state *old_conn_state)
234 235 236 237 238 239 240 241 242
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);

	lpt_disable_pch_transcoder(dev_priv);
	lpt_disable_iclkip(dev_priv);

	intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
243 244 245 246

	WARN_ON(!old_crtc_state->has_pch_encoder);

	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
247 248
}

249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273
static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
				   const struct intel_crtc_state *pipe_config,
				   const struct drm_connector_state *conn_state)
{
	struct drm_crtc *crtc = pipe_config->base.crtc;
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	WARN_ON(!intel_crtc->config->has_pch_encoder);

	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}

static void hsw_pre_enable_crt(struct intel_encoder *encoder,
			       const struct intel_crtc_state *pipe_config,
			       const struct drm_connector_state *conn_state)
{
	struct drm_crtc *crtc = pipe_config->base.crtc;
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;

	WARN_ON(!intel_crtc->config->has_pch_encoder);

	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
274 275

	dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296
}

static void hsw_enable_crt(struct intel_encoder *encoder,
			   const struct intel_crtc_state *pipe_config,
			   const struct drm_connector_state *conn_state)
{
	struct drm_crtc *crtc = pipe_config->base.crtc;
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;

	WARN_ON(!intel_crtc->config->has_pch_encoder);

	intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);

	intel_wait_for_vblank(dev_priv, pipe);
	intel_wait_for_vblank(dev_priv, pipe);
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}

297
static void intel_enable_crt(struct intel_encoder *encoder,
298 299
			     const struct intel_crtc_state *pipe_config,
			     const struct drm_connector_state *conn_state)
300
{
301
	intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
302 303
}

304 305 306
static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
307
{
308
	struct drm_device *dev = connector->dev;
309 310
	struct drm_i915_private *dev_priv = to_i915(dev);
	int max_dotclk = dev_priv->max_dotclk_freq;
311
	int max_clock;
312

313 314 315
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

316 317 318
	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;

319
	if (HAS_PCH_LPT(dev_priv))
320
		max_clock = 180000;
321
	else if (IS_VALLEYVIEW(dev_priv))
322 323 324 325 326
		/*
		 * 270 MHz due to current DPLL limits,
		 * DAC limit supposedly 355 MHz.
		 */
		max_clock = 270000;
327
	else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
328
		max_clock = 400000;
329 330
	else
		max_clock = 350000;
331 332
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;
333

334 335 336
	if (mode->clock > max_dotclk)
		return MODE_CLOCK_HIGH;

337
	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
338
	if (HAS_PCH_LPT(dev_priv) &&
339 340 341
	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
		return MODE_CLOCK_HIGH;

342 343 344
	return MODE_OK;
}

345
static bool intel_crt_compute_config(struct intel_encoder *encoder,
346 347
				     struct intel_crtc_state *pipe_config,
				     struct drm_connector_state *conn_state)
348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363
{
	return true;
}

static bool pch_crt_compute_config(struct intel_encoder *encoder,
				   struct intel_crtc_state *pipe_config,
				   struct drm_connector_state *conn_state)
{
	pipe_config->has_pch_encoder = true;

	return true;
}

static bool hsw_crt_compute_config(struct intel_encoder *encoder,
				   struct intel_crtc_state *pipe_config,
				   struct drm_connector_state *conn_state)
364
{
365
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
366

367
	pipe_config->has_pch_encoder = true;
368

369
	/* LPT FDI RX only supports 8bpc. */
370
	if (HAS_PCH_LPT(dev_priv)) {
371 372 373 374 375
		if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
			DRM_DEBUG_KMS("LPT only supports 24bpp\n");
			return false;
		}

376
		pipe_config->pipe_bpp = 24;
377
	}
378

379
	/* FDI must always be 2.7 GHz */
380
	pipe_config->port_clock = 135000 * 2;
381

382 383 384
	return true;
}

385
static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
386 387
{
	struct drm_device *dev = connector->dev;
388
	struct intel_crt *crt = intel_attached_crt(connector);
389
	struct drm_i915_private *dev_priv = to_i915(dev);
390
	u32 adpa;
391 392
	bool ret;

393 394
	/* The first time through, trigger an explicit detection cycle */
	if (crt->force_hotplug_required) {
395
		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
396
		u32 save_adpa;
397

398 399
		crt->force_hotplug_required = 0;

400
		save_adpa = adpa = I915_READ(crt->adpa_reg);
401 402 403 404 405 406
		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);

		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
		if (turn_off_dac)
			adpa &= ~ADPA_DAC_ENABLE;

407
		I915_WRITE(crt->adpa_reg, adpa);
408

409 410 411 412
		if (intel_wait_for_register(dev_priv,
					    crt->adpa_reg,
					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
					    1000))
413 414 415
			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");

		if (turn_off_dac) {
416 417
			I915_WRITE(crt->adpa_reg, save_adpa);
			POSTING_READ(crt->adpa_reg);
418
		}
419 420
	}

421
	/* Check the status to see if both blue and green are on now */
422
	adpa = I915_READ(crt->adpa_reg);
423
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
424 425 426
		ret = true;
	else
		ret = false;
427
	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
428 429

	return ret;
430 431
}

432 433 434
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
435
	struct intel_crt *crt = intel_attached_crt(connector);
436
	struct drm_i915_private *dev_priv = to_i915(dev);
437
	bool reenable_hpd;
438 439 440 441
	u32 adpa;
	bool ret;
	u32 save_adpa;

442 443 444 445 446 447 448 449 450 451 452 453 454 455
	/*
	 * Doing a force trigger causes a hpd interrupt to get sent, which can
	 * get us stuck in a loop if we're polling:
	 *  - We enable power wells and reset the ADPA
	 *  - output_poll_exec does force probe on VGA, triggering a hpd
	 *  - HPD handler waits for poll to unlock dev->mode_config.mutex
	 *  - output_poll_exec shuts off the ADPA, unlocks
	 *    dev->mode_config.mutex
	 *  - HPD handler runs, resets ADPA and brings us back to the start
	 *
	 * Just disable HPD interrupts here to prevent this
	 */
	reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);

456
	save_adpa = adpa = I915_READ(crt->adpa_reg);
457 458 459 460
	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);

	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;

461
	I915_WRITE(crt->adpa_reg, adpa);
462

463 464 465 466
	if (intel_wait_for_register(dev_priv,
				    crt->adpa_reg,
				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
				    1000)) {
467
		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
468
		I915_WRITE(crt->adpa_reg, save_adpa);
469 470 471
	}

	/* Check the status to see if both blue and green are on now */
472
	adpa = I915_READ(crt->adpa_reg);
473 474 475 476 477 478 479
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;

	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);

480 481 482
	if (reenable_hpd)
		intel_hpd_enable(dev_priv, crt->base.hpd_pin);

483 484 485
	return ret;
}

486 487 488 489 490 491 492 493 494 495 496
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
497
	struct drm_i915_private *dev_priv = to_i915(dev);
498
	u32 stat;
499
	bool ret = false;
500
	int i, tries = 0;
501

502
	if (HAS_PCH_SPLIT(dev_priv))
503
		return intel_ironlake_crt_detect_hotplug(connector);
504

505
	if (IS_VALLEYVIEW(dev_priv))
506 507
		return valleyview_crt_detect_hotplug(connector);

508 509 510 511
	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */
512

513
	if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
514 515 516 517 518 519
		tries = 2;
	else
		tries = 1;

	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
520 521 522
		i915_hotplug_interrupt_update(dev_priv,
					      CRT_HOTPLUG_FORCE_DETECT,
					      CRT_HOTPLUG_FORCE_DETECT);
523
		/* wait for FORCE_DETECT to go off */
524 525 526
		if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
					    CRT_HOTPLUG_FORCE_DETECT, 0,
					    1000))
527
			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
528
	}
529

530 531 532 533 534 535
	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;

	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
536

537
	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
538 539

	return ret;
540 541
}

542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563
static struct edid *intel_crt_get_edid(struct drm_connector *connector,
				struct i2c_adapter *i2c)
{
	struct edid *edid;

	edid = drm_get_edid(connector, i2c);

	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
		DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
		intel_gmbus_force_bit(i2c, true);
		edid = drm_get_edid(connector, i2c);
		intel_gmbus_force_bit(i2c, false);
	}

	return edid;
}

/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
static int intel_crt_ddc_get_modes(struct drm_connector *connector,
				struct i2c_adapter *adapter)
{
	struct edid *edid;
564
	int ret;
565 566 567 568 569

	edid = intel_crt_get_edid(connector, adapter);
	if (!edid)
		return 0;

570 571 572 573
	ret = intel_connector_update_modes(connector, edid);
	kfree(edid);

	return ret;
574 575
}

576
static bool intel_crt_detect_ddc(struct drm_connector *connector)
577
{
578
	struct intel_crt *crt = intel_attached_crt(connector);
579
	struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
580 581
	struct edid *edid;
	struct i2c_adapter *i2c;
582
	bool ret = false;
583

584
	BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
585

586
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
587
	edid = intel_crt_get_edid(connector, i2c);
588 589 590

	if (edid) {
		bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
591 592 593 594 595 596 597 598

		/*
		 * This may be a DVI-I connector with a shared DDC
		 * link between analog and digital outputs, so we
		 * have to check the EDID input spec of the attached device.
		 */
		if (!is_digital) {
			DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
599 600 601
			ret = true;
		} else {
			DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
602
		}
603 604
	} else {
		DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
605 606
	}

607 608
	kfree(edid);

609
	return ret;
610 611
}

612
static enum drm_connector_status
613
intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
614
{
615
	struct drm_device *dev = crt->base.base.dev;
616
	struct drm_i915_private *dev_priv = to_i915(dev);
617 618 619 620 621 622
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
623 624
	i915_reg_t bclrpat_reg, vtotal_reg,
		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
625 626 627
	uint8_t	st00;
	enum drm_connector_status status;

628 629
	DRM_DEBUG_KMS("starting load-detect on CRT\n");

630 631 632 633 634 635
	bclrpat_reg = BCLRPAT(pipe);
	vtotal_reg = VTOTAL(pipe);
	vblank_reg = VBLANK(pipe);
	vsync_reg = VSYNC(pipe);
	pipeconf_reg = PIPECONF(pipe);
	pipe_dsl_reg = PIPEDSL(pipe);
636 637 638 639 640 641 642 643 644 645 646 647 648 649

	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);

	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;

	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;

	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);

650
	if (!IS_GEN2(dev_priv)) {
651 652
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
653
		POSTING_READ(pipeconf_reg);
654 655
		/* Wait for next Vblank to substitue
		 * border color for Color info */
656
		intel_wait_for_vblank(dev_priv, pipe);
657
		st00 = I915_READ8(_VGA_MSR_WRITE);
658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;

		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;

		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;

			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;

		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
702
			st00 = I915_READ8(_VGA_MSR_WRITE);
703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));

		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}

	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);

	return status;
}

727 728 729 730 731 732 733 734 735 736 737 738 739 740 741
static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
{
	DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
	return 1;
}

static const struct dmi_system_id intel_spurious_crt_detect[] = {
	{
		.callback = intel_spurious_crt_detect_dmi_callback,
		.ident = "ACER ZGB",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
		},
	},
742 743 744 745 746 747 748 749
	{
		.callback = intel_spurious_crt_detect_dmi_callback,
		.ident = "Intel DZ77BH-55K",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
			DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
		},
	},
750 751 752
	{ }
};

753 754 755 756
static int
intel_crt_detect(struct drm_connector *connector,
		 struct drm_modeset_acquire_ctx *ctx,
		 bool force)
757
{
758
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
759
	struct intel_crt *crt = intel_attached_crt(connector);
760
	struct intel_encoder *intel_encoder = &crt->base;
761
	int status, ret;
762
	struct intel_load_detect_pipe tmp;
763

764
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
765
		      connector->base.id, connector->name,
766 767
		      force);

768 769 770 771
	/* Skip machines without VGA that falsely report hotplug events */
	if (dmi_check_system(intel_spurious_crt_detect))
		return connector_status_disconnected;

772
	intel_display_power_get(dev_priv, intel_encoder->power_domain);
773

774
	if (I915_HAS_HOTPLUG(dev_priv)) {
775 776 777 778
		/* We can not rely on the HPD pin always being correctly wired
		 * up, for example many KVM do not pass it through, and so
		 * only trust an assertion that the monitor is connected.
		 */
779 780
		if (intel_crt_detect_hotplug(connector)) {
			DRM_DEBUG_KMS("CRT detected via hotplug\n");
781 782
			status = connector_status_connected;
			goto out;
783
		} else
784
			DRM_DEBUG_KMS("CRT not detected via hotplug\n");
785 786
	}

787 788 789 790
	if (intel_crt_detect_ddc(connector)) {
		status = connector_status_connected;
		goto out;
	}
791

792 793 794 795
	/* Load detection is broken on HPD capable machines. Whoever wants a
	 * broken monitor (without edid) to work behind a broken kvm (that fails
	 * to have the right resistors for HP detection) needs to fix this up.
	 * For now just bail out. */
796
	if (I915_HAS_HOTPLUG(dev_priv) && !i915_modparams.load_detect_test) {
797 798 799
		status = connector_status_disconnected;
		goto out;
	}
800

801 802 803 804
	if (!force) {
		status = connector->status;
		goto out;
	}
805

806
	/* for pre-945g platforms use load detect */
807 808
	ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
	if (ret > 0) {
809 810
		if (intel_crt_detect_ddc(connector))
			status = connector_status_connected;
811
		else if (INTEL_GEN(dev_priv) < 4)
812 813
			status = intel_crt_load_detect(crt,
				to_intel_crtc(connector->state->crtc)->pipe);
814
		else if (i915_modparams.load_detect_test)
815
			status = connector_status_disconnected;
816 817
		else
			status = connector_status_unknown;
818 819
		intel_release_load_detect_pipe(connector, &tmp, ctx);
	} else if (ret == 0)
820
		status = connector_status_unknown;
821 822
	else if (ret < 0)
		status = ret;
823

824
out:
825
	intel_display_power_put(dev_priv, intel_encoder->power_domain);
826
	return status;
827 828 829 830 831 832 833 834 835 836
}

static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}

static int intel_crt_get_modes(struct drm_connector *connector)
{
837
	struct drm_device *dev = connector->dev;
838
	struct drm_i915_private *dev_priv = to_i915(dev);
839 840
	struct intel_crt *crt = intel_attached_crt(connector);
	struct intel_encoder *intel_encoder = &crt->base;
841
	int ret;
842
	struct i2c_adapter *i2c;
843

844
	intel_display_power_get(dev_priv, intel_encoder->power_domain);
845

846
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
847
	ret = intel_crt_ddc_get_modes(connector, i2c);
848
	if (ret || !IS_G4X(dev_priv))
849
		goto out;
850 851

	/* Try to probe digital port for output in DVI-I -> VGA mode. */
852
	i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
853 854 855
	ret = intel_crt_ddc_get_modes(connector, i2c);

out:
856
	intel_display_power_put(dev_priv, intel_encoder->power_domain);
857 858

	return ret;
859 860
}

861
void intel_crt_reset(struct drm_encoder *encoder)
862
{
863
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
864
	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
865

866
	if (INTEL_GEN(dev_priv) >= 5) {
867 868
		u32 adpa;

869
		adpa = I915_READ(crt->adpa_reg);
870 871
		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
		adpa |= ADPA_HOTPLUG_BITS;
872 873
		I915_WRITE(crt->adpa_reg, adpa);
		POSTING_READ(crt->adpa_reg);
874

875
		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
876
		crt->force_hotplug_required = 1;
877 878
	}

879 880
}

881 882 883 884 885 886
/*
 * Routines for controlling stuff on the analog port
 */

static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.fill_modes = drm_helper_probe_single_connector_modes,
887
	.late_register = intel_connector_register,
888
	.early_unregister = intel_connector_unregister,
889
	.destroy = intel_crt_destroy,
890
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
891
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
892 893 894
};

static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
895
	.detect_ctx = intel_crt_detect,
896 897 898 899 900
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
};

static const struct drm_encoder_funcs intel_crt_enc_funcs = {
901
	.reset = intel_crt_reset,
902
	.destroy = intel_encoder_destroy,
903 904
};

905
void intel_crt_init(struct drm_i915_private *dev_priv)
906 907
{
	struct drm_connector *connector;
908
	struct intel_crt *crt;
909
	struct intel_connector *intel_connector;
910 911
	i915_reg_t adpa_reg;
	u32 adpa;
912

913
	if (HAS_PCH_SPLIT(dev_priv))
914
		adpa_reg = PCH_ADPA;
915
	else if (IS_VALLEYVIEW(dev_priv))
916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936
		adpa_reg = VLV_ADPA;
	else
		adpa_reg = ADPA;

	adpa = I915_READ(adpa_reg);
	if ((adpa & ADPA_DAC_ENABLE) == 0) {
		/*
		 * On some machines (some IVB at least) CRT can be
		 * fused off, but there's no known fuse bit to
		 * indicate that. On these machine the ADPA register
		 * works normally, except the DAC enable bit won't
		 * take. So the only way to tell is attempt to enable
		 * it and see what happens.
		 */
		I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
			   ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
		if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
			return;
		I915_WRITE(adpa_reg, adpa);
	}

937 938
	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
	if (!crt)
939 940
		return;

941
	intel_connector = intel_connector_alloc();
942
	if (!intel_connector) {
943
		kfree(crt);
944 945 946 947
		return;
	}

	connector = &intel_connector->base;
948
	crt->connector = intel_connector;
949
	drm_connector_init(&dev_priv->drm, &intel_connector->base,
950 951
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

952
	drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
953
			 DRM_MODE_ENCODER_DAC, "CRT");
954

955
	intel_connector_attach_encoder(intel_connector, &crt->base);
956

957
	crt->base.type = INTEL_OUTPUT_ANALOG;
958
	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
959
	if (IS_I830(dev_priv))
960 961
		crt->base.crtc_mask = (1 << 0);
	else
962
		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
963

964
	if (IS_GEN2(dev_priv))
965 966 967
		connector->interlace_allowed = 0;
	else
		connector->interlace_allowed = 1;
968 969
	connector->doublescan_allowed = 0;

970
	crt->adpa_reg = adpa_reg;
971

972 973
	crt->base.power_domain = POWER_DOMAIN_PORT_CRT;

974
	if (I915_HAS_HOTPLUG(dev_priv) &&
975
	    !dmi_check_system(intel_spurious_crt_detect))
976
		crt->base.hpd_pin = HPD_CRT;
977

978
	if (HAS_DDI(dev_priv)) {
979
		crt->base.port = PORT_E;
980
		crt->base.get_config = hsw_crt_get_config;
981
		crt->base.get_hw_state = intel_ddi_get_hw_state;
982
		crt->base.compute_config = hsw_crt_compute_config;
983 984 985
		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
		crt->base.pre_enable = hsw_pre_enable_crt;
		crt->base.enable = hsw_enable_crt;
986
		crt->base.disable = hsw_disable_crt;
987
		crt->base.post_disable = hsw_post_disable_crt;
988
	} else {
989
		if (HAS_PCH_SPLIT(dev_priv)) {
990
			crt->base.compute_config = pch_crt_compute_config;
991 992 993
			crt->base.disable = pch_disable_crt;
			crt->base.post_disable = pch_post_disable_crt;
		} else {
994
			crt->base.compute_config = intel_crt_compute_config;
995 996
			crt->base.disable = intel_disable_crt;
		}
997
		crt->base.port = PORT_NONE;
998
		crt->base.get_config = intel_crt_get_config;
999
		crt->base.get_hw_state = intel_crt_get_hw_state;
1000
		crt->base.enable = intel_enable_crt;
1001
	}
1002
	intel_connector->get_hw_state = intel_connector_get_hw_state;
1003

1004 1005
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

1006
	if (!I915_HAS_HOTPLUG(dev_priv))
1007
		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1008

1009 1010 1011 1012 1013
	/*
	 * Configure the automatic hotplug detection stuff
	 */
	crt->force_hotplug_required = 0;

1014
	/*
1015 1016 1017
	 * TODO: find a proper way to discover whether we need to set the the
	 * polarity and link reversal bits or not, instead of relying on the
	 * BIOS.
1018
	 */
1019
	if (HAS_PCH_LPT(dev_priv)) {
1020 1021 1022
		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
				 FDI_RX_LINK_REVERSAL_OVERRIDE;

1023
		dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1024
	}
1025

1026
	intel_crt_reset(&crt->base.base);
1027
}