• Andrew Bresticker's avatar
    clk: tegra: Initialize UTMI PLL when enabling PLLU · 15d68e8c
    Andrew Bresticker authored
    Move the UTMI PLL initialization code form clk-tegra<chip>.c files into
    clk-pll.c. UTMI PLL was being configured and set in HW control right
    after registration. However, when the clock init_table is processed and
    child clks of PLLU are enabled, it will call in and enable PLLU as
    well, and initiate SW enabling sequence even though PLLU is already in
    HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.
    
    Doing the initialization once during pllu_enable means we configure it
    properly into HW control.
    
    A side effect of the commonization/localization of the UTMI PLL init
    code, is that it corrects some errors that were present for earlier
    generations. For instance, in clk-tegra124.c, it used to have:
    
        #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
    
    when the correct shift to use is present in the new version:
    
        #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
    
    which matches the Tegra124 TRM register definition.
    Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
    [rklein: Merged in some later fixes for potential deadlocks]
    Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
    [treding: coding style bike-shedding, remove unused variable]
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    15d68e8c
clk-tegra210.c 90.9 KB