The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK
frequency combined with the MCLK division and the digital filter
decimation rates, determines the sampling frequency. Along with
MCLK_DIV, the power mode is also configured according to datasheet
recommendations.

From user space, available sampling frequencies can be read. However,
it is not required for an exact value to be entered, since the driver
will look for the closest available match.

When the device configuration changes (for example, if the filter
decimation rate changes), a SYNC_IN pulse is required.
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>