• Kuogee Hsieh's avatar
    drm/msm/dp: Always clear mask bits to disable interrupts at dp_ctrl_reset_irq_ctrl() · 993a2adc
    Kuogee Hsieh authored
    dp_catalog_ctrl_reset() will software reset DP controller. But it will
    not reset programmable registers to default value. DP driver still have
    to clear mask bits to interrupt status registers to disable interrupts
    after software reset of controller.
    
    At current implementation, dp_ctrl_reset_irq_ctrl() will software reset dp
    controller but did not call dp_catalog_ctrl_enable_irq(false) to clear hpd
    related interrupt mask bits to disable hpd related interrupts due to it
    mistakenly think hpd related interrupt mask bits will be cleared by software
    reset of dp controller automatically. This mistake may cause system to crash
    during suspending procedure due to unexpected irq fired and trigger event
    thread to access dp controller registers with controller clocks are disabled.
    
    This patch fixes system crash during suspending problem by removing "enable"
    flag condition checking at dp_ctrl_reset_irq_ctrl() so that hpd related
    interrupt mask bits are cleared to prevent unexpected from happening.
    
    Changes in v2:
    -- add more details commit text
    
    Changes in v3:
    -- add synchrons_irq()
    -- add atomic_t suspended
    
    Changes in v4:
    -- correct Fixes's commit ID
    -- remove synchrons_irq()
    
    Changes in v5:
    -- revise commit text
    
    Changes in v6:
    -- add event_lock to protect "suspended"
    
    Changes in v7:
    -- delete "suspended" flag
    
    Fixes: 989ebe7b ("drm/msm/dp: do not initialize phy until plugin interrupt received")
    Signed-off-by: default avatarKuogee Hsieh <quic_khsieh@quicinc.com>
    Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
    Patchwork: https://patchwork.freedesktop.org/patch/486591/
    Link: https://lore.kernel.org/r/1652804494-19650-1-git-send-email-quic_khsieh@quicinc.comSigned-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
    993a2adc
dp_ctrl.c 53.8 KB