• Anson Huang's avatar
    clk: imx: correct pfdv2 gate_bit/vld_bit operations · a5a627c6
    Anson Huang authored
    The operations of pfdv2 gate_bit/valid_bit are incorrect,
    they are defined as u8 for bit offset, but gate_bit is
    actually assigned as mask which could be 32 bit long and
    it causes overflow, and vld_bit is assigned as bit offset
    based on incorrect gate_bit value, it causes incorrect
    pfd clock gate status in clock tree, this patch fixes the
    issue by assigning them as correct bit offset.
    
    Fixes: 9fcb6be3 ("clk: imx: add pfdv2 support")
    Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
    Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    a5a627c6
clk-pfdv2.c 3.93 KB