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Victor Goldenshtein authored
In addition to existing WCS PLL configuration add and enable also the coex PLL during init phase. This fixes boot failures due to silicon latchup in high temperature environment (>85c). Signed-off-by: Victor Goldenshtein <victorg@ti.com> Signed-off-by: Nadim Zubidat <nadimz@ti.com> Signed-off-by: Eliad Peller <eliad@wizery.com> Signed-off-by: Luciano Coelho <luciano.coelho@intel.com>
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