Commit 04a94bab authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (24 commits)
  [Blackfin] arch: import defines for BF547 -- it is just like the BF548, but no CAN
  [Blackfin] arch: fix build fails only include header files when enabled
  [Blackfin] arch: declare default INSTALL_PATH for Blackfin ports
  [Blackfin] arch: Encourage users to use the spidev character driver: Provide platform support
  [Blackfin] arch: Enable UART2 and UART3 for bf548
  [Blackfin] arch: Enable NET2272 on BF561-EZkit - remove request_mem_region
  [Blackfin] arch:Fix BUG [#3876] pfbutton test for BTN3 on bf533 don't show complete info
  [Blackfin] arch: remove duplicated definitions of the line discipline numbers N_* in asm-blackfin/termios.h
  [Blackfin] arch: fix building with mtd uclinux by putting the mtd_phys option into the function it actually gets used in
  [Blackfin] arch: simpler header and update dates
  [Blackfin] arch: move the init sections to the end of memory
  [Blackfin] arch: change the trace buffer control start/stop logic in the exception handlers
  [Blackfin] arch: fix typo in printk message
  [Blackfin] arch: this is an ezkit, not a stamp, so fixup the init function name
  [Blackfin] arch: add slightly better help text for CPLB_INFO
  [Blackfin] arch: Fix BUG - Enable ISP1362 driver to work ok with BF561
  [Blackfin] arch: Fix header file information
  [Blackfin] arch: Add Support for ISP1362
  [Blackfin] arch: add support for cmdline partitioning to the BF533-STAMP flash map driver and enable it as a module by default
  [Blackfin] arch: hook up set_irq_wake in Blackfin's irq code
  ...
parents 765cdb6c 920e526f
...@@ -544,7 +544,7 @@ config EXCPT_IRQ_SYSC_L1 ...@@ -544,7 +544,7 @@ config EXCPT_IRQ_SYSC_L1
default y default y
help help
If enabled, the entire ASM lowlevel exception and interrupt entry code If enabled, the entire ASM lowlevel exception and interrupt entry code
(STORE/RESTORE CONTEXT) is linked into L1 instruction memory. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency) (less latency)
config DO_IRQ_L1 config DO_IRQ_L1
...@@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE ...@@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE
depends on !SMP depends on !SMP
choice choice
prompt "Select PM Wakeup Event Source" prompt "Default Power Saving Mode"
default PM_WAKEUP_GPIO_BY_SIC_IWR
depends on PM depends on PM
help default PM_BFIN_SLEEP_DEEPER
If you have a GPIO already configured as input with the corresponding PORTx_MASK config PM_BFIN_SLEEP_DEEPER
bit set - "Specify Wakeup Event by SIC_IWR value" bool "Sleep Deeper"
help
Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
power dissipation by disabling the clock to the processor core (CCLK).
Furthermore, Standby sets the internal power supply voltage (VDDINT)
to 0.85 V to provide the greatest power savings, while preserving the
processor state.
The PLL and system clock (SCLK) continue to operate at a very low
frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
the SDRAM is put into Self Refresh Mode. Typically an external event
such as GPIO interrupt or RTC activity wakes up the processor.
Various Peripherals such as UART, SPORT, PPI may not function as
normal during Sleep Deeper, due to the reduced SCLK frequency.
When in the sleep mode, system DMA access to L1 memory is not supported.
config PM_BFIN_SLEEP
bool "Sleep"
help
Sleep Mode (High Power Savings) - The sleep mode reduces power
dissipation by disabling the clock to the processor core (CCLK).
The PLL and system clock (SCLK), however, continue to operate in
this mode. Typically an external event or RTC activity will wake
up the processor. When in the sleep mode,
system DMA access to L1 memory is not supported.
endchoice
config PM_WAKEUP_GPIO_BY_SIC_IWR
bool "Specify Wakeup Event by SIC_IWR value"
config PM_WAKEUP_BY_GPIO config PM_WAKEUP_BY_GPIO
bool "Cause Wakeup Event by GPIO" bool "Cause Wakeup Event by GPIO"
config PM_WAKEUP_GPIO_API
bool "Configure Wakeup Event by PM GPIO API"
endchoice
config PM_WAKEUP_SIC_IWR
hex "Wakeup Events (SIC_IWR)"
depends on PM_WAKEUP_GPIO_BY_SIC_IWR
default 0x8 if (BF537 || BF536 || BF534)
default 0x80 if (BF533 || BF532 || BF531)
default 0x80 if (BF54x)
default 0x80 if (BF52x)
config PM_WAKEUP_GPIO_NUMBER config PM_WAKEUP_GPIO_NUMBER
int "Wakeup GPIO number" int "Wakeup GPIO number"
......
...@@ -164,7 +164,7 @@ config DUAL_CORE_TEST_MODULE ...@@ -164,7 +164,7 @@ config DUAL_CORE_TEST_MODULE
config CPLB_INFO config CPLB_INFO
bool "Display the CPLB information" bool "Display the CPLB information"
help help
Display the CPLB information. Display the CPLB information via /proc/cplbinfo.
config ACCESS_CHECK config ACCESS_CHECK
bool "Check the user pointer address" bool "Check the user pointer address"
......
...@@ -119,6 +119,7 @@ archclean: ...@@ -119,6 +119,7 @@ archclean:
$(Q)$(MAKE) $(clean)=$(boot) $(Q)$(MAKE) $(clean)=$(boot)
INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage BOOT_TARGETS = vmImage
PHONY += $(BOOT_TARGETS) install PHONY += $(BOOT_TARGETS) install
......
...@@ -216,8 +216,6 @@ CONFIG_MEM_SIZE=128 ...@@ -216,8 +216,6 @@ CONFIG_MEM_SIZE=128
CONFIG_MEM_ADD_WIDTH=11 CONFIG_MEM_ADD_WIDTH=11
CONFIG_ENET_FLASH_PIN=0 CONFIG_ENET_FLASH_PIN=0
CONFIG_BOOT_LOAD=0x1000 CONFIG_BOOT_LOAD=0x1000
CONFIG_BFIN_SCRATCH_REG_RETN=y CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_RETE is not set
# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
...@@ -483,7 +481,7 @@ CONFIG_MTD=y ...@@ -483,7 +481,7 @@ CONFIG_MTD=y
# CONFIG_MTD_CONCAT is not set # CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y
# #
# User Modules And Translation Layers # User Modules And Translation Layers
...@@ -500,8 +498,8 @@ CONFIG_MTD_BLOCK=y ...@@ -500,8 +498,8 @@ CONFIG_MTD_BLOCK=y
# #
# RAM/ROM/Flash chip drivers # RAM/ROM/Flash chip drivers
# #
# CONFIG_MTD_CFI is not set CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m # CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set # CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_1=y
...@@ -515,8 +513,9 @@ CONFIG_MTD_CFI_I2=y ...@@ -515,8 +513,9 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set # CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set # CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set # CONFIG_MTD_ABSENT is not set
...@@ -526,6 +525,11 @@ CONFIG_MTD_ROM=m ...@@ -526,6 +525,11 @@ CONFIG_MTD_ROM=m
# #
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set # CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_BF5xx=m
CONFIG_BFIN_FLASH_BANK_0=0x7BB0
CONFIG_BFIN_FLASH_BANK_1=0x7BB0
CONFIG_BFIN_FLASH_BANK_2=0x7BB0
CONFIG_BFIN_FLASH_BANK_3=0x7BB0
# CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set # CONFIG_MTD_PLATRAM is not set
......
...@@ -104,6 +104,16 @@ int request_dma(unsigned int channel, char *device_id) ...@@ -104,6 +104,16 @@ int request_dma(unsigned int channel, char *device_id)
mutex_unlock(&(dma_ch[channel].dmalock)); mutex_unlock(&(dma_ch[channel].dmalock));
#ifdef CONFIG_BF54x
if (channel >= CH_UART2_RX && channel <= CH_UART3_TX &&
strncmp(device_id, "BFIN_UART", 9) == 0)
dma_ch[channel].regs->peripheral_map |=
(channel - CH_UART2_RX + 0xC);
else
dma_ch[channel].regs->peripheral_map |=
(channel - CH_UART2_RX + 0x6);
#endif
dma_ch[channel].device_id = device_id; dma_ch[channel].device_id = device_id;
dma_ch[channel].irq_callback = NULL; dma_ch[channel].irq_callback = NULL;
......
...@@ -186,7 +186,7 @@ static struct str_ident { ...@@ -186,7 +186,7 @@ static struct str_ident {
char name[RESOURCE_LABEL_SIZE]; char name[RESOURCE_LABEL_SIZE];
} str_ident[MAX_RESOURCES]; } str_ident[MAX_RESOURCES];
#ifdef CONFIG_PM #if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS]; static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)]; static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
...@@ -696,9 +696,8 @@ static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type) ...@@ -696,9 +696,8 @@ static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
return 0; return 0;
} }
u32 gpio_pm_setup(void) u32 bfin_pm_setup(void)
{ {
u32 sic_iwr = 0;
u16 bank, mask, i, gpio; u16 bank, mask, i, gpio;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
...@@ -723,7 +722,8 @@ u32 gpio_pm_setup(void) ...@@ -723,7 +722,8 @@ u32 gpio_pm_setup(void)
gpio = i; gpio = i;
while (mask) { while (mask) {
if (mask & 1) { if ((mask & 1) && (wakeup_flags_map[gpio] !=
PM_WAKE_IGNORE)) {
reserved_gpio_map[gpio_bank(gpio)] |= reserved_gpio_map[gpio_bank(gpio)] |=
gpio_bit(gpio); gpio_bit(gpio);
bfin_gpio_wakeup_type(gpio, bfin_gpio_wakeup_type(gpio,
...@@ -734,21 +734,17 @@ u32 gpio_pm_setup(void) ...@@ -734,21 +734,17 @@ u32 gpio_pm_setup(void)
mask >>= 1; mask >>= 1;
} }
sic_iwr |= 1 << bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
(sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)]; gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
} }
} }
AWA_DUMMY_READ(maskb_set); AWA_DUMMY_READ(maskb_set);
if (sic_iwr) return 0;
return sic_iwr;
else
return IWR_ENABLE_ALL;
} }
void gpio_pm_restore(void) void bfin_pm_restore(void)
{ {
u16 bank, mask, i; u16 bank, mask, i;
...@@ -768,7 +764,7 @@ void gpio_pm_restore(void) ...@@ -768,7 +764,7 @@ void gpio_pm_restore(void)
reserved_gpio_map[bank] = reserved_gpio_map[bank] =
gpio_bank_saved[bank].reserved; gpio_bank_saved[bank].reserved;
bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
} }
gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb; gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
......
...@@ -26,6 +26,10 @@ ...@@ -26,6 +26,10 @@
#include <asm/cplb.h> #include <asm/cplb.h>
#include <asm/cplbinit.h> #include <asm/cplbinit.h>
#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
#endif
struct cplb_entry icplb_tbl[MAX_CPLBS]; struct cplb_entry icplb_tbl[MAX_CPLBS];
struct cplb_entry dcplb_tbl[MAX_CPLBS]; struct cplb_entry dcplb_tbl[MAX_CPLBS];
......
...@@ -57,5 +57,5 @@ EXPORT_SYMBOL(init_task); ...@@ -57,5 +57,5 @@ EXPORT_SYMBOL(init_task);
* "init_task" linker map entry. * "init_task" linker map entry.
*/ */
union thread_union init_thread_union union thread_union init_thread_union
__attribute__ ((__section__(".data.init_task"))) = { __attribute__ ((__section__(".init_task.data"))) = {
INIT_THREAD_INFO(init_task)}; INIT_THREAD_INFO(init_task)};
This diff is collapsed.
...@@ -649,7 +649,7 @@ void dump_bfin_process(struct pt_regs *fp) ...@@ -649,7 +649,7 @@ void dump_bfin_process(struct pt_regs *fp)
if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
printk(KERN_NOTICE "HW Error context\n"); printk(KERN_NOTICE "HW Error context\n");
else if (context & 0x0020) else if (context & 0x0020)
printk(KERN_NOTICE "Defered Exception context\n"); printk(KERN_NOTICE "Deferred Exception context\n");
else if (context & 0x3FC0) else if (context & 0x3FC0)
printk(KERN_NOTICE "Interrupt context\n"); printk(KERN_NOTICE "Interrupt context\n");
else if (context & 0x4000) else if (context & 0x4000)
......
...@@ -41,6 +41,9 @@ _jiffies = _jiffies_64; ...@@ -41,6 +41,9 @@ _jiffies = _jiffies_64;
SECTIONS SECTIONS
{ {
. = CONFIG_BOOT_LOAD; . = CONFIG_BOOT_LOAD;
/* Neither the text, ro_data or bss section need to be aligned
* So pack them back to back
*/
.text : .text :
{ {
__text = .; __text = .;
...@@ -58,22 +61,25 @@ SECTIONS ...@@ -58,22 +61,25 @@ SECTIONS
*(__ex_table) *(__ex_table)
___stop___ex_table = .; ___stop___ex_table = .;
. = ALIGN(4);
__etext = .; __etext = .;
} }
RO_DATA(PAGE_SIZE) /* Just in case the first read only is a 32-bit access */
RO_DATA(4)
.bss :
{
. = ALIGN(4);
___bss_start = .;
*(.bss .bss.*)
*(COMMON)
___bss_stop = .;
}
.data : .data :
{ {
/* make sure the init_task is aligned to the
* kernel thread size so we can locate the kernel
* stack properly and quickly.
*/
__sdata = .; __sdata = .;
. = ALIGN(THREAD_SIZE); /* This gets done first, so the glob doesn't suck it in */
*(.data.init_task)
. = ALIGN(32); . = ALIGN(32);
*(.data.cacheline_aligned) *(.data.cacheline_aligned)
...@@ -81,10 +87,22 @@ SECTIONS ...@@ -81,10 +87,22 @@ SECTIONS
*(.data.*) *(.data.*)
CONSTRUCTORS CONSTRUCTORS
/* make sure the init_task is aligned to the
* kernel thread size so we can locate the kernel
* stack properly and quickly.
*/
. = ALIGN(THREAD_SIZE); . = ALIGN(THREAD_SIZE);
*(.init_task.data)
__edata = .; __edata = .;
} }
/* The init section should be last, so when we free it, it goes into
* the general memory pool, and (hopefully) will decrease fragmentation
* a tiny bit. The init section has a _requirement_ that it be
* PAGE_SIZE aligned
*/
. = ALIGN(PAGE_SIZE);
___init_begin = .; ___init_begin = .;
.init.text : .init.text :
...@@ -179,16 +197,7 @@ SECTIONS ...@@ -179,16 +197,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE); . = ALIGN(PAGE_SIZE);
___init_end = .; ___init_end = .;
.bss : __end =.;
{
. = ALIGN(4);
___bss_start = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
___bss_stop = .;
__end = .;
}
STABS_DEBUG STABS_DEBUG
......
...@@ -41,7 +41,9 @@ ...@@ -41,7 +41,9 @@
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/usb/sl811.h> #include <linux/usb/sl811.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h> #include <linux/usb/musb.h>
#endif
#include <asm/cplb.h> #include <asm/cplb.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/bfin5xx_spi.h> #include <asm/bfin5xx_spi.h>
...@@ -517,6 +519,14 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = { ...@@ -517,6 +519,14 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
.bits_per_word = 16, .bits_per_word = 16,
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = { static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \ #if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE) || defined(CONFIG_MTD_M25P80_MODULE)
...@@ -634,6 +644,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -634,6 +644,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_0, .mode = SPI_MODE_0,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
/* SPI controller data */ /* SPI controller data */
......
...@@ -34,7 +34,9 @@ ...@@ -34,7 +34,9 @@
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/flash.h> #include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h> #include <linux/usb/isp1362.h>
#endif
#include <linux/ata_platform.h> #include <linux/ata_platform.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <asm/dma.h> #include <asm/dma.h>
...@@ -134,6 +136,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { ...@@ -134,6 +136,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = { static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{ {
...@@ -168,6 +177,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -168,6 +177,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad1836_spi_chip_info, .controller_data = &ad1836_spi_chip_info,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
/* SPI (0) */ /* SPI (0) */
......
...@@ -226,6 +226,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = { ...@@ -226,6 +226,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = { static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{ {
...@@ -312,6 +319,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -312,6 +319,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_2, .mode = SPI_MODE_2,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
/* SPI (0) */ /* SPI (0) */
...@@ -423,9 +439,9 @@ static struct platform_device bfin_pata_device = { ...@@ -423,9 +439,9 @@ static struct platform_device bfin_pata_device = {
#include <linux/gpio_keys.h> #include <linux/gpio_keys.h>
static struct gpio_keys_button bfin_gpio_keys_table[] = { static struct gpio_keys_button bfin_gpio_keys_table[] = {
{BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"}, {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
{BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"}, {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
{BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"}, {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
}; };
static struct gpio_keys_platform_data bfin_gpio_keys_data = { static struct gpio_keys_platform_data bfin_gpio_keys_data = {
......
...@@ -487,6 +487,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { ...@@ -487,6 +487,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = { static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \ #if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE) || defined(CONFIG_MTD_M25P80_MODULE)
...@@ -593,6 +600,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -593,6 +600,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &spi_ad7877_chip_info, .controller_data = &spi_ad7877_chip_info,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
/* SPI controller data */ /* SPI controller data */
......
...@@ -37,7 +37,9 @@ ...@@ -37,7 +37,9 @@
#include <linux/spi/flash.h> #include <linux/spi/flash.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h> #include <linux/usb/musb.h>
#endif
#include <asm/bfin5xx_spi.h> #include <asm/bfin5xx_spi.h>
#include <asm/cplb.h> #include <asm/cplb.h>
#include <asm/dma.h> #include <asm/dma.h>
...@@ -420,6 +422,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { ...@@ -420,6 +422,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bf54x_spi_board_info[] __initdata = { static struct spi_board_info bf54x_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \ #if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE) || defined(CONFIG_MTD_M25P80_MODULE)
...@@ -445,6 +454,15 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = { ...@@ -445,6 +454,15 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
.controller_data = &spi_ad7877_chip_info, .controller_data = &spi_ad7877_chip_info,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
/* SPI (0) */ /* SPI (0) */
...@@ -631,7 +649,7 @@ static struct platform_device *ezkit_devices[] __initdata = { ...@@ -631,7 +649,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
&ezkit_flash_device, &ezkit_flash_device,
}; };
static int __init stamp_init(void) static int __init ezkit_init(void)
{ {
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
...@@ -644,4 +662,4 @@ static int __init stamp_init(void) ...@@ -644,4 +662,4 @@ static int __init stamp_init(void)
return 0; return 0;
} }
arch_initcall(stamp_init); arch_initcall(ezkit_init);
/* /*
* File: arch/blackfin/mach-bf561/dma.c * File: arch/blackfin/mach-bf548/dma.c
* Based on: * Based on:
* Author: * Author:
* *
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Description: This file contains the simple DMA Implementation for Blackfin * Description: This file contains the simple DMA Implementation for Blackfin
* *
* Modified: * Modified:
* Copyright 2004-2007 Analog Devices Inc. * Copyright 2004-2008 Analog Devices Inc.
* *
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
......
...@@ -92,6 +92,68 @@ void __exit bfin_isp1761_exit(void) ...@@ -92,6 +92,68 @@ void __exit bfin_isp1761_exit(void)
arch_initcall(bfin_isp1761_init); arch_initcall(bfin_isp1761_init);
#endif #endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
static struct resource isp1362_hcd_resources[] = {
{
.start = 0x2c060000,
.end = 0x2c060000,
.flags = IORESOURCE_MEM,
}, {
.start = 0x2c060004,
.end = 0x2c060004,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF8,
.end = IRQ_PF8,
.flags = IORESOURCE_IRQ,
},
};
static struct isp1362_platform_data isp1362_priv = {
.sel15Kres = 1,
.clknotstop = 0,
.oc_enable = 0,
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_connected = 0,
.no_power_switching = 1,
.power_switching_mode = 0,
};
static struct platform_device isp1362_hcd_device = {
.name = "isp1362-hcd",
.id = 0,
.dev = {
.platform_data = &isp1362_priv,
},
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
.resource = isp1362_hcd_resources,
};
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
static struct resource net2272_bfin_resources[] = {
{
.start = 0x2C000000,
.end = 0x2C000000 + 0x7F,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct platform_device net2272_bfin_device = {
.name = "net2272",
.id = -1,
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
.resource = net2272_bfin_resources,
};
#endif
/* /*
* USB-LAN EzExtender board * USB-LAN EzExtender board
* Driver needs to know address, irq and flag pin. * Driver needs to know address, irq and flag pin.
...@@ -204,6 +266,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { ...@@ -204,6 +266,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.bits_per_word = 16, .bits_per_word = 16,
}; };
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#endif #endif
/* SPI (0) */ /* SPI (0) */
...@@ -248,6 +317,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -248,6 +317,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad1836_spi_chip_info, .controller_data = &ad1836_spi_chip_info,
}, },
#endif #endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
}; };
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
...@@ -340,6 +418,10 @@ static struct platform_device *ezkit_devices[] __initdata = { ...@@ -340,6 +418,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
&ax88180_device, &ax88180_device,
#endif #endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
&net2272_bfin_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device, &bfin_spi0_device,
#endif #endif
...@@ -359,6 +441,11 @@ static struct platform_device *ezkit_devices[] __initdata = { ...@@ -359,6 +441,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
&i2c_gpio_device, &i2c_gpio_device,
#endif #endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
&ezkit_flash_device, &ezkit_flash_device,
}; };
......
...@@ -4,8 +4,6 @@ ...@@ -4,8 +4,6 @@
obj-y := \ obj-y := \
cache.o cacheinit.o entry.o \ cache.o cacheinit.o entry.o \
interrupt.o lock.o irqpanic.o arch_checks.o interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o dpmc.o obj-$(CONFIG_PM) += pm.o dpmc.o
...@@ -191,6 +191,9 @@ ENTRY(_sleep_mode) ...@@ -191,6 +191,9 @@ ENTRY(_sleep_mode)
call _test_pll_locked; call _test_pll_locked;
R0 = IWR_ENABLE(0); R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; call _set_sic_iwr;
P0.H = hi(PLL_CTL); P0.H = hi(PLL_CTL);
...@@ -237,6 +240,10 @@ ENTRY(_deep_sleep) ...@@ -237,6 +240,10 @@ ENTRY(_deep_sleep)
CLI R4; CLI R4;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; call _set_sic_iwr;
call _set_dram_srfs; call _set_dram_srfs;
...@@ -261,6 +268,9 @@ ENTRY(_deep_sleep) ...@@ -261,6 +268,9 @@ ENTRY(_deep_sleep)
call _test_pll_locked; call _test_pll_locked;
R0 = IWR_ENABLE(0); R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; call _set_sic_iwr;
P0.H = hi(PLL_CTL); P0.H = hi(PLL_CTL);
...@@ -286,7 +296,13 @@ ENTRY(_sleep_deeper) ...@@ -286,7 +296,13 @@ ENTRY(_sleep_deeper)
CLI R4; CLI R4;
P3 = R0; P3 = R0;
P4 = R1;
P5 = R2;
R0 = IWR_ENABLE(0); R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; call _set_sic_iwr;
call _set_dram_srfs; /* Set SDRAM Self Refresh */ call _set_dram_srfs; /* Set SDRAM Self Refresh */
...@@ -327,6 +343,8 @@ ENTRY(_sleep_deeper) ...@@ -327,6 +343,8 @@ ENTRY(_sleep_deeper)
call _test_pll_locked; call _test_pll_locked;
R0 = P3; R0 = P3;
R1 = P4;
R3 = P5;
call _set_sic_iwr; /* Set Awake from IDLE */ call _set_sic_iwr; /* Set Awake from IDLE */
P0.H = hi(PLL_CTL); P0.H = hi(PLL_CTL);
...@@ -340,6 +358,9 @@ ENTRY(_sleep_deeper) ...@@ -340,6 +358,9 @@ ENTRY(_sleep_deeper)
call _test_pll_locked; call _test_pll_locked;
R0 = IWR_ENABLE(0); R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; /* Set Awake from IDLE PLL */ call _set_sic_iwr; /* Set Awake from IDLE PLL */
P0.H = hi(VR_CTL); P0.H = hi(VR_CTL);
...@@ -417,14 +438,23 @@ ENTRY(_unset_dram_srfs) ...@@ -417,14 +438,23 @@ ENTRY(_unset_dram_srfs)
RTS; RTS;
ENTRY(_set_sic_iwr) ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
P0.H = hi(SIC_IWR0); P0.H = hi(SIC_IWR0);
P0.L = lo(SIC_IWR0); P0.L = lo(SIC_IWR0);
P1.H = hi(SIC_IWR1);
P1.L = lo(SIC_IWR1);
[P1] = R1;
#if defined(CONFIG_BF54x)
P1.H = hi(SIC_IWR2);
P1.L = lo(SIC_IWR2);
[P1] = R2;
#endif
#else #else
P0.H = hi(SIC_IWR); P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR); P0.L = lo(SIC_IWR);
#endif #endif
[P0] = R0; [P0] = R0;
SSYNC; SSYNC;
RTS; RTS;
......
...@@ -121,6 +121,7 @@ ENTRY(_ex_icplb_miss) ...@@ -121,6 +121,7 @@ ENTRY(_ex_icplb_miss)
(R7:6,P5:4) = [sp++]; (R7:6,P5:4) = [sp++];
ASTAT = [sp++]; ASTAT = [sp++];
SAVE_ALL_SYS SAVE_ALL_SYS
DEBUG_HWTRACE_SAVE(p5, r7)
#ifdef CONFIG_MPU #ifdef CONFIG_MPU
R0 = SEQSTAT; R0 = SEQSTAT;
R1 = SP; R1 = SP;
...@@ -132,14 +133,13 @@ ENTRY(_ex_icplb_miss) ...@@ -132,14 +133,13 @@ ENTRY(_ex_icplb_miss)
#else #else
call __cplb_hdr; call __cplb_hdr;
#endif #endif
DEBUG_START_HWTRACE(p5, r7) DEBUG_HWTRACE_RESTORE(p5, r7)
RESTORE_ALL_SYS RESTORE_ALL_SYS
SP = EX_SCRATCH_REG; SP = EX_SCRATCH_REG;
rtx; rtx;
ENDPROC(_ex_icplb_miss) ENDPROC(_ex_icplb_miss)
ENTRY(_ex_syscall) ENTRY(_ex_syscall)
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++]; (R7:6,P5:4) = [sp++];
ASTAT = [sp++]; ASTAT = [sp++];
raise 15; /* invoked by TRAP #0, for sys call */ raise 15; /* invoked by TRAP #0, for sys call */
...@@ -178,7 +178,6 @@ ENTRY(_ex_single_step) ...@@ -178,7 +178,6 @@ ENTRY(_ex_single_step)
ENDPROC(_ex_single_step) ENDPROC(_ex_single_step)
ENTRY(_bfin_return_from_exception) ENTRY(_bfin_return_from_exception)
DEBUG_START_HWTRACE(p5, r7)
#if ANOMALY_05000257 #if ANOMALY_05000257
R7=LC0; R7=LC0;
LC0=R7; LC0=R7;
...@@ -200,10 +199,9 @@ ENTRY(_handle_bad_cplb) ...@@ -200,10 +199,9 @@ ENTRY(_handle_bad_cplb)
* need to make a CPLB exception look like a normal exception * need to make a CPLB exception look like a normal exception
*/ */
DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS RESTORE_ALL_SYS
[--sp] = ASTAT; [--sp] = ASTAT;
[--sp] = (R7:6, P5:4); [--sp] = (R7:6,P5:4);
ENTRY(_ex_replaceable) ENTRY(_ex_replaceable)
nop; nop;
...@@ -253,7 +251,6 @@ ENTRY(_ex_trap_c) ...@@ -253,7 +251,6 @@ ENTRY(_ex_trap_c)
R6 = SEQSTAT; R6 = SEQSTAT;
[P5] = R6; [P5] = R6;
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++]; (R7:6,P5:4) = [sp++];
ASTAT = [sp++]; ASTAT = [sp++];
SP = EX_SCRATCH_REG; SP = EX_SCRATCH_REG;
...@@ -382,8 +379,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ ...@@ -382,8 +379,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
sp.h = _exception_stack_top; sp.h = _exception_stack_top;
/* Try to deal with syscalls quickly. */ /* Try to deal with syscalls quickly. */
[--sp] = ASTAT; [--sp] = ASTAT;
[--sp] = (R7:6, P5:4); [--sp] = (R7:6,P5:4);
DEBUG_STOP_HWTRACE(p5, r7)
r7 = SEQSTAT; /* reason code is in bit 5:0 */ r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE); r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE); r6.h = hi(SEQSTAT_EXCAUSE);
......
This diff is collapsed.
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001 * Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
* *
* Created: 2001 * Created: 2001
* Description: Power management for the bfin * Description: Blackfin power management
* *
* Modified: Nicolas Pitre - PXA250 support * Modified: Nicolas Pitre - PXA250 support
* Copyright (c) 2002 Monta Vista Software, Inc. * Copyright (c) 2002 Monta Vista Software, Inc.
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
* Copyright (c) 2002 Monta Vista Software, Inc. * Copyright (c) 2002 Monta Vista Software, Inc.
* Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610 * Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
* Copyright 2004 * Copyright 2004
* Copyright 2004-2006 Analog Devices Inc. * Copyright 2004-2008 Analog Devices Inc.
* *
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
...@@ -67,42 +67,30 @@ void bfin_pm_suspend_standby_enter(void) ...@@ -67,42 +67,30 @@ void bfin_pm_suspend_standby_enter(void)
gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
#endif #endif
#if defined(CONFIG_PM_WAKEUP_BY_GPIO) || defined(CONFIG_PM_WAKEUP_GPIO_API) u32 flags;
{
u32 flags;
local_irq_save(flags); local_irq_save(flags);
bfin_pm_setup();
sleep_deeper(gpio_pm_setup()); /*Goto Sleep*/ #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
gpio_pm_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
#else #else
bfin_write_SIC_IWR(IWR_ENABLE_ALL); sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#endif #endif
local_irq_restore(flags); bfin_pm_restore();
}
#endif
#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x # ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL); bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
# else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
# endif # endif
#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */ #else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
#endif
local_irq_restore(flags);
} }
/* /*
......
...@@ -138,8 +138,7 @@ void __init mem_init(void) ...@@ -138,8 +138,7 @@ void __init mem_init(void)
start_mem = PAGE_ALIGN(start_mem); start_mem = PAGE_ALIGN(start_mem);
max_mapnr = num_physpages = MAP_NR(high_memory); max_mapnr = num_physpages = MAP_NR(high_memory);
printk(KERN_INFO "Kernel managed physical pages: %lu\n", printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages);
num_physpages);
/* This will put all memory onto the freelists. */ /* This will put all memory onto the freelists. */
totalram_pages = free_all_bootmem(); totalram_pages = free_all_bootmem();
...@@ -153,8 +152,7 @@ void __init mem_init(void) ...@@ -153,8 +152,7 @@ void __init mem_init(void)
/* do not count in kernel image between _rambase and _ramstart */ /* do not count in kernel image between _rambase and _ramstart */
reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
PAGE_SHIFT;
#endif #endif
codek = (_etext - _stext) >> 10; codek = (_etext - _stext) >> 10;
...@@ -163,11 +161,9 @@ void __init mem_init(void) ...@@ -163,11 +161,9 @@ void __init mem_init(void)
printk(KERN_INFO printk(KERN_INFO
"Memory available: %luk/%luk RAM, " "Memory available: %luk/%luk RAM, "
"(%uk init code, %uk kernel code, " "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
"%uk data, %uk dma, %uk reserved)\n",
(unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10, (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
initk, codek, datak, DMA_UNCACHED_REGION >> 10, initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
(reservedpages << (PAGE_SHIFT-10)));
/* Initialize the blackfin L1 Memory. */ /* Initialize the blackfin L1 Memory. */
l1sram_init(); l1sram_init();
......
...@@ -70,6 +70,7 @@ extern void program_IAR(void); ...@@ -70,6 +70,7 @@ extern void program_IAR(void);
extern void evt14_softirq(void); extern void evt14_softirq(void);
extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
extern char fixed_code_start; extern char fixed_code_start;
...@@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[]; ...@@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[];
extern unsigned long table_start, table_end; extern unsigned long table_start, table_end;
extern unsigned long bfin_sic_iwr[];
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
extern struct file_operations dpmc_fops; extern struct file_operations dpmc_fops;
extern char _start; extern char _start;
......
/************************************************************ /************************************************************
*
* Copyright (C) 2004, Analog Devices. All Rights Reserved * Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
* *
* FILE bfin5xx_spi.h * FILE bfin5xx_spi.h
* PROGRAMMER(S): Luke Yang (Analog Devices Inc.) * PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
...@@ -32,42 +32,6 @@ ...@@ -32,42 +32,6 @@
#define SPI_BAUD_OFF 0x14 #define SPI_BAUD_OFF 0x14
#define SPI_SHAW_OFF 0x18 #define SPI_SHAW_OFF 0x18
#define CMD_SPI_OUT_ENABLE 1
#define CMD_SPI_SET_BAUDRATE 2
#define CMD_SPI_SET_POLAR 3
#define CMD_SPI_SET_PHASE 4
#define CMD_SPI_SET_MASTER 5
#define CMD_SPI_SET_SENDOPT 6
#define CMD_SPI_SET_RECVOPT 7
#define CMD_SPI_SET_ORDER 8
#define CMD_SPI_SET_LENGTH16 9
#define CMD_SPI_GET_STAT 11
#define CMD_SPI_GET_CFG 12
#define CMD_SPI_SET_CSAVAIL 13
#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
#define CMD_SPI_SET_CSLOW 15 /* CS avail */
#define CMD_SPI_MISO_ENABLE 16
#define CMD_SPI_SET_CSENABLE 17
#define CMD_SPI_SET_CSDISABLE 18
#define CMD_SPI_SET_TRIGGER_MODE 19
#define CMD_SPI_SET_TRIGGER_SENSE 20
#define CMD_SPI_SET_TRIGGER_EDGE 21
#define CMD_SPI_SET_TRIGGER_LEVEL 22
#define CMD_SPI_SET_TIME_SPS 23
#define CMD_SPI_SET_TIME_SAMPLES 24
#define CMD_SPI_GET_SYSTEMCLOCK 25
#define CMD_SPI_SET_WRITECONTINUOUS 26
#define CMD_SPI_SET_SKFS 27
#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
#define SPI_DEFAULT_BARD 0x0100
#define SPI0_IRQ_NUM IRQ_SPI
#define SPI_ERR_TRIG -1
#define BIT_CTL_ENABLE 0x4000 #define BIT_CTL_ENABLE 0x4000
#define BIT_CTL_OPENDRAIN 0x2000 #define BIT_CTL_OPENDRAIN 0x2000
...@@ -148,6 +112,10 @@ ...@@ -148,6 +112,10 @@
#define CFG_SPI_CS6VALUE 6 #define CFG_SPI_CS6VALUE 6
#define CFG_SPI_CS7VALUE 7 #define CFG_SPI_CS7VALUE 7
#define CMD_SPI_SET_BAUDRATE 2
#define CMD_SPI_GET_SYSTEMCLOCK 25
#define CMD_SPI_SET_WRITECONTINUOUS 26
/* device.platform_data for SSP controller devices */ /* device.platform_data for SSP controller devices */
struct bfin5xx_spi_master { struct bfin5xx_spi_master {
u16 num_chipselect; u16 num_chipselect;
......
...@@ -53,10 +53,10 @@ unsigned long get_pll_status(void); ...@@ -53,10 +53,10 @@ unsigned long get_pll_status(void);
void change_baud(int baud); void change_baud(int baud);
void fullon_mode(void); void fullon_mode(void);
void active_mode(void); void active_mode(void);
void sleep_mode(u32 sic_iwr); void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void deep_sleep(u32 sic_iwr); void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void hibernate_mode(u32 sic_iwr); void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void sleep_deeper(u32 sic_iwr); void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void program_wdog_timer(unsigned long); void program_wdog_timer(unsigned long);
void unmask_wdog_wakeup_evt(void); void unmask_wdog_wakeup_evt(void);
void clear_wdog_wakeup_evt(void); void clear_wdog_wakeup_evt(void);
......
...@@ -376,16 +376,19 @@ struct gpio_port_t { ...@@ -376,16 +376,19 @@ struct gpio_port_t {
#endif #endif
#ifdef CONFIG_PM #ifdef CONFIG_PM
unsigned int bfin_pm_setup(void);
void bfin_pm_restore(void);
#ifndef CONFIG_BF54x
#define PM_WAKE_RISING 0x1 #define PM_WAKE_RISING 0x1
#define PM_WAKE_FALLING 0x2 #define PM_WAKE_FALLING 0x2
#define PM_WAKE_HIGH 0x4 #define PM_WAKE_HIGH 0x4
#define PM_WAKE_LOW 0x8 #define PM_WAKE_LOW 0x8
#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
#define PM_WAKE_IGNORE 0xF0
int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
void gpio_pm_wakeup_free(unsigned gpio); void gpio_pm_wakeup_free(unsigned gpio);
unsigned int gpio_pm_setup(void);
void gpio_pm_restore(void);
struct gpio_port_s { struct gpio_port_s {
unsigned short data; unsigned short data;
...@@ -409,6 +412,7 @@ struct gpio_port_s { ...@@ -409,6 +412,7 @@ struct gpio_port_s {
unsigned short fer; unsigned short fer;
unsigned short reserved; unsigned short reserved;
}; };
#endif /*CONFIG_BF54x*/
#endif /*CONFIG_PM*/ #endif /*CONFIG_PM*/
/*********************************************************** /***********************************************************
......
...@@ -46,6 +46,10 @@ ...@@ -46,6 +46,10 @@
#include "defBF544.h" #include "defBF544.h"
#endif #endif
#ifdef CONFIG_BF547
#include "defBF547.h"
#endif
#ifdef CONFIG_BF548 #ifdef CONFIG_BF548
#include "defBF548.h" #include "defBF548.h"
#endif #endif
...@@ -58,10 +62,12 @@ ...@@ -58,10 +62,12 @@
#ifdef CONFIG_BF542 #ifdef CONFIG_BF542
#include "cdefBF542.h" #include "cdefBF542.h"
#endif #endif
#ifdef CONFIG_BF544 #ifdef CONFIG_BF544
#include "cdefBF544.h" #include "cdefBF544.h"
#endif #endif
#ifdef CONFIG_BF547
#include "cdefBF547.h"
#endif
#ifdef CONFIG_BF548 #ifdef CONFIG_BF548
#include "cdefBF548.h" #include "cdefBF548.h"
#endif #endif
......
This diff is collapsed.
This diff is collapsed.
...@@ -1010,9 +1010,9 @@ ...@@ -1010,9 +1010,9 @@
#define DMA_READY 0x1 /* DMA Ready */ #define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */ #define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */ #define FIFOEMPTY 0x4 /* FIFO Empty */
#define COMPLETE 0x8 /* DMA Complete */ #define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */ #define HSHK 0x10 /* Host Handshake */
#define TIMEOUT 0x20 /* Host Timeout */ #define HSTIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */ #define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */ #define DMA_DIR 0x100 /* DMA Direction */
......
...@@ -51,9 +51,13 @@ ...@@ -51,9 +51,13 @@
#define CH_PIXC_OVERLAY 16 #define CH_PIXC_OVERLAY 16
#define CH_PIXC_OUTPUT 17 #define CH_PIXC_OUTPUT 17
#define CH_SPORT2_RX 18 #define CH_SPORT2_RX 18
#define CH_UART2_RX 18
#define CH_SPORT2_TX 19 #define CH_SPORT2_TX 19
#define CH_UART2_TX 19
#define CH_SPORT3_RX 20 #define CH_SPORT3_RX 20
#define CH_UART3_RX 20
#define CH_SPORT3_TX 21 #define CH_SPORT3_TX 21
#define CH_UART3_TX 21
#define CH_SDH 22 #define CH_SDH 22
#define CH_NFC 22 #define CH_NFC 22
#define CH_SPI2 23 #define CH_SPI2 23
......
...@@ -99,9 +99,13 @@ Events (highest priority) EMU 0 ...@@ -99,9 +99,13 @@ Events (highest priority) EMU 0
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
...@@ -421,9 +425,13 @@ Events (highest priority) EMU 0 ...@@ -421,9 +425,13 @@ Events (highest priority) EMU 0
/* IAR4 BIT FILEDS */ /* IAR4 BIT FILEDS */
#define IRQ_CAN0_ERR_POS 0 #define IRQ_CAN0_ERR_POS 0
#define IRQ_SPORT2_RX_POS 4 #define IRQ_SPORT2_RX_POS 4
#define IRQ_UART2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8 #define IRQ_SPORT2_TX_POS 8
#define IRQ_UART2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12 #define IRQ_SPORT3_RX_POS 12
#define IRQ_UART3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16 #define IRQ_SPORT3_TX_POS 16
#define IRQ_UART3_TX_POS 16
#define IRQ_EPPI1_POS 20 #define IRQ_EPPI1_POS 20
#define IRQ_EPPI2_POS 24 #define IRQ_EPPI2_POS 24
#define IRQ_SPI1_POS 28 #define IRQ_SPI1_POS 28
......
...@@ -49,4 +49,24 @@ ...@@ -49,4 +49,24 @@
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
#define SIC_IAR0 SICA_IAR0
#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
#endif /* _MACH_BLACKFIN_H_ */ #endif /* _MACH_BLACKFIN_H_ */
...@@ -39,24 +39,6 @@ struct termio { ...@@ -39,24 +39,6 @@ struct termio {
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
/* line disciplines */
#define N_TTY 0
#define N_SLIP 1
#define N_MOUSE 2
#define N_PPP 3
#define N_STRIP 4
#define N_AX25 5
#define N_X25 6 /* X.25 async */
#define N_6PACK 7
#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
#define N_R3964 9 /* Reserved for Simatic R3964 module */
#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
#define N_HDLC 13 /* synchronous HDLC */
#define N_SYNC_PPP 14 /* synchronous PPP */
#define N_HCI 15 /* Bluetooth HCI UART */
#ifdef __KERNEL__ #ifdef __KERNEL__
/* intr=^C quit=^\ erase=del kill=^U /* intr=^C quit=^\ erase=del kill=^U
......
...@@ -46,42 +46,47 @@ extern unsigned long software_trace_buff[]; ...@@ -46,42 +46,47 @@ extern unsigned long software_trace_buff[];
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg)
#define trace_buffer_stop(preg, dreg) \ #define trace_buffer_stop(preg, dreg) \
preg.L = LO(TBUFCTL); \ preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \ preg.H = HI(TBUFCTL); \
dreg = 0x1; \ dreg = 0x1; \
[preg] = dreg; [preg] = dreg;
#define trace_buffer_start(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = BFIN_TRACE_ON; \
[preg] = dreg;
#define trace_buffer_init(preg, dreg) \ #define trace_buffer_init(preg, dreg) \
preg.L = LO(TBUFCTL); \ preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \ preg.H = HI(TBUFCTL); \
dreg = BFIN_TRACE_INIT; \ dreg = BFIN_TRACE_INIT; \
[preg] = dreg; [preg] = dreg;
#define trace_buffer_save(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = [preg]; \
[sp++] = dreg; \
dreg = 0x1; \
[preg] = dreg;
#define trace_buffer_restore(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = [sp--]; \
[preg] = dreg;
#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#define trace_buffer_stop(preg, dreg) #define trace_buffer_stop(preg, dreg)
#define trace_buffer_start(preg, dreg)
#define trace_buffer_init(preg, dreg) #define trace_buffer_init(preg, dreg)
#define trace_buffer_save(preg, dreg)
#define trace_buffer_restore(preg, dreg)
#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ #endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) # define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) # define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
#else #else
# define DEBUG_START_HWTRACE(preg, dreg) # define DEBUG_HWTRACE_SAVE(preg, dreg)
# define DEBUG_STOP_HWTRACE(preg, dreg) # define DEBUG_HWTRACE_RESTORE(preg, dreg)
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
......
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