Commit 0ba82994 authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher

igb: Move ITR related data into work container within the q_vector

This change moves information related to interrupt throttle rate
configuration into a separate q_vector sub-structure called a work
container. A similar change has already been made for ixgbe and this work
is based off of that.
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarAaron Brown  <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 866cff06
...@@ -409,6 +409,9 @@ ...@@ -409,6 +409,9 @@
#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
/* Extended Interrupt Cause Set */ /* Extended Interrupt Cause Set */
/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
/* Transmit Descriptor Control */ /* Transmit Descriptor Control */
/* Enable the counting of descriptors still to be processed. */ /* Enable the counting of descriptors still to be processed. */
......
...@@ -42,8 +42,11 @@ ...@@ -42,8 +42,11 @@
struct igb_adapter; struct igb_adapter;
/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ /* Interrupt defines */
#define IGB_START_ITR 648 #define IGB_START_ITR 648 /* ~6000 ints/sec */
#define IGB_4K_ITR 980
#define IGB_20K_ITR 196
#define IGB_70K_ITR 56
/* TX/RX descriptor defines */ /* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD 256 #define IGB_DEFAULT_TXD 256
...@@ -175,16 +178,23 @@ struct igb_rx_queue_stats { ...@@ -175,16 +178,23 @@ struct igb_rx_queue_stats {
u64 alloc_failed; u64 alloc_failed;
}; };
struct igb_ring_container {
struct igb_ring *ring; /* pointer to linked list of rings */
unsigned int total_bytes; /* total bytes processed this int */
unsigned int total_packets; /* total packets processed this int */
u16 work_limit; /* total work allowed per interrupt */
u8 count; /* total number of rings in vector */
u8 itr; /* current ITR setting for ring */
};
struct igb_q_vector { struct igb_q_vector {
struct igb_adapter *adapter; /* backlink */ struct igb_adapter *adapter; /* backlink */
struct igb_ring *rx_ring; int cpu; /* CPU for DCA */
struct igb_ring *tx_ring; u32 eims_value; /* EIMS mask value */
struct napi_struct napi;
u32 eims_value; struct igb_ring_container rx, tx;
u16 cpu;
u16 tx_work_limit;
struct napi_struct napi;
int numa_node; int numa_node;
u16 itr_val; u16 itr_val;
...@@ -215,9 +225,6 @@ struct igb_ring { ...@@ -215,9 +225,6 @@ struct igb_ring {
u16 next_to_clean ____cacheline_aligned_in_smp; u16 next_to_clean ____cacheline_aligned_in_smp;
u16 next_to_use; u16 next_to_use;
unsigned int total_bytes;
unsigned int total_packets;
union { union {
/* TX */ /* TX */
struct { struct {
......
...@@ -2013,8 +2013,8 @@ static int igb_set_coalesce(struct net_device *netdev, ...@@ -2013,8 +2013,8 @@ static int igb_set_coalesce(struct net_device *netdev,
for (i = 0; i < adapter->num_q_vectors; i++) { for (i = 0; i < adapter->num_q_vectors; i++) {
struct igb_q_vector *q_vector = adapter->q_vector[i]; struct igb_q_vector *q_vector = adapter->q_vector[i];
q_vector->tx_work_limit = adapter->tx_work_limit; q_vector->tx.work_limit = adapter->tx_work_limit;
if (q_vector->rx_ring) if (q_vector->rx.ring)
q_vector->itr_val = adapter->rx_itr_setting; q_vector->itr_val = adapter->rx_itr_setting;
else else
q_vector->itr_val = adapter->tx_itr_setting; q_vector->itr_val = adapter->tx_itr_setting;
......
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