Commit 1c2e1fd1 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'omap-fixes-for-v3.4-rc3' of...

Merge tag 'omap-fixes-for-v3.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Fix regression for bad uart muxing and oops when PM is not set.
Revert one softreset regression and few other minor fixes.

* tag 'omap-fixes-for-v3.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP1: DMTIMER: fix broken timer clock source selection
  ARM: OMAP: serial: Fix the ocp smart idlemode handling bug
  ARM: OMAP2+: UART: Fix incorrect population of default uart pads
  ARM: OMAP: sram: fix BUG in dpll code for !PM case
  ARM: OMAP2/3: VENC hwmods: Remove OCPIF_SWSUP_IDLE flag from VENC slave interface
  ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status"
  ARM: OMAP2+: hwmod: add softreset delay field and OMAP4 data
  ARM: OMAP1: mux: add missing include
parents 888073d4 6aaec67d
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <mach/hardware.h>
#include <plat/mux.h> #include <plat/mux.h>
......
...@@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev, ...@@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
int n = (pdev->id - 1) << 1; int n = (pdev->id - 1) << 1;
u32 l; u32 l;
l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
l |= source << n; l |= source << n;
__raw_writel(l, MOD_CONF_CTRL_1); omap_writel(l, MOD_CONF_CTRL_1);
return 0; return 0;
} }
......
...@@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh) ...@@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
goto dis_opt_clks; goto dis_opt_clks;
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
if (oh->class->sysc->srst_udelay)
udelay(oh->class->sysc->srst_udelay);
if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
omap_test_timeout((omap_hwmod_read(oh, omap_test_timeout((omap_hwmod_read(oh,
oh->class->sysc->syss_offs) oh->class->sysc->syss_offs)
...@@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) ...@@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
*/ */
int omap_hwmod_softreset(struct omap_hwmod *oh) int omap_hwmod_softreset(struct omap_hwmod *oh)
{ {
if (!oh) u32 v;
int ret;
if (!oh || !(oh->_sysc_cache))
return -EINVAL; return -EINVAL;
return _ocp_softreset(oh); v = oh->_sysc_cache;
ret = _set_softreset(oh, &v);
if (ret)
goto error;
_write_sysconfig(v, oh);
error:
return ret;
} }
/** /**
......
...@@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { ...@@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} }
}, },
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
......
...@@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { ...@@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
.slave = &omap2430_dss_venc_hwmod, .slave = &omap2430_dss_venc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_venc_addrs, .addr = omap2_dss_venc_addrs,
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
......
...@@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { ...@@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} }
}, },
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
......
...@@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { ...@@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
.rev_offs = 0x0000, .rev_offs = 0x0000,
.sysc_offs = 0x0010, .sysc_offs = 0x0010,
/*
* ISS needs 100 OCP clk cycles delay after a softreset before
* accessing sysconfig again.
* The lowest frequency at the moment for L3 bus is 100 MHz, so
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
*
* TODO: Indicate errata when available.
*/
.srst_udelay = 2,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
......
...@@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev) ...@@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
static void omap_uart_set_smartidle(struct platform_device *pdev) static void omap_uart_set_smartidle(struct platform_device *pdev)
{ {
struct omap_device *od = to_omap_device(pdev); struct omap_device *od = to_omap_device(pdev);
u8 idlemode;
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
} }
#else #else
...@@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {} ...@@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
#endif /* CONFIG_PM */ #endif /* CONFIG_PM */
#ifdef CONFIG_OMAP_MUX #ifdef CONFIG_OMAP_MUX
static struct omap_device_pad default_uart1_pads[] __initdata = {
{
.name = "uart1_cts.uart1_cts",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart1_rts.uart1_rts",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart1_tx.uart1_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart1_rx.uart1_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_uart2_pads[] __initdata = {
{
.name = "uart2_cts.uart2_cts",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart2_rts.uart2_rts",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart2_tx.uart2_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart2_rx.uart2_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_uart3_pads[] __initdata = {
{
.name = "uart3_cts_rctx.uart3_cts_rctx",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart3_rts_sd.uart3_rts_sd",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart3_tx_irtx.uart3_tx_irtx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart3_rx_irrx.uart3_rx_irrx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
{
.name = "gpmc_wait2.uart4_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "gpmc_wait3.uart4_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
},
};
static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
{
.name = "uart4_tx.uart4_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart4_rx.uart4_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
},
};
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
{ {
switch (bdata->id) {
case 0:
bdata->pads = default_uart1_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
break;
case 1:
bdata->pads = default_uart2_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
break;
case 2:
bdata->pads = default_uart3_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
break;
case 3:
if (cpu_is_omap44xx()) {
bdata->pads = default_omap4_uart4_pads;
bdata->pads_cnt =
ARRAY_SIZE(default_omap4_uart4_pads);
} else if (cpu_is_omap3630()) {
bdata->pads = default_omap36xx_uart4_pads;
bdata->pads_cnt =
ARRAY_SIZE(default_omap36xx_uart4_pads);
}
break;
default:
break;
}
} }
#else #else
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
......
...@@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields { ...@@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
* @rev_offs: IP block revision register offset (from module base addr) * @rev_offs: IP block revision register offset (from module base addr)
* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
* @syss_offs: OCP_SYSSTATUS register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
* @srst_udelay: Delay needed after doing a softreset in usecs
* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
* @clockact: the default value of the module CLOCKACTIVITY bits * @clockact: the default value of the module CLOCKACTIVITY bits
...@@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig { ...@@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
u16 sysc_offs; u16 sysc_offs;
u16 syss_offs; u16 syss_offs;
u16 sysc_flags; u16 sysc_flags;
struct omap_hwmod_sysc_fields *sysc_fields;
u8 srst_udelay;
u8 idlemodes; u8 idlemodes;
u8 clockact; u8 clockact;
struct omap_hwmod_sysc_fields *sysc_fields;
}; };
/** /**
......
...@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, ...@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
sdrc_actim_ctrl_b_1, sdrc_mr_1); sdrc_actim_ctrl_b_1, sdrc_mr_1);
} }
#ifdef CONFIG_PM
void omap3_sram_restore_context(void) void omap3_sram_restore_context(void)
{ {
omap_sram_ceil = omap_sram_base + omap_sram_size; omap_sram_ceil = omap_sram_base + omap_sram_size;
...@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void) ...@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
omap3_sram_configure_core_dpll_sz); omap3_sram_configure_core_dpll_sz);
omap_push_sram_idle(); omap_push_sram_idle();
} }
#endif /* CONFIG_PM */
#endif /* CONFIG_ARCH_OMAP3 */
static inline int omap34xx_sram_init(void) static inline int omap34xx_sram_init(void)
{ {
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
omap3_sram_restore_context(); omap3_sram_restore_context();
#endif
return 0; return 0;
} }
#else
static inline int omap34xx_sram_init(void)
{
return 0;
}
#endif /* CONFIG_ARCH_OMAP3 */
static inline int am33xx_sram_init(void) static inline int am33xx_sram_init(void)
{ {
......
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