Commit 262fc784 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'versatile-for-v5.9' of...

Merge tag 'versatile-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt

Versatile DTS changes for the v5.9 kernel cycle, essentially
just a single patch fixing up the node names for schema.

* tag 'versatile-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: dts: arm-realview: Align L2 cache-controller nodename with dtschema

Link: https://lore.kernel.org/r/CACRpkdbkM9ZmuG2FnBmO7upcJfnqq2oSLDCFDXC5b3K+dtps9Q@mail.gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3b796abd f7f7a8f4
...@@ -59,7 +59,7 @@ intc_second: interrupt-controller@10040000 { ...@@ -59,7 +59,7 @@ intc_second: interrupt-controller@10040000 {
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
}; };
L2: l2-cache { L2: cache-controller {
compatible = "arm,l220-cache"; compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>; reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
......
...@@ -323,7 +323,7 @@ intc_dc1176: interrupt-controller@10120000 { ...@@ -323,7 +323,7 @@ intc_dc1176: interrupt-controller@10120000 {
<0x10120000 0x100>; <0x10120000 0x100>;
}; };
L2: l2-cache { L2: cache-controller {
compatible = "arm,l220-cache"; compatible = "arm,l220-cache";
reg = <0x10110000 0x1000>; reg = <0x10110000 0x1000>;
interrupt-parent = <&intc_dc1176>; interrupt-parent = <&intc_dc1176>;
......
...@@ -92,7 +92,7 @@ intc_tc11mp: interrupt-controller@1f000100 { ...@@ -92,7 +92,7 @@ intc_tc11mp: interrupt-controller@1f000100 {
<0x1f000100 0x100>; <0x1f000100 0x100>;
}; };
L2: l2-cache { L2: cache-controller {
compatible = "arm,l220-cache"; compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>; reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>; interrupt-parent = <&intc_tc11mp>;
......
...@@ -60,7 +60,7 @@ CPU1: cpu@1 { ...@@ -60,7 +60,7 @@ CPU1: cpu@1 {
}; };
}; };
L2: l2-cache { L2: cache-controller {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x1f002000 0x1000>; reg = <0x1f002000 0x1000>;
cache-unified; cache-unified;
......
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