Commit 2b55915d authored by Conor Dooley's avatar Conor Dooley

riscv: dts: microchip: mpfs: remove bogus card-detect-delay

Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
        From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.

Fixes: bc47b221 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107e ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 72a05748
...@@ -100,7 +100,6 @@ &mmc { ...@@ -100,7 +100,6 @@ &mmc {
disable-wp; disable-wp;
cap-sd-highspeed; cap-sd-highspeed;
cap-mmc-highspeed; cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v; mmc-ddr-1_8v;
mmc-hs200-1_8v; mmc-hs200-1_8v;
sd-uhs-sdr12; sd-uhs-sdr12;
......
...@@ -70,7 +70,6 @@ &mmc { ...@@ -70,7 +70,6 @@ &mmc {
disable-wp; disable-wp;
cap-sd-highspeed; cap-sd-highspeed;
cap-mmc-highspeed; cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v; mmc-ddr-1_8v;
mmc-hs200-1_8v; mmc-hs200-1_8v;
sd-uhs-sdr12; sd-uhs-sdr12;
......
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