Skip to content

L
linux
Commit 406ca449 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge tag 'renesas-dt2-for-v4.5' of... 

Merge tag 'renesas-dt2-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Second Round of Renesas ARM Based SoC DT Updates for v4.5" from Simon Horman:

* sh73a0, r8a7740: Add L2 cache-controller node
* r8a7791, r8a7794: remove deprecated #gpio-range-cells
* r8a7793: Add DU support and enable for VGA port
* r8a7790: switch console back to scif0
* alt: Correct ether and scif2 pinmux
* koelsch: Correct hdmi pinmux
* silk, lager, porter, bockw: Move SPI FLASH partitions to subnode
* bockw: Add schi0 pinmux

* tag 'renesas-dt2-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
  ARM: shmobile: alt: Correct ether pfc
  ARM: shmobile: alt: Correct scif2 pfc
  ARM: shmobile: silk: Move SPI FLASH partitions to subnode
  ARM: shmobile: lager: Move SPI FLASH partitions to subnode
  ARM: shmobile: porter: Move SPI FLASH partitions to subnode
  ARM: shmobile: bockw: Move SPI FLASH partition to subnode
  ARM: shmobile: r8a7791: koelsch: Fix pinmux for HDMI
  ARM: shmobile: r8a7794: remove deprecated #gpio-range-cells from dtsi
  ARM: shmobile: r8a7791: remove deprecated #gpio-range-cells from dtsi
  ARM: shmobile: r8a7793: Add DU node to device tree
  ARM: shmobile: r8a7794: alt: Enable PFC DU for the VGA port
  ARM: shmobile: bockw dts: define sdhi0 pins with pull-ups
  ARM: shmobile: r8a7790: switch console back to scif0
parents 6da06083 c8d9fdbe
Hide whitespace changes
Inline Side-by-side
Showing with 150 additions and 66 deletions
arch/arm/boot/dts/r8a7740.dtsi
View file @ 406ca449
...@@ -26,6 +26,7 @@ cpu@0 { ...@@ -26,6 +26,7 @@ cpu@0 {
reg = <0x0>; reg = <0x0>;
clock-frequency = <800000000>; clock-frequency = <800000000>;
power-domains = <&pd_a3sm>; power-domains = <&pd_a3sm>;
next-level-cache = <&L2>;
}; };
}; };
...@@ -37,6 +38,18 @@ gic: interrupt-controller@c2800000 { ...@@ -37,6 +38,18 @@ gic: interrupt-controller@c2800000 {
<0xc2000000 0x1000>; <0xc2000000 0x1000>;
}; };
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xf0100000 0x1000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_a3sm>;
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
arm,shared-override;
cache-unified;
cache-level = <2>;
};
dbsc3: memory-controller@fe400000 { dbsc3: memory-controller@fe400000 {
compatible = "renesas,dbsc3-r8a7740"; compatible = "renesas,dbsc3-r8a7740";
reg = <0xfe400000 0x400>; reg = <0xfe400000 0x400>;
......
arch/arm/boot/dts/r8a7778-bockw.dts
View file @ 406ca449
...@@ -137,10 +137,14 @@ mmc_pins: mmc { ...@@ -137,10 +137,14 @@ mmc_pins: mmc {
}; };
sdhi0_pins: sd0 { sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
"sdhi0_cd";
renesas,function = "sdhi0"; renesas,function = "sdhi0";
}; };
sdhi0_pup_pins: sd0_pup {
renesas,groups = "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
bias-pull-up;
};
hspi0_pins: hspi0 { hspi0_pins: hspi0 {
renesas,groups = "hspi0_a"; renesas,groups = "hspi0_a";
...@@ -169,7 +173,7 @@ vin1_pins: vin1 { ...@@ -169,7 +173,7 @@ vin1_pins: vin1 {
}; };
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>; vmmc-supply = <&fixedregulator3v3>;
...@@ -184,16 +188,19 @@ &hspi0 { ...@@ -184,16 +188,19 @@ &hspi0 {
status = "okay"; status = "okay";
flash: flash@0 { flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl008k", "jedec,spi-nor"; compatible = "spansion,s25fl008k", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <104000000>; spi-max-frequency = <104000000>;
m25p,fast-read; m25p,fast-read;
partition@0 { partitions {
label = "data(spi)"; #address-cells = <1>;
reg = <0x00000000 0x00100000>; #size-cells = <1>;
partition@0 {
label = "data(spi)";
reg = <0x00000000 0x00100000>;
};
}; };
}; };
}; };
......
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 406ca449
...@@ -47,13 +47,13 @@ / { ...@@ -47,13 +47,13 @@ / {
compatible = "renesas,lager", "renesas,r8a7790"; compatible = "renesas,lager", "renesas,r8a7790";
aliases { aliases {
serial0 = &scifa0; serial0 = &scif0;
serial1 = &scifa1; serial1 = &scifa1;
}; };
chosen { chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = &scifa0; stdout-path = &scif0;
}; };
memory@40000000 { memory@40000000 {
...@@ -296,9 +296,9 @@ du_pins: du { ...@@ -296,9 +296,9 @@ du_pins: du {
renesas,function = "du"; renesas,function = "du";
}; };
scifa0_pins: serial0 { scif0_pins: serial0 {
renesas,groups = "scifa0_data"; renesas,groups = "scif0_data";
renesas,function = "scifa0"; renesas,function = "scif0";
}; };
ether_pins: ether { ether_pins: ether {
...@@ -439,8 +439,6 @@ &qspi { ...@@ -439,8 +439,6 @@ &qspi {
status = "okay"; status = "okay";
flash: flash@0 { flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl512s", "jedec,spi-nor"; compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <30000000>; spi-max-frequency = <30000000>;
...@@ -450,25 +448,30 @@ flash: flash@0 { ...@@ -450,25 +448,30 @@ flash: flash@0 {
spi-cpol; spi-cpol;
m25p,fast-read; m25p,fast-read;
partition@0 { partitions {
label = "loader"; #address-cells = <1>;
reg = <0x00000000 0x00040000>; #size-cells = <1>;
read-only;
}; partition@0 {
partition@40000 { label = "loader";
label = "user"; reg = <0x00000000 0x00040000>;
reg = <0x00040000 0x00400000>; read-only;
read-only; };
}; partition@40000 {
partition@440000 { label = "user";
label = "flash"; reg = <0x00040000 0x00400000>;
reg = <0x00440000 0x03bc0000>; read-only;
};
partition@440000 {
label = "flash";
reg = <0x00440000 0x03bc0000>;
};
}; };
}; };
}; };
&scifa0 { &scif0 {
pinctrl-0 = <&scifa0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 406ca449
...@@ -326,7 +326,7 @@ i2c2_pins: i2c2 { ...@@ -326,7 +326,7 @@ i2c2_pins: i2c2 {
}; };
du_pins: du { du_pins: du {
renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0"; renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du"; renesas,function = "du";
}; };
......
arch/arm/boot/dts/r8a7791-porter.dts
View file @ 406ca449
...@@ -192,8 +192,6 @@ &qspi { ...@@ -192,8 +192,6 @@ &qspi {
status = "okay"; status = "okay";
flash@0 { flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl512s", "jedec,spi-nor"; compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <30000000>; spi-max-frequency = <30000000>;
...@@ -201,19 +199,24 @@ flash@0 { ...@@ -201,19 +199,24 @@ flash@0 {
spi-rx-bus-width = <4>; spi-rx-bus-width = <4>;
m25p,fast-read; m25p,fast-read;
partition@0 { partitions {
label = "loader_prg"; #address-cells = <1>;
reg = <0x00000000 0x00040000>; #size-cells = <1>;
read-only;
}; partition@0 {
partition@40000 { label = "loader_prg";
label = "user_prg"; reg = <0x00000000 0x00040000>;
reg = <0x00040000 0x00400000>; read-only;
read-only; };
}; partition@40000 {
partition@440000 { label = "user_prg";
label = "flash_fs"; reg = <0x00040000 0x00400000>;
reg = <0x00440000 0x03bc0000>; read-only;
};
partition@440000 {
label = "flash_fs";
reg = <0x00440000 0x03bc0000>;
};
}; };
}; };
}; };
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 406ca449
...@@ -509,7 +509,6 @@ i2c8: i2c@e6510000 { ...@@ -509,7 +509,6 @@ i2c8: i2c@e6510000 {
pfc: pfc@e6060000 { pfc: pfc@e6060000 {
compatible = "renesas,pfc-r8a7791"; compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>; reg = <0 0xe6060000 0 0x250>;
#gpio-range-cells = <3>;
}; };
mmcif0: mmc@ee200000 { mmcif0: mmc@ee200000 {
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ 406ca449
...@@ -344,6 +344,36 @@ qspi: spi@e6b10000 { ...@@ -344,6 +344,36 @@ qspi: spi@e6b10000 {
status = "disabled"; status = "disabled";
}; };
du: display@feb00000 {
compatible = "renesas,du-r8a7793";
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
reg-names = "du", "lvds.0";
interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
<0 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_DU0>,
<&mstp7_clks R8A7793_CLK_DU1>,
<&mstp7_clks R8A7793_CLK_LVDS0>;
clock-names = "du.0", "du.1", "lvds.0";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
};
};
};
};
clocks { clocks {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
......
arch/arm/boot/dts/r8a7794-alt.dts
View file @ 406ca449
...@@ -80,6 +80,8 @@ x13_clk: x13-clock { ...@@ -80,6 +80,8 @@ x13_clk: x13-clock {
}; };
&du { &du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay"; status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>, clocks = <&mstp7_clks R8A7794_CLK_DU0>,
...@@ -101,6 +103,11 @@ &extal_clk { ...@@ -101,6 +103,11 @@ &extal_clk {
}; };
&pfc { &pfc {
du_pins: du {
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
renesas,function = "du";
};
scif2_pins: serial2 { scif2_pins: serial2 {
renesas,groups = "scif2_data"; renesas,groups = "scif2_data";
renesas,function = "scif2"; renesas,function = "scif2";
...@@ -111,9 +118,9 @@ ether_pins: ether { ...@@ -111,9 +118,9 @@ ether_pins: ether {
renesas,function = "eth"; renesas,function = "eth";
}; };
ether_b_pins: ether { phy1_pins: phy1 {
renesas,groups = "eth_link_b", "eth_mdio_b", "eth_rmii_b"; renesas,groups = "intc_irq8";
renesas,function = "eth"; renesas,function = "intc";
}; };
i2c1_pins: i2c1 { i2c1_pins: i2c1 {
...@@ -132,6 +139,9 @@ &cmt0 { ...@@ -132,6 +139,9 @@ &cmt0 {
}; };
&ether { &ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>; phy-handle = <&phy1>;
renesas,ether-link-active-low; renesas,ether-link-active-low;
status = "okay"; status = "okay";
...@@ -182,5 +192,8 @@ vin0ep: endpoint { ...@@ -182,5 +192,8 @@ vin0ep: endpoint {
}; };
&scif2 { &scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
arch/arm/boot/dts/r8a7794-silk.dts
View file @ 406ca449
...@@ -194,8 +194,6 @@ &qspi { ...@@ -194,8 +194,6 @@ &qspi {
status = "okay"; status = "okay";
flash@0 { flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl512s", "jedec,spi-nor"; compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <30000000>; spi-max-frequency = <30000000>;
...@@ -205,19 +203,24 @@ flash@0 { ...@@ -205,19 +203,24 @@ flash@0 {
spi-cpha; spi-cpha;
m25p,fast-read; m25p,fast-read;
partition@0 { partitions {
label = "loader"; #address-cells = <1>;
reg = <0x00000000 0x00040000>; #size-cells = <1>;
read-only;
}; partition@0 {
partition@40000 { label = "loader";
label = "user"; reg = <0x00000000 0x00040000>;
reg = <0x00040000 0x00400000>; read-only;
read-only; };
}; partition@40000 {
partition@440000 { label = "user";
label = "flash"; reg = <0x00040000 0x00400000>;
reg = <0x00440000 0x03bc0000>; read-only;
};
partition@440000 {
label = "flash";
reg = <0x00440000 0x03bc0000>;
};
}; };
}; };
}; };
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ 406ca449
...@@ -217,7 +217,6 @@ irqc0: interrupt-controller@e61c0000 { ...@@ -217,7 +217,6 @@ irqc0: interrupt-controller@e61c0000 {
pfc: pin-controller@e6060000 { pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7794"; compatible = "renesas,pfc-r8a7794";
reg = <0 0xe6060000 0 0x11c>; reg = <0 0xe6060000 0 0x11c>;
#gpio-range-cells = <3>;
}; };
dmac0: dma-controller@e6700000 { dmac0: dma-controller@e6700000 {
......
arch/arm/boot/dts/sh73a0.dtsi
View file @ 406ca449
...@@ -28,6 +28,7 @@ cpu@0 { ...@@ -28,6 +28,7 @@ cpu@0 {
reg = <0>; reg = <0>;
clock-frequency = <1196000000>; clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
...@@ -35,6 +36,7 @@ cpu@1 { ...@@ -35,6 +36,7 @@ cpu@1 {
reg = <1>; reg = <1>;
clock-frequency = <1196000000>; clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
}; };
}; };
...@@ -53,6 +55,18 @@ gic: interrupt-controller@f0001000 { ...@@ -53,6 +55,18 @@ gic: interrupt-controller@f0001000 {
<0xf0000100 0x100>; <0xf0000100 0x100>;
}; };
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xf0100000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_a3sm>;
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
arm,shared-override;
cache-unified;
cache-level = <2>;
};
sbsc2: memory-controller@fb400000 { sbsc2: memory-controller@fb400000 {
compatible = "renesas,sbsc-sh73a0"; compatible = "renesas,sbsc-sh73a0";
reg = <0xfb400000 0x400>; reg = <0xfb400000 0x400>;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7