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Commit 40e7a399 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'v5.16-rockchip-dts64-2' of... 

Merge tag 'v5.16-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Idle-cooling information for rk3399, rk356x additions (tsadc resets,
i2s, spdif, pwm), rk3368 powerdomains, fixes to make gpio subnodes
compliant with the new pinctrl yaml binding and addition of the
chassis-type for the non-sbc devices.

* tag 'v5.16-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add idle cooling devices to rk3399
  arm64: dts: rockchip: fix resets in tsadc node for rk356x
  arm64: dts: rockchip: Add analog audio on Quartz64
  arm64: dts: rockchip: Add i2s1 on rk356x
  arm64: dts: rockchip: change gpio nodenames
  arm64: dts: rockchip: add 'chassis-type' property
  arm64: dts: rockchip: add powerdomains to rk3368
  dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yaml
  arm64: dts: rockchip: enable spdif on Quartz64 A
  arm64: dts: rockchip: add spdif node to rk356x
  arm64: dts: rockchip: add pwm nodes for rk3568

Link: https://lore.kernel.org/r/4536780.s7XYDJ6uuW@philSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7b27dc27 43f9699b
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Showing with 489 additions and 27 deletions
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
View file @ 40e7a399
......@@ -22,6 +22,7 @@ select:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
......@@ -35,6 +36,7 @@ properties:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- const: syscon
......
arch/arm64/boot/dts/rockchip/px30.dtsi
View file @ 40e7a399
......@@ -1338,7 +1338,7 @@ pinctrl: pinctrl {
#size-cells = <2>;
ranges;
gpio0: gpio0@ff040000 {
gpio0: gpio@ff040000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff040000 0x0 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1350,7 +1350,7 @@ gpio0: gpio0@ff040000 {
#interrupt-cells = <2>;
};
gpio1: gpio1@ff250000 {
gpio1: gpio@ff250000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1362,7 +1362,7 @@ gpio1: gpio1@ff250000 {
#interrupt-cells = <2>;
};
gpio2: gpio2@ff260000 {
gpio2: gpio@ff260000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1374,7 +1374,7 @@ gpio2: gpio2@ff260000 {
#interrupt-cells = <2>;
};
gpio3: gpio3@ff270000 {
gpio3: gpio@ff270000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff270000 0x0 0x100>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View file @ 40e7a399
......@@ -790,7 +790,7 @@ pinctrl: pinctrl {
#size-cells = <2>;
ranges;
gpio0: gpio0@ff220000 {
gpio0: gpio@ff220000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff220000 0x0 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
......@@ -801,7 +801,7 @@ gpio0: gpio0@ff220000 {
#interrupt-cells = <2>;
};
gpio1: gpio1@ff230000 {
gpio1: gpio@ff230000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff230000 0x0 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
......@@ -812,7 +812,7 @@ gpio1: gpio1@ff230000 {
#interrupt-cells = <2>;
};
gpio2: gpio2@ff240000 {
gpio2: gpio@ff240000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff240000 0x0 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
......@@ -823,7 +823,7 @@ gpio2: gpio2@ff240000 {
#interrupt-cells = <2>;
};
gpio3: gpio3@ff250000 {
gpio3: gpio@ff250000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
......@@ -834,7 +834,7 @@ gpio3: gpio3@ff250000 {
#interrupt-cells = <2>;
};
gpio4: gpio4@ff260000 {
gpio4: gpio@ff260000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View file @ 40e7a399
......@@ -1014,7 +1014,7 @@ pinctrl: pinctrl {
#size-cells = <2>;
ranges;
gpio0: gpio0@ff210000 {
gpio0: gpio@ff210000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff210000 0x0 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1027,7 +1027,7 @@ gpio0: gpio0@ff210000 {
#interrupt-cells = <2>;
};
gpio1: gpio1@ff220000 {
gpio1: gpio@ff220000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff220000 0x0 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1040,7 +1040,7 @@ gpio1: gpio1@ff220000 {
#interrupt-cells = <2>;
};
gpio2: gpio2@ff230000 {
gpio2: gpio@ff230000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff230000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1053,7 +1053,7 @@ gpio2: gpio2@ff230000 {
#interrupt-cells = <2>;
};
gpio3: gpio3@ff240000 {
gpio3: gpio@ff240000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff240000 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 40e7a399
......@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
......@@ -615,6 +616,115 @@ mbox: mbox@ff6b0000 {
status = "disabled";
};
pmu: power-management@ff730000 {
compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
compatible = "rockchip,rk3368-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Note: Although SCLK_* are the working clocks
* of device without including on the NOC, needed for
* synchronous reset.
*
* The clocks on the which NOC:
* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
* ACLK_RGA is on ACLK_RGA_NIU.
* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
*
* Which clock are device clocks:
* clocks devices
* *_IEP IEP:Image Enhancement Processor
* *_ISP ISP:Image Signal Processing
* *_VIP VIP:Video Input Processor
* *_VOP* VOP:Visual Output Processor
* *_RGA RGA
* *_EDP* EDP
* *_DPHY* LVDS
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
power-domain@RK3368_PD_VIO {
reg = <RK3368_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
<&cru ACLK_VIP>,
<&cru ACLK_RGA>,
<&cru ACLK_VOP>,
<&cru ACLK_VOP_IEP>,
<&cru DCLK_VOP>,
<&cru HCLK_IEP>,
<&cru HCLK_ISP>,
<&cru HCLK_RGA>,
<&cru HCLK_VIP>,
<&cru HCLK_VOP>,
<&cru HCLK_VIO_HDCPMMU>,
<&cru PCLK_EDP_CTRL>,
<&cru PCLK_HDMI_CTRL>,
<&cru PCLK_HDCP>,
<&cru PCLK_ISP>,
<&cru PCLK_VIP>,
<&cru PCLK_DPHYRX>,
<&cru PCLK_DPHYTX0>,
<&cru PCLK_MIPI_CSI>,
<&cru PCLK_MIPI_DSI0>,
<&cru SCLK_VOP0_PWM>,
<&cru SCLK_EDP_24M>,
<&cru SCLK_EDP>,
<&cru SCLK_HDCP>,
<&cru SCLK_ISP>,
<&cru SCLK_RGA>,
<&cru SCLK_HDMI_CEC>,
<&cru SCLK_HDMI_HDCP>;
pm_qos = <&qos_iep>,
<&qos_isp_r0>,
<&qos_isp_r1>,
<&qos_isp_w0>,
<&qos_isp_w1>,
<&qos_vip>,
<&qos_vop>,
<&qos_rga_r>,
<&qos_rga_w>;
#power-domain-cells = <0>;
};
/*
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
power-domain@RK3368_PD_VIDEO {
reg = <RK3368_PD_VIDEO>;
clocks = <&cru ACLK_VIDEO>,
<&cru HCLK_VIDEO>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_vpu_r>,
<&qos_vpu_w>;
#power-domain-cells = <0>;
};
/*
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
power-domain@RK3368_PD_GPU_1 {
reg = <RK3368_PD_GPU_1>;
clocks = <&cru ACLK_GPU_CFG>,
<&cru ACLK_GPU_MEM>,
<&cru SCLK_GPU_CORE>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
};
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
......@@ -711,6 +821,7 @@ iep_mmu: iommu@ff900800 {
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
......@@ -723,6 +834,7 @@ isp_mmu: iommu@ff914000 {
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3368_PD_VIO>;
rockchip,disable-mmu-reset;
status = "disabled";
};
......@@ -733,6 +845,7 @@ vop_mmu: iommu@ff930300 {
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
......@@ -759,6 +872,71 @@ vpu_mmu: iommu@ff9a0800 {
status = "disabled";
};
qos_iep: qos@ffad0000 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0000 0x0 0x20>;
};
qos_isp_r0: qos@ffad0080 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0080 0x0 0x20>;
};
qos_isp_r1: qos@ffad0100 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0100 0x0 0x20>;
};
qos_isp_w0: qos@ffad0180 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0180 0x0 0x20>;
};
qos_isp_w1: qos@ffad0200 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0200 0x0 0x20>;
};
qos_vip: qos@ffad0280 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0280 0x0 0x20>;
};
qos_vop: qos@ffad0300 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0300 0x0 0x20>;
};
qos_rga_r: qos@ffad0380 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0380 0x0 0x20>;
};
qos_rga_w: qos@ffad0400 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffad0400 0x0 0x20>;
};
qos_hevc_r: qos@ffae0000 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffae0000 0x0 0x20>;
};
qos_vpu_r: qos@ffae0100 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffae0100 0x0 0x20>;
};
qos_vpu_w: qos@ffae0180 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffae0180 0x0 0x20>;
};
qos_gpu: qos@ffaf0000 {
compatible = "rockchip,rk3368-qos", "syscon";
reg = <0x0 0xffaf0000 0x0 0x20>;
};
efuse256: efuse@ffb00000 {
compatible = "rockchip,rk3368-efuse";
reg = <0x0 0xffb00000 0x0 0x20>;
......@@ -797,7 +975,7 @@ pinctrl: pinctrl {
#size-cells = <0x2>;
ranges;
gpio0: gpio0@ff750000 {
gpio0: gpio@ff750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff750000 0x0 0x100>;
clocks = <&cru PCLK_GPIO0>;
......@@ -810,7 +988,7 @@ gpio0: gpio0@ff750000 {
#interrupt-cells = <0x2>;
};
gpio1: gpio1@ff780000 {
gpio1: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO1>;
......@@ -823,7 +1001,7 @@ gpio1: gpio1@ff780000 {
#interrupt-cells = <0x2>;
};
gpio2: gpio2@ff790000 {
gpio2: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
......@@ -836,7 +1014,7 @@ gpio2: gpio2@ff790000 {
#interrupt-cells = <0x2>;
};
gpio3: gpio3@ff7a0000 {
gpio3: gpio@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7a0000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
......
arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
View file @ 40e7a399
......@@ -16,6 +16,7 @@ / {
"google,bob-rev7", "google,bob-rev6",
"google,bob-rev5", "google,bob-rev4",
"google,bob", "google,gru", "rockchip,rk3399";
chassis-type = "convertible";
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51";
......
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
View file @ 40e7a399
......@@ -24,6 +24,7 @@ / {
"google,kevin-rev9", "google,kevin-rev8",
"google,kevin-rev7", "google,kevin-rev6",
"google,kevin", "google,gru", "rockchip,rk3399";
chassis-type = "convertible";
/* Power tree */
......
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View file @ 40e7a399
......@@ -8,6 +8,8 @@
#include "rk3399-gru.dtsi"
/{
chassis-type = "tablet";
/* Power tree */
/* ppvar_sys children, sorted by name */
......
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View file @ 40e7a399
......@@ -17,6 +17,7 @@
/ {
model = "Pine64 Pinebook Pro";
compatible = "pine64,pinebook-pro", "rockchip,rk3399";
chassis-type = "laptop";
aliases {
mmc0 = &sdio0;
......
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ 40e7a399
......@@ -124,6 +124,12 @@ cpu_b0: cpu@100 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
cpu_b1: cpu@101 {
......@@ -136,6 +142,12 @@ cpu_b1: cpu@101 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
idle-states {
......@@ -2026,7 +2038,7 @@ pinctrl: pinctrl {
#size-cells = <2>;
ranges;
gpio0: gpio0@ff720000 {
gpio0: gpio@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
......@@ -2039,7 +2051,7 @@ gpio0: gpio0@ff720000 {
#interrupt-cells = <0x2>;
};
gpio1: gpio1@ff730000 {
gpio1: gpio@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
......@@ -2052,7 +2064,7 @@ gpio1: gpio1@ff730000 {
#interrupt-cells = <0x2>;
};
gpio2: gpio2@ff780000 {
gpio2: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
......@@ -2065,7 +2077,7 @@ gpio2: gpio2@ff780000 {
#interrupt-cells = <0x2>;
};
gpio3: gpio3@ff788000 {
gpio3: gpio@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
......@@ -2078,7 +2090,7 @@ gpio3: gpio3@ff788000 {
#interrupt-cells = <0x2>;
};
gpio4: gpio4@ff790000 {
gpio4: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
......
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View file @ 40e7a399
......@@ -58,6 +58,39 @@ led-diy {
};
};
rk817-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK817";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817>;
};
};
spdif_dit: spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif_sound: spdif-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_dit>;
};
};
vcc12v_dcin: vcc12v_dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
......@@ -197,13 +230,17 @@ rk817: pmic@20 {
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
wakeup-source;
#clock-cells = <1>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
......@@ -392,6 +429,16 @@ regulator-state-mem {
};
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
......@@ -458,6 +505,10 @@ &sdmmc0 {
status = "okay";
};
&spdif {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
......
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View file @ 40e7a399
......@@ -263,6 +263,50 @@ uart0: serial@fdd50000 {
status = "disabled";
};
pwm0: pwm@fdd70000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70000 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm0m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@fdd70010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70010 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm1m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@fdd70020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70020 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm2m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@fdd70030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70030 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pmu: power-management@fdd90000 {
compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
reg = <0x0 0xfdd90000 0x0 0x1000>;
......@@ -564,6 +608,45 @@ sdhci: mmc@fe310000 {
status = "disabled";
};
spdif: spdif@fe460000 {
compatible = "rockchip,rk3568-spdif";
reg = <0x0 0xfe460000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
dmas = <&dmac1 1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_tx>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1_8ch: i2s@fe410000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe410000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
assigned-clock-rates = <1188000000>, <1188000000>;
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
<&cru HCLK_I2S1_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 3>, <&dmac1 2>;
dma-names = "rx", "tx";
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
&i2s1m0_lrcktx &i2s1m0_lrckrx
&i2s1m0_sdi0 &i2s1m0_sdi1
&i2s1m0_sdi2 &i2s1m0_sdi3
&i2s1m0_sdo0 &i2s1m0_sdo1
&i2s1m0_sdo2 &i2s1m0_sdo3>;
#sound-dai-cells = <0>;
status = "disabled";
};
dmac0: dmac@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
......@@ -838,9 +921,8 @@ tsadc: tsadc@fe710000 {
assigned-clock-rates = <17000000>, <700000>;
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
<&cru SRST_TSADCPHY>;
reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
pinctrl-names = "init", "default", "sleep";
......@@ -863,6 +945,138 @@ saradc: saradc@fe720000 {
status = "disabled";
};
pwm4: pwm@fe6e0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0000 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm4_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@fe6e0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0010 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@fe6e0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0020 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm6_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@fe6e0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0030 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm7_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm8: pwm@fe6f0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0000 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm8m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm9: pwm@fe6f0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0010 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm9m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm10: pwm@fe6f0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0020 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm10m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm11: pwm@fe6f0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0030 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm11m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm12: pwm@fe700000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700000 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm12m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm13: pwm@fe700010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700010 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm13m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm14: pwm@fe700020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700020 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm14m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm15: pwm@fe700030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700030 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm15m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
......
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