Commit 4342d647 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nicolas Ferre

ARM: at91: make matrix register base soc independent

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: default avatarRyan Mallon <rmallon@gmail.com>
Cc: linux-usb@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent fac36a5a
...@@ -327,6 +327,7 @@ static void __init at91sam9260_ioremap_registers(void) ...@@ -327,6 +327,7 @@ static void __init at91sam9260_ioremap_registers(void)
at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
} }
static void __init at91sam9260_initialize(void) static void __init at91sam9260_initialize(void)
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <mach/cpu.h> #include <mach/cpu.h>
#include <mach/at91sam9260.h> #include <mach/at91sam9260.h>
#include <mach/at91sam9260_matrix.h> #include <mach/at91sam9260_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include "generic.h" #include "generic.h"
...@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ...@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */ /* enable pin */
if (gpio_is_valid(data->enable_pin)) if (gpio_is_valid(data->enable_pin))
...@@ -1265,7 +1266,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) ...@@ -1265,7 +1266,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
switch (data->chipselect) { switch (data->chipselect) {
case 4: case 4:
...@@ -1288,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) ...@@ -1288,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
return; return;
} }
at91_sys_write(AT91_MATRIX_EBICSA, csa); at91_matrix_write(AT91_MATRIX_EBICSA, csa);
if (gpio_is_valid(data->rst_pin)) { if (gpio_is_valid(data->rst_pin)) {
at91_set_multi_drive(data->rst_pin, 0); at91_set_multi_drive(data->rst_pin, 0);
......
...@@ -285,6 +285,7 @@ static void __init at91sam9261_ioremap_registers(void) ...@@ -285,6 +285,7 @@ static void __init at91sam9261_ioremap_registers(void)
at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
} }
static void __init at91sam9261_initialize(void) static void __init at91sam9261_initialize(void)
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/at91sam9261.h> #include <mach/at91sam9261.h>
#include <mach/at91sam9261_matrix.h> #include <mach/at91sam9261_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include "generic.h" #include "generic.h"
...@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ...@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */ /* enable pin */
if (gpio_is_valid(data->enable_pin)) if (gpio_is_valid(data->enable_pin))
......
...@@ -306,6 +306,7 @@ static void __init at91sam9263_ioremap_registers(void) ...@@ -306,6 +306,7 @@ static void __init at91sam9263_ioremap_registers(void)
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
} }
static void __init at91sam9263_initialize(void) static void __init at91sam9263_initialize(void)
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/at91sam9263.h> #include <mach/at91sam9263.h>
#include <mach/at91sam9263_matrix.h> #include <mach/at91sam9263_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include "generic.h" #include "generic.h"
...@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) ...@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
* we assume SMC timings are configured by board code, * we assume SMC timings are configured by board code,
* except True IDE where timings are controlled by driver * except True IDE where timings are controlled by driver
*/ */
ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA); ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
switch (data->chipselect) { switch (data->chipselect) {
case 4: case 4:
at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */ at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
...@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) ...@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
data->chipselect); data->chipselect);
return; return;
} }
at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
if (gpio_is_valid(data->det_pin)) { if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1); at91_set_gpio_input(data->det_pin, 1);
...@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ...@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBI0CSA); csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* enable pin */ /* enable pin */
if (gpio_is_valid(data->enable_pin)) if (gpio_is_valid(data->enable_pin))
......
...@@ -333,6 +333,7 @@ static void __init at91sam9g45_ioremap_registers(void) ...@@ -333,6 +333,7 @@ static void __init at91sam9g45_ioremap_registers(void)
at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
} }
static void __init at91sam9g45_initialize(void) static void __init at91sam9g45_initialize(void)
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/at91sam9g45.h> #include <mach/at91sam9g45.h>
#include <mach/at91sam9g45_matrix.h> #include <mach/at91sam9g45_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include <mach/at_hdmac.h> #include <mach/at_hdmac.h>
#include <mach/atmel-mci.h> #include <mach/atmel-mci.h>
...@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ...@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
/* enable pin */ /* enable pin */
if (gpio_is_valid(data->enable_pin)) if (gpio_is_valid(data->enable_pin))
......
...@@ -290,6 +290,7 @@ static void __init at91sam9rl_ioremap_registers(void) ...@@ -290,6 +290,7 @@ static void __init at91sam9rl_ioremap_registers(void)
at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
} }
static void __init at91sam9rl_initialize(void) static void __init at91sam9rl_initialize(void)
......
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/at91sam9rl.h> #include <mach/at91sam9rl.h>
#include <mach/at91sam9rl_matrix.h> #include <mach/at91sam9rl_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include <mach/at_hdmac.h> #include <mach/at_hdmac.h>
...@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ...@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data) if (!data)
return; return;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */ /* enable pin */
if (gpio_is_valid(data->enable_pin)) if (gpio_is_valid(data->enable_pin))
......
...@@ -43,6 +43,7 @@ ...@@ -43,6 +43,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/at91sam9_smc.h> #include <mach/at91sam9_smc.h>
#include <mach/at91sam9260_matrix.h> #include <mach/at91sam9260_matrix.h>
#include <mach/at91_matrix.h>
#include "sam9_smc.h" #include "sam9_smc.h"
#include "generic.h" #include "generic.h"
...@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void) ...@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
{ {
unsigned long csa; unsigned long csa;
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
/* configure chip-select 0 (NOR) */ /* configure chip-select 0 (NOR) */
sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
......
...@@ -67,6 +67,9 @@ extern void at91sam9g45_restart(char, const char *); ...@@ -67,6 +67,9 @@ extern void at91sam9g45_restart(char, const char *);
/* shutdown */ /* shutdown */
extern void at91_ioremap_shdwc(u32 base_addr); extern void at91_ioremap_shdwc(u32 base_addr);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
/* GPIO */ /* GPIO */
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
......
/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#ifndef __MACH_AT91_MATRIX_H__
#define __MACH_AT91_MATRIX_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_matrix_base;
#define at91_matrix_read(field) \
__raw_readl(at91_matrix_base + field)
#define at91_matrix_write(field, value) \
__raw_writel(value, at91_matrix_base + field);
#else
.extern at91_matrix_base
#endif
#endif /* __MACH_AT91_MATRIX_H__ */
...@@ -95,8 +95,6 @@ ...@@ -95,8 +95,6 @@
#define AT91_USART2 AT91RM9200_BASE_US2 #define AT91_USART2 AT91RM9200_BASE_US2
#define AT91_USART3 AT91RM9200_BASE_US3 #define AT91_USART3 AT91RM9200_BASE_US3
#define AT91_MATRIX 0 /* not supported */
/* /*
* Internal Memory. * Internal Memory.
*/ */
......
...@@ -81,12 +81,12 @@ ...@@ -81,12 +81,12 @@
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800 #define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SMC 0xffffec00 #define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_MATRIX 0xffffee00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 #define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400 #define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600 #define AT91SAM9260_BASE_PIOB 0xfffff600
......
...@@ -15,12 +15,12 @@ ...@@ -15,12 +15,12 @@
#ifndef AT91SAM9260_MATRIX_H #ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H #define AT91SAM9260_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
...@@ -28,11 +28,11 @@ ...@@ -28,11 +28,11 @@
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
...@@ -43,11 +43,11 @@ ...@@ -43,11 +43,11 @@
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
...@@ -55,11 +55,11 @@ ...@@ -55,11 +55,11 @@
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ #define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1) #define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
......
...@@ -66,11 +66,11 @@ ...@@ -66,11 +66,11 @@
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9261_BASE_SMC 0xffffec00 #define AT91SAM9261_BASE_SMC 0xffffec00
#define AT91SAM9261_BASE_MATRIX 0xffffee00
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 #define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9261_BASE_PIOA 0xfffff400 #define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600 #define AT91SAM9261_BASE_PIOB 0xfffff600
......
...@@ -15,15 +15,15 @@ ...@@ -15,15 +15,15 @@
#ifndef AT91SAM9261_MATRIX_H #ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H #define AT91SAM9261_MATRIX_H
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ #define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ #define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ #define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ #define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ #define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ #define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ #define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0) #define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0) #define AT91_MATRIX_ITCM_16 (5 << 0)
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
#define AT91_MATRIX_DTCM_32 (6 << 4) #define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4) #define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ #define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1) #define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ #define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif #endif
...@@ -76,7 +76,6 @@ ...@@ -76,7 +76,6 @@
*/ */
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
...@@ -84,6 +83,7 @@ ...@@ -84,6 +83,7 @@
#define AT91SAM9263_BASE_SMC0 0xffffe400 #define AT91SAM9263_BASE_SMC0 0xffffe400
#define AT91SAM9263_BASE_ECC1 0xffffe600 #define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_SMC1 0xffffea00 #define AT91SAM9263_BASE_SMC1 0xffffea00
#define AT91SAM9263_BASE_MATRIX 0xffffec00
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 #define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9263_BASE_PIOA 0xfffff200 #define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400 #define AT91SAM9263_BASE_PIOB 0xfffff400
......
...@@ -15,15 +15,15 @@ ...@@ -15,15 +15,15 @@
#ifndef AT91SAM9263_MATRIX_H #ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H #define AT91SAM9263_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ #define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ #define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ #define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
...@@ -31,14 +31,14 @@ ...@@ -31,14 +31,14 @@
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ #define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ #define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
...@@ -49,22 +49,22 @@ ...@@ -49,22 +49,22 @@
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ #define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ #define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ #define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ #define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ #define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ #define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ #define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ #define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ #define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ #define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
...@@ -75,7 +75,7 @@ ...@@ -75,7 +75,7 @@
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2) #define AT91_MATRIX_RCB2 (1 << 2)
...@@ -86,7 +86,7 @@ ...@@ -86,7 +86,7 @@
#define AT91_MATRIX_RCB7 (1 << 7) #define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8) #define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ #define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0) #define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0) #define AT91_MATRIX_ITCM_16 (5 << 0)
...@@ -96,7 +96,7 @@ ...@@ -96,7 +96,7 @@
#define AT91_MATRIX_DTCM_16 (5 << 4) #define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4) #define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ #define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) #define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
...@@ -114,7 +114,7 @@ ...@@ -114,7 +114,7 @@
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) #define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) #define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ #define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) #define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
......
...@@ -88,13 +88,13 @@ ...@@ -88,13 +88,13 @@
*/ */
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9G45_BASE_ECC 0xffffe200 #define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_DMA 0xffffec00 #define AT91SAM9G45_BASE_DMA 0xffffec00
#define AT91SAM9G45_BASE_SMC 0xffffe800 #define AT91SAM9G45_BASE_SMC 0xffffe800
#define AT91SAM9G45_BASE_MATRIX 0xffffea00
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 #define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9G45_BASE_PIOA 0xfffff200 #define AT91SAM9G45_BASE_PIOA 0xfffff200
#define AT91SAM9G45_BASE_PIOB 0xfffff400 #define AT91SAM9G45_BASE_PIOB 0xfffff400
......
...@@ -15,18 +15,18 @@ ...@@ -15,18 +15,18 @@
#ifndef AT91SAM9G45_MATRIX_H #ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H #define AT91SAM9G45_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ #define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ #define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ #define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ #define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ #define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ #define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
...@@ -37,14 +37,14 @@ ...@@ -37,14 +37,14 @@
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0) #define AT91_MATRIX_ULBT_128 (7 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ #define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ #define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
...@@ -52,22 +52,22 @@ ...@@ -52,22 +52,22 @@
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ #define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ #define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ #define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ #define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ #define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ #define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ #define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ #define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ #define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ #define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
...@@ -81,7 +81,7 @@ ...@@ -81,7 +81,7 @@
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2) #define AT91_MATRIX_RCB2 (1 << 2)
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
#define AT91_MATRIX_RCB10 (1 << 10) #define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11) #define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ #define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0) #define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0) #define AT91_MATRIX_ITCM_32 (6 << 0)
...@@ -107,12 +107,12 @@ ...@@ -107,12 +107,12 @@
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) #define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) #define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ #define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ #define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0) #define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0) #define AT91C_VDEC_SEL_ON (1 << 0)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ #define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
...@@ -138,13 +138,13 @@ ...@@ -138,13 +138,13 @@
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ #define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ #define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) #define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0) #define AT91_MATRIX_WPSR_WPV (1 << 0)
......
...@@ -70,7 +70,6 @@ ...@@ -70,7 +70,6 @@
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
...@@ -78,6 +77,7 @@ ...@@ -78,6 +77,7 @@
#define AT91SAM9RL_BASE_DMA 0xffffe600 #define AT91SAM9RL_BASE_DMA 0xffffe600
#define AT91SAM9RL_BASE_ECC 0xffffe800 #define AT91SAM9RL_BASE_ECC 0xffffe800
#define AT91SAM9RL_BASE_SMC 0xffffec00 #define AT91SAM9RL_BASE_SMC 0xffffec00
#define AT91SAM9RL_BASE_MATRIX 0xffffee00
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 #define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9RL_BASE_PIOA 0xfffff400 #define AT91SAM9RL_BASE_PIOA 0xfffff400
#define AT91SAM9RL_BASE_PIOB 0xfffff600 #define AT91SAM9RL_BASE_PIOB 0xfffff600
......
...@@ -14,12 +14,12 @@ ...@@ -14,12 +14,12 @@
#ifndef AT91SAM9RL_MATRIX_H #ifndef AT91SAM9RL_MATRIX_H
#define AT91SAM9RL_MATRIX_H #define AT91SAM9RL_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
...@@ -27,12 +27,12 @@ ...@@ -27,12 +27,12 @@
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
...@@ -43,12 +43,12 @@ ...@@ -43,12 +43,12 @@
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2) #define AT91_MATRIX_RCB2 (1 << 2)
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
#define AT91_MATRIX_RCB4 (1 << 4) #define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5) #define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ #define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0) #define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0) #define AT91_MATRIX_ITCM_16 (5 << 0)
...@@ -74,7 +74,7 @@ ...@@ -74,7 +74,7 @@
#define AT91_MATRIX_DTCM_16 (5 << 4) #define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4) #define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ #define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1) #define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) #define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
......
...@@ -276,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr) ...@@ -276,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
panic("Impossible to ioremap at91_rstc_base\n"); panic("Impossible to ioremap at91_rstc_base\n");
} }
void __iomem *at91_matrix_base;
void __init at91_ioremap_matrix(u32 base_addr)
{
at91_matrix_base = ioremap(base_addr, 512);
if (!at91_matrix_base)
panic("Impossible to ioremap at91_matrix_base\n");
}
void __init at91_initialize(unsigned long main_clock) void __init at91_initialize(unsigned long main_clock)
{ {
at91_boot_soc.ioremap_registers(); at91_boot_soc.ioremap_registers();
......
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#include <mach/board.h> #include <mach/board.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <mach/at91sam9261_matrix.h> #include <mach/at91sam9261_matrix.h>
#include <mach/at91_matrix.h>
#include "at91_udc.h" #include "at91_udc.h"
...@@ -910,9 +911,9 @@ static void pullup(struct at91_udc *udc, int is_on) ...@@ -910,9 +911,9 @@ static void pullup(struct at91_udc *udc, int is_on)
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
u32 usbpucr; u32 usbpucr;
usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR); usbpucr = at91_matrix_read(AT91_MATRIX_USBPUCR);
usbpucr |= AT91_MATRIX_USBPUCR_PUON; usbpucr |= AT91_MATRIX_USBPUCR_PUON;
at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr); at91_matrix_write(AT91_MATRIX_USBPUCR, usbpucr);
} }
} else { } else {
stop_activity(udc); stop_activity(udc);
...@@ -928,9 +929,9 @@ static void pullup(struct at91_udc *udc, int is_on) ...@@ -928,9 +929,9 @@ static void pullup(struct at91_udc *udc, int is_on)
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
u32 usbpucr; u32 usbpucr;
usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR); usbpucr = at91_matrix_read(AT91_MATRIX_USBPUCR);
usbpucr &= ~AT91_MATRIX_USBPUCR_PUON; usbpucr &= ~AT91_MATRIX_USBPUCR_PUON;
at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr); at91_matrix_write(AT91_MATRIX_USBPUCR, usbpucr);
} }
clk_off(udc); clk_off(udc);
} }
......
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