Commit 75d43b2d authored by Michael Ellerman's avatar Michael Ellerman

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

Freescale updates from Scott (27 commits):

  "Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit
   FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board
   support, and PrPMC PCI enumeration."
parents d0b7abb2 cb0446c1
* Bus Enumeration by Freescale PCI-X Agent
Typically any Freescale PCI-X bridge hardware strapped into Agent mode
is prevented from enumerating the bus. The PrPMC form-factor requires
all mezzanines to be PCI-X Agents, but one per system may still
enumerate the bus.
The property defined below will allow a PCI-X bridge to be used for bus
enumeration despite being strapped into Agent mode.
Required properties:
- fsl,pci-agent-force-enum : There is no value associated with this
property. The property itself is treated as a boolean.
Example:
/* PCI-X bridge known to be PrPMC Monarch */
pci0: pci@ef008000 {
fsl,pci-agent-force-enum;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
...
...
};
...@@ -288,6 +288,10 @@ config PPC_EMULATE_SSTEP ...@@ -288,6 +288,10 @@ config PPC_EMULATE_SSTEP
bool bool
default y if KPROBES || UPROBES || XMON || HAVE_HW_BREAKPOINT default y if KPROBES || UPROBES || XMON || HAVE_HW_BREAKPOINT
config ZONE_DMA32
bool
default y if PPC64
source "init/Kconfig" source "init/Kconfig"
source "kernel/Kconfig.freezer" source "kernel/Kconfig.freezer"
......
...@@ -410,7 +410,7 @@ sdhc@114000 { ...@@ -410,7 +410,7 @@ sdhc@114000 {
/include/ "qoriq-gpio-3.dtsi" /include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi" /include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 { usb0: usb@210000 {
compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
fsl,iommu-parent = <&pamu1>; fsl,iommu-parent = <&pamu1>;
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
phy_type = "utmi"; phy_type = "utmi";
...@@ -418,7 +418,7 @@ usb0: usb@210000 { ...@@ -418,7 +418,7 @@ usb0: usb@210000 {
}; };
/include/ "qoriq-usb2-dr-0.dtsi" /include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 { usb1: usb@211000 {
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
fsl,iommu-parent = <&pamu1>; fsl,iommu-parent = <&pamu1>;
fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */ fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
dr_mode = "host"; dr_mode = "host";
......
...@@ -498,13 +498,13 @@ sdhc@114000 { ...@@ -498,13 +498,13 @@ sdhc@114000 {
/include/ "qoriq-gpio-3.dtsi" /include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi" /include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 { usb0: usb@210000 {
compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
phy_type = "utmi"; phy_type = "utmi";
port0; port0;
}; };
/include/ "qoriq-usb2-dr-0.dtsi" /include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 { usb1: usb@211000 {
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
dr_mode = "host"; dr_mode = "host";
phy_type = "utmi"; phy_type = "utmi";
}; };
......
/*
* T1040RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/t104xsi-pre.dtsi"
/include/ "t104xrdb.dtsi"
/ {
model = "fsl,T1040RDB";
compatible = "fsl,T1040RDB";
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1040rdb-cpld";
};
};
};
/include/ "fsl/t1040si-post.dtsi"
/*
* T1042RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/t104xsi-pre.dtsi"
/include/ "t104xrdb.dtsi"
/ {
model = "fsl,T1042RDB";
compatible = "fsl,T1042RDB";
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb-cpld";
};
};
};
/include/ "fsl/t1042si-post.dtsi"
/*
* T1042RDB_PI Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/t104xsi-pre.dtsi"
/include/ "t104xrdb.dtsi"
/ {
model = "fsl,T1042RDB_PI";
compatible = "fsl,T1042RDB_PI";
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb_pi-cpld";
};
};
soc: soc@ffe000000 {
i2c@118000 {
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
interrupts = <0x2 0x1 0 0>;
};
};
};
};
/include/ "fsl/t1042si-post.dtsi"
/*
* T1040RDB/T1042RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/ {
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xff800000 0x00010000
3 0 0xf 0xffdf0000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <3 0 0x300>;
};
};
memory {
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512a";
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};
i2c@118100 {
pca9546@77 {
compatible = "nxp,pca9546";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pci0: pcie@ffe240000 {
reg = <0xf 0xfe240000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci1: pcie@ffe250000 {
reg = <0xf 0xfe250000 0 0x10000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci2: pcie@ffe260000 {
reg = <0xf 0xfe260000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci3: pcie@ffe270000 {
reg = <0xf 0xfe270000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
};
...@@ -165,6 +165,8 @@ CONFIG_NFS_FS=y ...@@ -165,6 +165,8 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V4=y CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y CONFIG_ROOT_NFS=y
CONFIG_NFSD=m CONFIG_NFSD=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m CONFIG_NLS_UTF8=m
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
......
...@@ -50,7 +50,6 @@ CONFIG_NET_IPIP=y ...@@ -50,7 +50,6 @@ CONFIG_NET_IPIP=y
CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y CONFIG_IP_PIMSM_V2=y
CONFIG_ARPD=y
CONFIG_INET_ESP=y CONFIG_INET_ESP=y
# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set # CONFIG_INET_LRO is not set
...@@ -60,33 +59,17 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -60,33 +59,17 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_FTL=y CONFIG_FTL=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND=y CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_RESERVE=1
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072 CONFIG_BLK_DEV_RAM_SIZE=131072
...@@ -102,6 +85,7 @@ CONFIG_INPUT_FF_MEMLESS=m ...@@ -102,6 +85,7 @@ CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_LIBPS2=y
CONFIG_PPC_EPAPR_HV_BYTECHAN=y
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_MANY_PORTS=y
...@@ -115,7 +99,6 @@ CONFIG_SPI_GPIO=y ...@@ -115,7 +99,6 @@ CONFIG_SPI_GPIO=y
CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y CONFIG_SPI_FSL_ESPI=y
# CONFIG_HWMON is not set # CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_USB_HID=m CONFIG_USB_HID=m
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_MON=y CONFIG_USB_MON=y
...@@ -124,14 +107,17 @@ CONFIG_USB_EHCI_FSL=y ...@@ -124,14 +107,17 @@ CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_MMC=y CONFIG_MMC=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y CONFIG_FSL_DMA=y
CONFIG_VIRT_DRIVERS=y
CONFIG_FSL_HV_MANAGER=y
CONFIG_FSL_CORENET_CF=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_ISO9660_FS=m CONFIG_ISO9660_FS=m
...@@ -144,35 +130,24 @@ CONFIG_NTFS_FS=y ...@@ -144,35 +130,24 @@ CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y CONFIG_HUGETLBFS=y
CONFIG_MISC_FILESYSTEMS=y
CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=1 CONFIG_JFFS2_FS_DEBUG=1
CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_NFS_FS=y CONFIG_NFS_FS=y
CONFIG_NFS_V4=y CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y CONFIG_ROOT_NFS=y
CONFIG_NFSD=m CONFIG_NFSD=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m CONFIG_NLS_UTF8=m
CONFIG_CRC_T10DIF=y CONFIG_CRC_T10DIF=y
CONFIG_CRC16=y CONFIG_DEBUG_INFO=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_FRAME_WARN=1024 CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_SHIRQ=y CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD4=y
...@@ -180,4 +155,3 @@ CONFIG_CRYPTO_SHA256=y ...@@ -180,4 +155,3 @@ CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_FSL_CAAM=y
CONFIG_FSL_CORENET_CF=y
...@@ -213,7 +213,6 @@ CONFIG_RTC_DRV_DS1307=y ...@@ -213,7 +213,6 @@ CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y CONFIG_FSL_DMA=y
# CONFIG_NET_DMA is not set # CONFIG_NET_DMA is not set
...@@ -227,6 +226,9 @@ CONFIG_UDF_FS=m ...@@ -227,6 +226,9 @@ CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y CONFIG_NTFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PROC_KCORE=y CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y CONFIG_HUGETLBFS=y
......
...@@ -214,7 +214,6 @@ CONFIG_RTC_DRV_DS1307=y ...@@ -214,7 +214,6 @@ CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y CONFIG_FSL_DMA=y
# CONFIG_NET_DMA is not set # CONFIG_NET_DMA is not set
...@@ -228,6 +227,9 @@ CONFIG_UDF_FS=m ...@@ -228,6 +227,9 @@ CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y CONFIG_NTFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PROC_KCORE=y CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y CONFIG_HUGETLBFS=y
......
...@@ -145,6 +145,9 @@ CONFIG_UDF_FS=m ...@@ -145,6 +145,9 @@ CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y CONFIG_NTFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PROC_KCORE=y CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_ADFS_FS=m CONFIG_ADFS_FS=m
......
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <linux/mmdebug.h> #include <linux/mmdebug.h>
#include <linux/mmzone.h>
#include <asm/processor.h> /* For TASK_SIZE */ #include <asm/processor.h> /* For TASK_SIZE */
#include <asm/mmu.h> #include <asm/mmu.h>
#include <asm/page.h> #include <asm/page.h>
...@@ -281,6 +282,8 @@ extern unsigned long empty_zero_page[]; ...@@ -281,6 +282,8 @@ extern unsigned long empty_zero_page[];
extern pgd_t swapper_pg_dir[]; extern pgd_t swapper_pg_dir[];
void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
int dma_pfn_limit_to_zone(u64 pfn_limit);
extern void paging_init(void); extern void paging_init(void);
/* /*
......
...@@ -947,7 +947,7 @@ ...@@ -947,7 +947,7 @@
* 32-bit 8xx: * 32-bit 8xx:
* - SPRG0 scratch for exception vectors * - SPRG0 scratch for exception vectors
* - SPRG1 scratch for exception vectors * - SPRG1 scratch for exception vectors
* - SPRG2 apparently unused but initialized * - SPRG2 scratch for exception vectors
* *
*/ */
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
...@@ -1057,6 +1057,7 @@ ...@@ -1057,6 +1057,7 @@
#ifdef CONFIG_8xx #ifdef CONFIG_8xx
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
#endif #endif
......
...@@ -106,10 +106,14 @@ int __init swiotlb_setup_bus_notifier(void) ...@@ -106,10 +106,14 @@ int __init swiotlb_setup_bus_notifier(void)
return 0; return 0;
} }
void swiotlb_detect_4g(void) void __init swiotlb_detect_4g(void)
{ {
if ((memblock_end_of_DRAM() - 1) > 0xffffffff) if ((memblock_end_of_DRAM() - 1) > 0xffffffff) {
ppc_swiotlb_enable = 1; ppc_swiotlb_enable = 1;
#ifdef CONFIG_ZONE_DMA32
limit_zone_pfn(ZONE_DMA32, (1ULL << 32) >> PAGE_SHIFT);
#endif
}
} }
static int __init swiotlb_late_init(void) static int __init swiotlb_late_init(void)
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <asm/vio.h> #include <asm/vio.h>
#include <asm/bug.h> #include <asm/bug.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/swiotlb.h>
/* /*
* Generic direct DMA implementation * Generic direct DMA implementation
...@@ -25,6 +26,18 @@ ...@@ -25,6 +26,18 @@
* default the offset is PCI_DRAM_OFFSET. * default the offset is PCI_DRAM_OFFSET.
*/ */
static u64 __maybe_unused get_pfn_limit(struct device *dev)
{
u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
struct dev_archdata __maybe_unused *sd = &dev->archdata;
#ifdef CONFIG_SWIOTLB
if (sd->max_direct_dma_addr && sd->dma_ops == &swiotlb_dma_ops)
pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
#endif
return pfn;
}
void *dma_direct_alloc_coherent(struct device *dev, size_t size, void *dma_direct_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag, dma_addr_t *dma_handle, gfp_t flag,
...@@ -40,6 +53,26 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size, ...@@ -40,6 +53,26 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
#else #else
struct page *page; struct page *page;
int node = dev_to_node(dev); int node = dev_to_node(dev);
u64 pfn = get_pfn_limit(dev);
int zone;
zone = dma_pfn_limit_to_zone(pfn);
if (zone < 0) {
dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
__func__, pfn);
return NULL;
}
switch (zone) {
case ZONE_DMA:
flag |= GFP_DMA;
break;
#ifdef CONFIG_ZONE_DMA32
case ZONE_DMA32:
flag |= GFP_DMA32;
break;
#endif
};
/* ignore region specifiers */ /* ignore region specifiers */
flag &= ~(__GFP_HIGHMEM); flag &= ~(__GFP_HIGHMEM);
......
...@@ -104,12 +104,15 @@ turn_on_mmu: ...@@ -104,12 +104,15 @@ turn_on_mmu:
* task's thread_struct. * task's thread_struct.
*/ */
#define EXCEPTION_PROLOG \ #define EXCEPTION_PROLOG \
mtspr SPRN_SPRG_SCRATCH0,r10; \ EXCEPTION_PROLOG_0; \
mtspr SPRN_SPRG_SCRATCH1,r11; \
mfcr r10; \
EXCEPTION_PROLOG_1; \ EXCEPTION_PROLOG_1; \
EXCEPTION_PROLOG_2 EXCEPTION_PROLOG_2
#define EXCEPTION_PROLOG_0 \
mtspr SPRN_SPRG_SCRATCH0,r10; \
mtspr SPRN_SPRG_SCRATCH1,r11; \
mfcr r10
#define EXCEPTION_PROLOG_1 \ #define EXCEPTION_PROLOG_1 \
mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
andi. r11,r11,MSR_PR; \ andi. r11,r11,MSR_PR; \
...@@ -144,6 +147,14 @@ turn_on_mmu: ...@@ -144,6 +147,14 @@ turn_on_mmu:
SAVE_4GPRS(3, r11); \ SAVE_4GPRS(3, r11); \
SAVE_2GPRS(7, r11) SAVE_2GPRS(7, r11)
/*
* Exception exit code.
*/
#define EXCEPTION_EPILOG_0 \
mtcr r10; \
mfspr r10,SPRN_SPRG_SCRATCH0; \
mfspr r11,SPRN_SPRG_SCRATCH1
/* /*
* Note: code which follows this uses cr0.eq (set if from kernel), * Note: code which follows this uses cr0.eq (set if from kernel),
* r11, r12 (SRR0), and r9 (SRR1). * r11, r12 (SRR0), and r9 (SRR1).
...@@ -293,16 +304,8 @@ InstructionTLBMiss: ...@@ -293,16 +304,8 @@ InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
stw r3, 8(r0) stw r3, 8(r0)
#endif #endif
DO_8xx_CPU6(0x3f80, r3) EXCEPTION_PROLOG_0
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mtspr SPRN_SPRG_SCRATCH2, r10
mfcr r10
#ifdef CONFIG_8xx_CPU6
stw r10, 0(r0)
stw r11, 4(r0)
#else
mtspr SPRN_DAR, r10
mtspr SPRN_SPRG2, r11
#endif
mfspr r10, SPRN_SRR0 /* Get effective address of fault */ mfspr r10, SPRN_SRR0 /* Get effective address of fault */
#ifdef CONFIG_8xx_CPU15 #ifdef CONFIG_8xx_CPU15
addi r11, r10, 0x1000 addi r11, r10, 0x1000
...@@ -359,18 +362,11 @@ InstructionTLBMiss: ...@@ -359,18 +362,11 @@ InstructionTLBMiss:
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
/* Restore registers */ /* Restore registers */
#ifndef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mfspr r10, SPRN_DAR
mtcr r10
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2
#else
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
lwz r3, 8(r0) lwz r3, 8(r0)
#endif #endif
mfspr r10, SPRN_M_TW mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi rfi
2: 2:
mfspr r11, SPRN_SRR1 mfspr r11, SPRN_SRR1
...@@ -381,19 +377,11 @@ InstructionTLBMiss: ...@@ -381,19 +377,11 @@ InstructionTLBMiss:
mtspr SPRN_SRR1, r11 mtspr SPRN_SRR1, r11
/* Restore registers */ /* Restore registers */
#ifndef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mfspr r10, SPRN_DAR
mtcr r10
li r11, 0x00f0
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2
#else
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
lwz r3, 8(r0) lwz r3, 8(r0)
#endif #endif
mfspr r10, SPRN_M_TW mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
b InstructionAccess b InstructionAccess
. = 0x1200 . = 0x1200
...@@ -401,16 +389,8 @@ DataStoreTLBMiss: ...@@ -401,16 +389,8 @@ DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
stw r3, 8(r0) stw r3, 8(r0)
#endif #endif
DO_8xx_CPU6(0x3f80, r3) EXCEPTION_PROLOG_0
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mtspr SPRN_SPRG_SCRATCH2, r10
mfcr r10
#ifdef CONFIG_8xx_CPU6
stw r10, 0(r0)
stw r11, 4(r0)
#else
mtspr SPRN_DAR, r10
mtspr SPRN_SPRG2, r11
#endif
mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the /* If we are faulting a kernel address, we have to use the
...@@ -483,19 +463,12 @@ DataStoreTLBMiss: ...@@ -483,19 +463,12 @@ DataStoreTLBMiss:
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
/* Restore registers */ /* Restore registers */
#ifndef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mfspr r10, SPRN_DAR
mtcr r10
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2
#else
mtspr SPRN_DAR, r11 /* Tag DAR */
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
lwz r3, 8(r0) lwz r3, 8(r0)
#endif #endif
mfspr r10, SPRN_M_TW mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi rfi
/* This is an instruction TLB error on the MPC8xx. This could be due /* This is an instruction TLB error on the MPC8xx. This could be due
...@@ -507,35 +480,18 @@ InstructionTLBError: ...@@ -507,35 +480,18 @@ InstructionTLBError:
b InstructionAccess b InstructionAccess
/* This is the data TLB error on the MPC8xx. This could be due to /* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We can catch that * many reasons, including a dirty update to a pte. We bail out to
* one here, but anything else is an error. First, we track down the * a higher level function that can handle it.
* Linux pte. If it is valid, write access is allowed, but the
* page dirty bit is not set, we will set it and reload the TLB. For
* any other case, we bail out to a higher level function that can
* handle it.
*/ */
. = 0x1400 . = 0x1400
DataTLBError: DataTLBError:
#ifdef CONFIG_8xx_CPU6 EXCEPTION_PROLOG_0
stw r3, 8(r0)
#endif
DO_8xx_CPU6(0x3f80, r3)
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
mfcr r10
stw r10, 0(r0)
stw r11, 4(r0)
mfspr r10, SPRN_DAR mfspr r11, SPRN_DAR
cmpwi cr0, r10, 0x00f0 cmpwi cr0, r11, 0x00f0
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ DARFixed:/* Return from dcbx instruction bug workaround */
mfspr r10, SPRN_M_TW /* Restore registers */ EXCEPTION_EPILOG_0
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
b DataAccess b DataAccess
EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
...@@ -559,11 +515,15 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR ...@@ -559,11 +515,15 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
* by decoding the registers used by the dcbx instruction and adding them. * by decoding the registers used by the dcbx instruction and adding them.
* DAR is set to the calculated address and r10 also holds the EA on exit. * DAR is set to the calculated address.
*/ */
/* define if you don't want to use self modifying code */ /* define if you don't want to use self modifying code */
#define NO_SELF_MODIFYING_CODE #define NO_SELF_MODIFYING_CODE
FixupDAR:/* Entry point for dcbx workaround. */ FixupDAR:/* Entry point for dcbx workaround. */
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
#endif
mtspr SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */ /* fetch instruction from memory. */
mfspr r10, SPRN_SRR0 mfspr r10, SPRN_SRR0
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
...@@ -579,16 +539,17 @@ FixupDAR:/* Entry point for dcbx workaround. */ ...@@ -579,16 +539,17 @@ FixupDAR:/* Entry point for dcbx workaround. */
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r11, 0(r11) /* Get the pte */ lwz r11, 0(r11) /* Get the pte */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0) /* restore r3 from memory */
#endif
/* concat physical page address(r11) and page offset(r10) */ /* concat physical page address(r11) and page offset(r10) */
rlwimi r11, r10, 0, 20, 31 rlwimi r11, r10, 0, 20, 31
lwz r11,0(r11) lwz r11,0(r11)
/* Check if it really is a dcbx instruction. */ /* Check if it really is a dcbx instruction. */
/* dcbt and dcbtst does not generate DTLB Misses/Errors, /* dcbt and dcbtst does not generate DTLB Misses/Errors,
* no need to include them here */ * no need to include them here */
srwi r10, r11, 26 /* check if major OP code is 31 */ xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
cmpwi cr0, r10, 31 rlwinm r10, r10, 0, 21, 5
bne- 141f
rlwinm r10, r11, 0, 21, 30
cmpwi cr0, r10, 2028 /* Is dcbz? */ cmpwi cr0, r10, 2028 /* Is dcbz? */
beq+ 142f beq+ 142f
cmpwi cr0, r10, 940 /* Is dcbi? */ cmpwi cr0, r10, 940 /* Is dcbi? */
...@@ -599,16 +560,13 @@ FixupDAR:/* Entry point for dcbx workaround. */ ...@@ -599,16 +560,13 @@ FixupDAR:/* Entry point for dcbx workaround. */
beq+ 142f beq+ 142f
cmpwi cr0, r10, 1964 /* Is icbi? */ cmpwi cr0, r10, 1964 /* Is icbi? */
beq+ 142f beq+ 142f
141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 141: mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Nope, go back to normal TLB processing */ b DARFixed /* Nope, go back to normal TLB processing */
144: mfspr r10, SPRN_DSISR 144: mfspr r10, SPRN_DSISR
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
mtspr SPRN_DSISR, r10 mtspr SPRN_DSISR, r10
142: /* continue, it was a dcbx, dcbi instruction. */ 142: /* continue, it was a dcbx, dcbi instruction. */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0) /* restore r3 from memory */
#endif
#ifndef NO_SELF_MODIFYING_CODE #ifndef NO_SELF_MODIFYING_CODE
andis. r10,r11,0x1f /* test if reg RA is r0 */ andis. r10,r11,0x1f /* test if reg RA is r0 */
li r10,modified_instr@l li r10,modified_instr@l
...@@ -619,14 +577,15 @@ FixupDAR:/* Entry point for dcbx workaround. */ ...@@ -619,14 +577,15 @@ FixupDAR:/* Entry point for dcbx workaround. */
stw r11,0(r10) /* store add/and instruction */ stw r11,0(r10) /* store add/and instruction */
dcbf 0,r10 /* flush new instr. to memory. */ dcbf 0,r10 /* flush new instr. to memory. */
icbi 0,r10 /* invalidate instr. cache line */ icbi 0,r10 /* invalidate instr. cache line */
lwz r11, 4(r0) /* restore r11 from memory */ mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
isync /* Wait until new instr is loaded from memory */ isync /* Wait until new instr is loaded from memory */
modified_instr: modified_instr:
.space 4 /* this is where the add instr. is stored */ .space 4 /* this is where the add instr. is stored */
bne+ 143f bne+ 143f
subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
143: mtdar r10 /* store faulting EA in DAR */ 143: mtdar r10 /* store faulting EA in DAR */
mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Go back to normal TLB handling */ b DARFixed /* Go back to normal TLB handling */
#else #else
mfctr r10 mfctr r10
...@@ -680,13 +639,16 @@ modified_instr: ...@@ -680,13 +639,16 @@ modified_instr:
mfdar r11 mfdar r11
mtctr r11 /* restore ctr reg from DAR */ mtctr r11 /* restore ctr reg from DAR */
mtdar r10 /* save fault EA to DAR */ mtdar r10 /* save fault EA to DAR */
mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Go back to normal TLB handling */ b DARFixed /* Go back to normal TLB handling */
/* special handling for r10,r11 since these are modified already */ /* special handling for r10,r11 since these are modified already */
153: lwz r11, 4(r0) /* load r11 from memory */ 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
b 155f add r10, r10, r11 /* add it */
154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ mfctr r11 /* restore r11 */
155: add r10, r10, r11 /* add it */ b 151b
154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
add r10, r10, r11 /* add it */
mfctr r11 /* restore r11 */ mfctr r11 /* restore r11 */
b 151b b 151b
#endif #endif
......
...@@ -260,6 +260,60 @@ static int __init mark_nonram_nosave(void) ...@@ -260,6 +260,60 @@ static int __init mark_nonram_nosave(void)
} }
return 0; return 0;
} }
#else /* CONFIG_NEED_MULTIPLE_NODES */
static int __init mark_nonram_nosave(void)
{
return 0;
}
#endif
static bool zone_limits_final;
static unsigned long max_zone_pfns[MAX_NR_ZONES] = {
[0 ... MAX_NR_ZONES - 1] = ~0UL
};
/*
* Restrict the specified zone and all more restrictive zones
* to be below the specified pfn. May not be called after
* paging_init().
*/
void __init limit_zone_pfn(enum zone_type zone, unsigned long pfn_limit)
{
int i;
if (WARN_ON(zone_limits_final))
return;
for (i = zone; i >= 0; i--) {
if (max_zone_pfns[i] > pfn_limit)
max_zone_pfns[i] = pfn_limit;
}
}
/*
* Find the least restrictive zone that is entirely below the
* specified pfn limit. Returns < 0 if no suitable zone is found.
*
* pfn_limit must be u64 because it can exceed 32 bits even on 32-bit
* systems -- the DMA limit can be higher than any possible real pfn.
*/
int dma_pfn_limit_to_zone(u64 pfn_limit)
{
enum zone_type top_zone = ZONE_NORMAL;
int i;
#ifdef CONFIG_HIGHMEM
top_zone = ZONE_HIGHMEM;
#endif
for (i = top_zone; i >= 0; i--) {
if (max_zone_pfns[i] <= pfn_limit)
return i;
}
return -EPERM;
}
/* /*
* paging_init() sets up the page tables - in fact we've already done this. * paging_init() sets up the page tables - in fact we've already done this.
...@@ -268,7 +322,7 @@ void __init paging_init(void) ...@@ -268,7 +322,7 @@ void __init paging_init(void)
{ {
unsigned long long total_ram = memblock_phys_mem_size(); unsigned long long total_ram = memblock_phys_mem_size();
phys_addr_t top_of_ram = memblock_end_of_DRAM(); phys_addr_t top_of_ram = memblock_end_of_DRAM();
unsigned long max_zone_pfns[MAX_NR_ZONES]; enum zone_type top_zone;
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
unsigned long v = __fix_to_virt(__end_of_fixed_addresses - 1); unsigned long v = __fix_to_virt(__end_of_fixed_addresses - 1);
...@@ -290,18 +344,20 @@ void __init paging_init(void) ...@@ -290,18 +344,20 @@ void __init paging_init(void)
(unsigned long long)top_of_ram, total_ram); (unsigned long long)top_of_ram, total_ram);
printk(KERN_DEBUG "Memory hole size: %ldMB\n", printk(KERN_DEBUG "Memory hole size: %ldMB\n",
(long int)((top_of_ram - total_ram) >> 20)); (long int)((top_of_ram - total_ram) >> 20));
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
#ifdef CONFIG_HIGHMEM #ifdef CONFIG_HIGHMEM
max_zone_pfns[ZONE_DMA] = lowmem_end_addr >> PAGE_SHIFT; top_zone = ZONE_HIGHMEM;
max_zone_pfns[ZONE_HIGHMEM] = top_of_ram >> PAGE_SHIFT; limit_zone_pfn(ZONE_NORMAL, lowmem_end_addr >> PAGE_SHIFT);
#else #else
max_zone_pfns[ZONE_DMA] = top_of_ram >> PAGE_SHIFT; top_zone = ZONE_NORMAL;
#endif #endif
limit_zone_pfn(top_zone, top_of_ram >> PAGE_SHIFT);
zone_limits_final = true;
free_area_init_nodes(max_zone_pfns); free_area_init_nodes(max_zone_pfns);
mark_nonram_nosave(); mark_nonram_nosave();
} }
#endif /* ! CONFIG_NEED_MULTIPLE_NODES */
static void __init register_page_bootmem_info(void) static void __init register_page_bootmem_info(void)
{ {
......
...@@ -1134,14 +1134,6 @@ void __init do_init_bootmem(void) ...@@ -1134,14 +1134,6 @@ void __init do_init_bootmem(void)
} }
} }
void __init paging_init(void)
{
unsigned long max_zone_pfns[MAX_NR_ZONES];
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
max_zone_pfns[ZONE_DMA] = memblock_end_of_DRAM() >> PAGE_SHIFT;
free_area_init_nodes(max_zone_pfns);
}
static int __init early_numa(char *p) static int __init early_numa(char *p)
{ {
if (!p) if (!p)
......
...@@ -276,7 +276,7 @@ config CORENET_GENERIC ...@@ -276,7 +276,7 @@ config CORENET_GENERIC
For 64bit kernel, the following boards are supported: For 64bit kernel, the following boards are supported:
T208x QDS/RDB, T4240 QDS/RDB and B4 QDS T208x QDS/RDB, T4240 QDS/RDB and B4 QDS
The following boards are supported for both 32bit and 64bit kernel: The following boards are supported for both 32bit and 64bit kernel:
P5020 DS, P5040 DS and T104xQDS P5020 DS, P5040 DS and T104xQDS/RDB
endif # FSL_SOC_BOOKE endif # FSL_SOC_BOOKE
......
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <asm/time.h> #include <asm/time.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/pgtable.h>
#include <asm/ppc-pci.h> #include <asm/ppc-pci.h>
#include <mm/mmu_decl.h> #include <mm/mmu_decl.h>
#include <asm/prom.h> #include <asm/prom.h>
...@@ -67,6 +68,16 @@ void __init corenet_gen_setup_arch(void) ...@@ -67,6 +68,16 @@ void __init corenet_gen_setup_arch(void)
swiotlb_detect_4g(); swiotlb_detect_4g();
#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
/*
* Inbound windows don't cover the full lower 4 GiB
* due to conflicts with PCICSRBAR and outbound windows,
* so limit the DMA32 zone to 2 GiB, to allow consistent
* allocations to succeed.
*/
limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
#endif
pr_info("%s board\n", ppc_md.name); pr_info("%s board\n", ppc_md.name);
mpc85xx_qe_init(); mpc85xx_qe_init();
...@@ -129,6 +140,9 @@ static const char * const boards[] __initconst = { ...@@ -129,6 +140,9 @@ static const char * const boards[] __initconst = {
"fsl,B4220QDS", "fsl,B4220QDS",
"fsl,T1040QDS", "fsl,T1040QDS",
"fsl,T1042QDS", "fsl,T1042QDS",
"fsl,T1040RDB",
"fsl,T1042RDB",
"fsl,T1042RDB_PI",
"keymile,kmcoge4", "keymile,kmcoge4",
NULL NULL
}; };
......
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/pgtable.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/udbg.h> #include <asm/udbg.h>
#include <asm/mpic.h> #include <asm/mpic.h>
...@@ -44,6 +45,15 @@ static void __init qemu_e500_setup_arch(void) ...@@ -44,6 +45,15 @@ static void __init qemu_e500_setup_arch(void)
fsl_pci_assign_primary(); fsl_pci_assign_primary();
swiotlb_detect_4g(); swiotlb_detect_4g();
#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
/*
* Inbound windows don't cover the full lower 4 GiB
* due to conflicts with PCICSRBAR and outbound windows,
* so limit the DMA32 zone to 2 GiB, to allow consistent
* allocations to succeed.
*/
limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
#endif
mpc85xx_smp_init(); mpc85xx_smp_init();
} }
......
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/hw_irq.h> #include <asm/hw_irq.h>
...@@ -50,6 +52,7 @@ struct fsl_msi_feature { ...@@ -50,6 +52,7 @@ struct fsl_msi_feature {
struct fsl_msi_cascade_data { struct fsl_msi_cascade_data {
struct fsl_msi *msi_data; struct fsl_msi *msi_data;
int index; int index;
int virq;
}; };
static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
...@@ -65,11 +68,24 @@ static void fsl_msi_end_irq(struct irq_data *d) ...@@ -65,11 +68,24 @@ static void fsl_msi_end_irq(struct irq_data *d)
{ {
} }
static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
{
struct fsl_msi *msi_data = irqd->domain->host_data;
irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
int cascade_virq, srs;
srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
cascade_virq = msi_data->cascade_array[srs]->virq;
seq_printf(p, " fsl-msi-%d", cascade_virq);
}
static struct irq_chip fsl_msi_chip = { static struct irq_chip fsl_msi_chip = {
.irq_mask = mask_msi_irq, .irq_mask = mask_msi_irq,
.irq_unmask = unmask_msi_irq, .irq_unmask = unmask_msi_irq,
.irq_ack = fsl_msi_end_irq, .irq_ack = fsl_msi_end_irq,
.name = "FSL-MSI", .irq_print_chip = fsl_msi_print_chip,
}; };
static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq, static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
...@@ -180,7 +196,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) ...@@ -180,7 +196,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
np = of_parse_phandle(hose->dn, "fsl,msi", 0); np = of_parse_phandle(hose->dn, "fsl,msi", 0);
if (np) { if (np) {
if (of_device_is_compatible(np, "fsl,mpic-msi") || if (of_device_is_compatible(np, "fsl,mpic-msi") ||
of_device_is_compatible(np, "fsl,vmpic-msi")) of_device_is_compatible(np, "fsl,vmpic-msi") ||
of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
phandle = np->phandle; phandle = np->phandle;
else { else {
dev_err(&pdev->dev, dev_err(&pdev->dev,
...@@ -239,40 +256,24 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) ...@@ -239,40 +256,24 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
return rc; return rc;
} }
static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) static irqreturn_t fsl_msi_cascade(int irq, void *data)
{ {
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *idata = irq_desc_get_irq_data(desc);
unsigned int cascade_irq; unsigned int cascade_irq;
struct fsl_msi *msi_data; struct fsl_msi *msi_data;
int msir_index = -1; int msir_index = -1;
u32 msir_value = 0; u32 msir_value = 0;
u32 intr_index; u32 intr_index;
u32 have_shift = 0; u32 have_shift = 0;
struct fsl_msi_cascade_data *cascade_data; struct fsl_msi_cascade_data *cascade_data = data;
irqreturn_t ret = IRQ_NONE;
cascade_data = irq_get_handler_data(irq);
msi_data = cascade_data->msi_data; msi_data = cascade_data->msi_data;
raw_spin_lock(&desc->lock);
if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
if (chip->irq_mask_ack)
chip->irq_mask_ack(idata);
else {
chip->irq_mask(idata);
chip->irq_ack(idata);
}
}
if (unlikely(irqd_irq_inprogress(idata)))
goto unlock;
msir_index = cascade_data->index; msir_index = cascade_data->index;
if (msir_index >= NR_MSI_REG_MAX) if (msir_index >= NR_MSI_REG_MAX)
cascade_irq = NO_IRQ; cascade_irq = NO_IRQ;
irqd_set_chained_irq_inprogress(idata);
switch (msi_data->feature & FSL_PIC_IP_MASK) { switch (msi_data->feature & FSL_PIC_IP_MASK) {
case FSL_PIC_IP_MPIC: case FSL_PIC_IP_MPIC:
msir_value = fsl_msi_read(msi_data->msi_regs, msir_value = fsl_msi_read(msi_data->msi_regs,
...@@ -301,40 +302,32 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) ...@@ -301,40 +302,32 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
cascade_irq = irq_linear_revmap(msi_data->irqhost, cascade_irq = irq_linear_revmap(msi_data->irqhost,
msi_hwirq(msi_data, msir_index, msi_hwirq(msi_data, msir_index,
intr_index + have_shift)); intr_index + have_shift));
if (cascade_irq != NO_IRQ) if (cascade_irq != NO_IRQ) {
generic_handle_irq(cascade_irq); generic_handle_irq(cascade_irq);
ret = IRQ_HANDLED;
}
have_shift += intr_index + 1; have_shift += intr_index + 1;
msir_value = msir_value >> (intr_index + 1); msir_value = msir_value >> (intr_index + 1);
} }
irqd_clr_chained_irq_inprogress(idata);
switch (msi_data->feature & FSL_PIC_IP_MASK) { return ret;
case FSL_PIC_IP_MPIC:
case FSL_PIC_IP_VMPIC:
chip->irq_eoi(idata);
break;
case FSL_PIC_IP_IPIC:
if (!irqd_irq_disabled(idata) && chip->irq_unmask)
chip->irq_unmask(idata);
break;
}
unlock:
raw_spin_unlock(&desc->lock);
} }
static int fsl_of_msi_remove(struct platform_device *ofdev) static int fsl_of_msi_remove(struct platform_device *ofdev)
{ {
struct fsl_msi *msi = platform_get_drvdata(ofdev); struct fsl_msi *msi = platform_get_drvdata(ofdev);
int virq, i; int virq, i;
struct fsl_msi_cascade_data *cascade_data;
if (msi->list.prev != NULL) if (msi->list.prev != NULL)
list_del(&msi->list); list_del(&msi->list);
for (i = 0; i < NR_MSI_REG_MAX; i++) { for (i = 0; i < NR_MSI_REG_MAX; i++) {
virq = msi->msi_virqs[i]; if (msi->cascade_array[i]) {
if (virq != NO_IRQ) { virq = msi->cascade_array[i]->virq;
cascade_data = irq_get_handler_data(virq);
kfree(cascade_data); BUG_ON(virq == NO_IRQ);
free_irq(virq, msi->cascade_array[i]);
kfree(msi->cascade_array[i]);
irq_dispose_mapping(virq); irq_dispose_mapping(virq);
} }
} }
...@@ -353,7 +346,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, ...@@ -353,7 +346,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
int offset, int irq_index) int offset, int irq_index)
{ {
struct fsl_msi_cascade_data *cascade_data = NULL; struct fsl_msi_cascade_data *cascade_data = NULL;
int virt_msir, i; int virt_msir, i, ret;
virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
if (virt_msir == NO_IRQ) { if (virt_msir == NO_IRQ) {
...@@ -368,11 +361,18 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, ...@@ -368,11 +361,18 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
return -ENOMEM; return -ENOMEM;
} }
irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class); irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
msi->msi_virqs[irq_index] = virt_msir;
cascade_data->index = offset; cascade_data->index = offset;
cascade_data->msi_data = msi; cascade_data->msi_data = msi;
irq_set_handler_data(virt_msir, cascade_data); cascade_data->virq = virt_msir;
irq_set_chained_handler(virt_msir, fsl_msi_cascade); msi->cascade_array[irq_index] = cascade_data;
ret = request_irq(virt_msir, fsl_msi_cascade, 0,
"fsl-msi-cascade", cascade_data);
if (ret) {
dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
virt_msir, ret);
return ret;
}
/* Release the hwirqs corresponding to this MSI register */ /* Release the hwirqs corresponding to this MSI register */
for (i = 0; i < IRQS_PER_MSI_REG; i++) for (i = 0; i < IRQS_PER_MSI_REG; i++)
...@@ -466,7 +466,8 @@ static int fsl_of_msi_probe(struct platform_device *dev) ...@@ -466,7 +466,8 @@ static int fsl_of_msi_probe(struct platform_device *dev)
p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) { if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
msi->srs_shift = MSIIR1_SRS_SHIFT; msi->srs_shift = MSIIR1_SRS_SHIFT;
msi->ibs_shift = MSIIR1_IBS_SHIFT; msi->ibs_shift = MSIIR1_IBS_SHIFT;
if (p) if (p)
...@@ -572,6 +573,10 @@ static const struct of_device_id fsl_of_msi_ids[] = { ...@@ -572,6 +573,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
.compatible = "fsl,vmpic-msi", .compatible = "fsl,vmpic-msi",
.data = &vmpic_msi_feature, .data = &vmpic_msi_feature,
}, },
{
.compatible = "fsl,vmpic-msi-v4.3",
.data = &vmpic_msi_feature,
},
#endif #endif
{} {}
}; };
......
...@@ -27,6 +27,8 @@ ...@@ -27,6 +27,8 @@
#define FSL_PIC_IP_IPIC 0x00000002 #define FSL_PIC_IP_IPIC 0x00000002
#define FSL_PIC_IP_VMPIC 0x00000003 #define FSL_PIC_IP_VMPIC 0x00000003
struct fsl_msi_cascade_data;
struct fsl_msi { struct fsl_msi {
struct irq_domain *irqhost; struct irq_domain *irqhost;
...@@ -37,7 +39,7 @@ struct fsl_msi { ...@@ -37,7 +39,7 @@ struct fsl_msi {
u32 srs_shift; /* Shift of the shared interrupt register select */ u32 srs_shift; /* Shift of the shared interrupt register select */
void __iomem *msi_regs; void __iomem *msi_regs;
u32 feature; u32 feature;
int msi_virqs[NR_MSI_REG_MAX]; struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
struct msi_bitmap bitmap; struct msi_bitmap bitmap;
......
...@@ -522,7 +522,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary) ...@@ -522,7 +522,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
} else { } else {
/* For PCI read PROG to identify controller mode */ /* For PCI read PROG to identify controller mode */
early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
if ((progif & 1) == 1) if ((progif & 1) &&
!of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
goto no_bridge; goto no_bridge;
} }
......
...@@ -781,13 +781,13 @@ struct fsl_ifc_regs { ...@@ -781,13 +781,13 @@ struct fsl_ifc_regs {
__be32 amask; __be32 amask;
u32 res4[0x2]; u32 res4[0x2];
} amask_cs[FSL_IFC_BANK_COUNT]; } amask_cs[FSL_IFC_BANK_COUNT];
u32 res5[0x17]; u32 res5[0x18];
struct { struct {
__be32 csor_ext;
__be32 csor; __be32 csor;
__be32 csor_ext;
u32 res6; u32 res6;
} csor_cs[FSL_IFC_BANK_COUNT]; } csor_cs[FSL_IFC_BANK_COUNT];
u32 res7[0x19]; u32 res7[0x18];
struct { struct {
__be32 ftim[4]; __be32 ftim[4];
u32 res8[0x8]; u32 res8[0x8];
......
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