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Commit 8d97b849 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (28 commits)
  [MIPS] Pb1000: bury the remnants of the PCI code
  [MIPS] Fix build failure in mips oprofile code
  [MIPS] fix warning message on SMP kernels
  [MIPS] markeins: build fix
  [MIPS] ELF handling - use SELFMAG instead of numeric constant
  [MIPS] Get rid of __ilog2
  [MIPS] Fix __fls for non-MIPS32/MIPS64 cpus
  [MIPS] XXS1500 code style cleanup
  [MIPS] MTX-1 code style cleanup
  [MIPS] Pb1200/DBAu1200 code style cleanup
  [MIPS] Pb1550 code style cleanup
  [MIPS] Pb1500 code style cleanup
  [MIPS] Pb1100 code style cleanup
  [MIPS] Pb1000 code style cleanup
  [MIPS] DBAu1xx0 code style cleanup
  [MIPS] Alchemy PCI code style cleanup
  [MIPS] Alchemy common code style cleanup
  [MIPS] Alchemy common headers style cleanup
  [MIPS] Add empty argument parenthesis to GCC_IMM_ASM
  [MIPS] msp_hwbutton.c: minor irq handler cleanups
  ...
parents 9f1a0735 cb0e8b0f
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arch/mips/au1000/common/Makefile
View file @ 8d97b849
#
# Copyright 2000 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Au1000 CPU, generic files.
# Makefile for the Alchemy Au1xx0 CPUs, generic files.
#
obj-y += prom.o irq.o puts.o time.o reset.o \
......
arch/mips/au1000/common/au1xxx_irqmap.c
View file @ 8d97b849
This diff is collapsed.
arch/mips/au1000/common/clocks.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* Simple Au1000 clocks routines.
* Simple Au1xx0 clocks routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -30,8 +29,8 @@
#include <linux/module.h>
#include <asm/mach-au1x00/au1000.h>
static unsigned int au1x00_clock; // Hz
static unsigned int lcd_clock; // KHz
static unsigned int au1x00_clock; /* Hz */
static unsigned int lcd_clock; /* KHz */
static unsigned long uart_baud_base;
/*
......@@ -47,8 +46,6 @@ unsigned int get_au1x00_speed(void)
return au1x00_clock;
}
/*
* The UART baud base is not known at compile time ... if
* we want to be able to use the same code on different
......@@ -73,24 +70,23 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
void set_au1x00_lcd_clock(void)
{
unsigned int static_cfg0;
unsigned int sys_busclk =
(get_au1x00_speed()/1000) /
((int)(au_readl(SYS_POWERCTRL)&0x03) + 2);
unsigned int sys_busclk = (get_au1x00_speed() / 1000) /
((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2);
static_cfg0 = au_readl(MEM_STCFG0);
if (static_cfg0 & (1<<11))
if (static_cfg0 & (1 << 11))
lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
else
lcd_clock = sys_busclk / 4;
if (lcd_clock > 50000) /* Epson MAX */
printk("warning: LCD clock too high (%d KHz)\n", lcd_clock);
printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n",
lcd_clock);
}
unsigned int get_au1x00_lcd_clock(void)
{
return lcd_clock;
}
EXPORT_SYMBOL(get_au1x00_lcd_clock);
arch/mips/au1000/common/cputable.c
View file @ 8d97b849
......@@ -14,7 +14,7 @@
#include <asm/mach-au1x00/au1000.h>
struct cpu_spec* cur_cpu_spec[NR_CPUS];
struct cpu_spec *cur_cpu_spec[NR_CPUS];
/* With some thought, we can probably use the mask to reduce the
* size of the table.
......@@ -39,8 +39,7 @@ struct cpu_spec cpu_specs[] = {
{ 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
};
void
set_cpuspec(void)
void set_cpuspec(void)
{
struct cpu_spec *sp;
u32 prid;
......
arch/mips/au1000/common/dbdma.c
View file @ 8d97b849
This diff is collapsed.
arch/mips/au1000/common/dbg_io.c
View file @ 8d97b849
#include <linux/types.h>
#include <asm/mach-au1x00/au1000.h>
......@@ -8,12 +9,6 @@
* uart to be used for debugging.
*/
#define DEBUG_BASE UART_DEBUG_BASE
/**/
/* we need uint32 uint8 */
/* #include "types.h" */
typedef unsigned char uint8;
typedef unsigned int uint32;
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
......@@ -51,17 +46,15 @@ typedef unsigned int uint32;
#define UART_MOD_CNTRL 0x100 /* Module Control */
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
extern unsigned long calc_clock(void);
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
{
if (UART16550_READ(UART_MOD_CNTRL) != 0x3) {
if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
UART16550_WRITE(UART_MOD_CNTRL, 3);
}
calc_clock();
/* disable interrupts */
......@@ -69,7 +62,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
/* set up baud rate */
{
uint32 divisor;
u32 divisor;
/* set divisor */
divisor = get_au1x00_uart_baud_base() / baud;
......@@ -80,9 +73,9 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
UART16550_WRITE(UART_LCR, (data | parity | stop));
}
static int remoteDebugInitialized = 0;
static int remoteDebugInitialized;
uint8 getDebugChar(void)
u8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
......@@ -92,15 +85,13 @@ uint8 getDebugChar(void)
UART16550_STOP_1BIT);
}
while((UART16550_READ(UART_LSR) & 0x1) == 0);
while ((UART16550_READ(UART_LSR) & 0x1) == 0);
return UART16550_READ(UART_RX);
}
int putDebugChar(uint8 byte)
int putDebugChar(u8 byte)
{
// int i;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_115200,
......@@ -109,9 +100,8 @@ int putDebugChar(uint8 byte)
UART16550_STOP_1BIT);
}
while ((UART16550_READ(UART_LSR)&0x40) == 0);
while ((UART16550_READ(UART_LSR) & 0x40) == 0);
UART16550_WRITE(UART_TX, byte);
//for (i=0;i<0xfff;i++);
return 1;
}
......
arch/mips/au1000/common/dma.c
View file @ 8d97b849
/*
*
* BRIEF MODULE DESCRIPTION
* A DMA channel allocator for Au1000. API is modeled loosely off of
* A DMA channel allocator for Au1x00. API is modeled loosely off of
* linux/kernel/dma.c.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify it
......@@ -39,7 +38,8 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
defined(CONFIG_SOC_AU1100)
/*
* A note on resource allocation:
*
......@@ -56,7 +56,6 @@
* returned from request_dma.
*/
DEFINE_SPINLOCK(au1000_dma_spin_lock);
struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
......@@ -71,7 +70,7 @@ struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
};
EXPORT_SYMBOL(au1000_dma_table);
// Device FIFO addresses and default DMA modes
/* Device FIFO addresses and default DMA modes */
static const struct dma_dev {
unsigned int fifo_addr;
unsigned int dma_mode;
......@@ -80,8 +79,8 @@ static const struct dma_dev {
{UART0_ADDR + UART_RX, 0},
{0, 0},
{0, 0},
{AC97C_DATA, DMA_DW16 }, // coherent
{AC97C_DATA, DMA_DR | DMA_DW16 }, // coherent
{AC97C_DATA, DMA_DW16 }, /* coherent */
{AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */
{UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC},
{UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC},
{USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC},
......@@ -101,10 +100,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
struct dma_chan *chan;
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
if ((chan = get_dma_chan(i)) != NULL) {
chan = get_dma_chan(i);
if (chan != NULL)
len += sprintf(buf + len, "%2d: %s\n",
i, chan->dev_str);
}
}
if (fpos >= len) {
......@@ -113,18 +112,19 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
return 0;
}
*start = buf + fpos;
if ((len -= fpos) > length)
len -= fpos;
if (len > length)
return length;
*eof = 1;
return len;
}
// Device FIFO addresses and default DMA modes - 2nd bank
/* Device FIFO addresses and default DMA modes - 2nd bank */
static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
{SD0_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent
{SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8}, // coherent
{SD1_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent
{SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8} // coherent
{ SD0_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */
{ SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }, /* coherent */
{ SD1_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */
{ SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 } /* coherent */
};
void dump_au1000_dma_channel(unsigned int dmanr)
......@@ -150,7 +150,6 @@ void dump_au1000_dma_channel(unsigned int dmanr)
au_readl(chan->io + DMA_BUFFER1_COUNT));
}
/*
* Finds a free channel, and binds the requested device to it.
* Returns the allocated channel number, or negative on error.
......@@ -169,14 +168,14 @@ int request_au1000_dma(int dev_id, const char *dev_str,
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
#endif
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
break;
}
if (i == NUM_AU1000_DMA_CHANNELS)
return -ENODEV;
......@@ -185,15 +184,15 @@ int request_au1000_dma(int dev_id, const char *dev_str,
if (dev_id >= DMA_NUM_DEV) {
dev_id -= DMA_NUM_DEV;
dev = &dma_dev_table_bank2[dev_id];
} else {
} else
dev = &dma_dev_table[dev_id];
}
if (irqhandler) {
chan->irq = AU1000_DMA_INT_BASE + i;
chan->irq_dev = irq_dev_id;
if ((ret = request_irq(chan->irq, irqhandler, irqflags,
dev_str, chan->irq_dev))) {
ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
chan->irq_dev);
if (ret) {
chan->irq = 0;
chan->irq_dev = NULL;
return ret;
......@@ -203,7 +202,7 @@ int request_au1000_dma(int dev_id, const char *dev_str,
chan->irq_dev = NULL;
}
// fill it in
/* fill it in */
chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
chan->dev_id = dev_id;
chan->dev_str = dev_str;
......@@ -220,8 +219,9 @@ EXPORT_SYMBOL(request_au1000_dma);
void free_au1000_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan) {
printk("Trying to free DMA%d\n", dmanr);
printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
return;
}
......@@ -235,4 +235,4 @@ void free_au1000_dma(unsigned int dmanr)
}
EXPORT_SYMBOL(free_au1000_dma);
#endif // AU1000 AU1500 AU1100
#endif /* AU1000 AU1500 AU1100 */
arch/mips/au1000/common/gpio.c
View file @ 8d97b849
......@@ -69,7 +69,7 @@ static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
static int au1xxx_gpio1_read(unsigned gpio)
{
return ((gpio1->pinstaterd >> gpio) & 0x01);
return (gpio1->pinstaterd >> gpio) & 0x01;
}
static void au1xxx_gpio1_write(unsigned gpio, int value)
......@@ -104,7 +104,6 @@ int au1xxx_gpio_get_value(unsigned gpio)
else
return au1xxx_gpio1_read(gpio);
}
EXPORT_SYMBOL(au1xxx_gpio_get_value);
void au1xxx_gpio_set_value(unsigned gpio, int value)
......@@ -118,7 +117,6 @@ void au1xxx_gpio_set_value(unsigned gpio, int value)
else
au1xxx_gpio1_write(gpio, value);
}
EXPORT_SYMBOL(au1xxx_gpio_set_value);
int au1xxx_gpio_direction_input(unsigned gpio)
......@@ -132,7 +130,6 @@ int au1xxx_gpio_direction_input(unsigned gpio)
return au1xxx_gpio1_direction_input(gpio);
}
EXPORT_SYMBOL(au1xxx_gpio_direction_input);
int au1xxx_gpio_direction_output(unsigned gpio, int value)
......@@ -146,5 +143,4 @@ int au1xxx_gpio_direction_output(unsigned gpio, int value)
return au1xxx_gpio1_direction_output(gpio, value);
}
EXPORT_SYMBOL(au1xxx_gpio_direction_output);
arch/mips/au1000/common/irq.c
View file @ 8d97b849
......@@ -210,10 +210,8 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
au_sync();
}
static inline void mask_and_ack_level_irq(unsigned int irq_nr)
{
local_disable_irq(irq_nr);
au_sync();
#if defined(CONFIG_MIPS_PB1000)
......@@ -263,14 +261,14 @@ void restore_local_and_enable(int controller, unsigned long mask)
unsigned long flags, new_mask;
spin_lock_irqsave(&irq_lock, flags);
for (i = 0; i < 32; i++) {
for (i = 0; i < 32; i++)
if (mask & (1 << i)) {
if (controller)
local_enable_irq(i + 32);
else
local_enable_irq(i);
}
}
if (controller)
new_mask = au_readl(IC1_MASKSET);
else
......
arch/mips/au1000/common/pci.c
View file @ 8d97b849
......@@ -2,9 +2,8 @@
* BRIEF MODULE DESCRIPTION
* Alchemy/AMD Au1x00 PCI support.
*
* Copyright 2001-2003, 2007 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*
......@@ -86,9 +85,9 @@ static int __init au1x_pci_setup(void)
u32 prid = read_c0_prid();
if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk("Non-coherent PCI accesses enabled\n");
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
}
}
#endif
......
arch/mips/au1000/common/platform.c
View file @ 8d97b849
......@@ -269,8 +269,8 @@ static struct platform_device au1x00_pcmcia_device = {
#ifdef SMBUS_PSC_BASE
static struct resource pbdb_smbus_resources[] = {
{
.start = SMBUS_PSC_BASE,
.end = SMBUS_PSC_BASE + 0x24 - 1,
.start = CPHYSADDR(SMBUS_PSC_BASE),
.end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
.flags = IORESOURCE_MEM,
},
};
......@@ -302,16 +302,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
#endif
};
int __init au1xxx_platform_init(void)
static int __init au1xxx_platform_init(void)
{
unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
int i;
/* Fill up uartclk. */
for (i = 0; au1x00_uart_data[i].flags ; i++)
for (i = 0; au1x00_uart_data[i].flags; i++)
au1x00_uart_data[i].uartclk = uartclk;
return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices));
return platform_add_devices(au1xxx_platform_devices,
ARRAY_SIZE(au1xxx_platform_devices));
}
arch_initcall(au1xxx_platform_init);
arch/mips/au1000/common/power.c
View file @ 8d97b849
This diff is collapsed.
arch/mips/au1000/common/prom.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* PROM library initialisation code, supports YAMON and U-Boot.
*
* Copyright 2000, 2001, 2006 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000-2001, 2006, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/xx files.
......@@ -57,7 +56,7 @@ void prom_init_cmdline(void)
actr = 1; /* Always ignore argv[0] */
cp = &(arcs_cmdline[0]);
while(actr < prom_argc) {
while (actr < prom_argc) {
strcpy(cp, prom_argv[actr]);
cp += strlen(prom_argv[actr]);
*cp++ = ' ';
......@@ -84,10 +83,8 @@ char *prom_getenv(char *envname)
if (yamon) {
if (strcmp(envname, *env++) == 0)
return *env;
} else {
if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
return *env + i + 1;
}
} else if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
return *env + i + 1;
env++;
}
......@@ -110,13 +107,13 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
int i;
for(i = 0; i < 6; i++) {
for (i = 0; i < 6; i++) {
unsigned char num;
if((*str == '.') || (*str == ':'))
if ((*str == '.') || (*str == ':'))
str++;
num = str2hexnum(*str++) << 4;
num |= (str2hexnum(*str++));
num = str2hexnum(*str++) << 4;
num |= str2hexnum(*str++);
ea[i] = num;
}
}
......
arch/mips/au1000/common/puts.c
View file @ 8d97b849
/*
*
* BRIEF MODULE DESCRIPTION
* Low level uart routines to directly access a 16550 uart.
* Low level UART routines to directly access Alchemy UART.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -40,12 +39,12 @@
static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
#ifdef SLOW_DOWN
static inline void slow_down(void)
{
int k;
for (k=0; k<10000; k++);
int k;
for (k = 0; k < 10000; k++);
}
#else
#define slow_down()
......@@ -54,16 +53,16 @@ static inline void slow_down(void)
void
prom_putchar(const unsigned char c)
{
unsigned char ch;
int i = 0;
unsigned char ch;
int i = 0;
do {
ch = com1[SER_CMD];
slow_down();
i++;
if (i > TIMEOUT)
break;
} while (0 == (ch & TX_BUSY));
do {
ch = com1[SER_CMD];
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SER_DATA] = c;
com1[SER_DATA] = c;
}
arch/mips/au1000/common/reset.c
View file @ 8d97b849
/*
*
* BRIEF MODULE DESCRIPTION
* Au1000 reset routines.
* Au1xx0 reset routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2006, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -28,10 +27,11 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/cacheflush.h>
#include <asm/mach-au1x00/au1000.h>
extern int au_sleep(void);
extern void (*flush_cache_all)(void);
void au1000_restart(char *command)
{
......@@ -40,8 +40,8 @@ void au1000_restart(char *command)
u32 prid = read_c0_prid();
printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
switch (prid & 0xFF000000)
{
switch (prid & 0xFF000000) {
case 0x00000000: /* Au1000 */
au_writel(0x02, 0xb0000010); /* ac97_enable */
au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
......@@ -138,9 +138,6 @@ void au1000_restart(char *command)
au_writel(0x00, 0xb1900064); /* sys_auxpll */
au_writel(0x00, 0xb1900100); /* sys_pininputen */
break;
default:
break;
}
set_c0_status(ST0_BEV | ST0_ERL);
......@@ -158,25 +155,25 @@ void au1000_restart(char *command)
void au1000_halt(void)
{
#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
/* power off system */
printk("\n** Powering off...\n");
au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
/* Power off system */
printk(KERN_NOTICE "\n** Powering off...\n");
au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
au_sync();
while(1); /* should not get here */
while (1); /* should not get here */
#else
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
#ifdef CONFIG_MIPS_MIRAGE
au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
#endif
#ifdef CONFIG_MIPS_DB1200
au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
#endif
#ifdef CONFIG_PM
au_sleep();
/* should not get here */
printk(KERN_ERR "Unable to put cpu in sleep mode\n");
while(1);
/* Should not get here */
printk(KERN_ERR "Unable to put CPU in sleep mode\n");
while (1);
#else
while (1)
__asm__(".set\tmips3\n\t"
......
arch/mips/au1000/common/setup.c
View file @ 8d97b849
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000, 2007-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com
*
* Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
*
......@@ -48,7 +47,7 @@ void __init plat_mem_setup(void)
{
struct cpu_spec *sp;
char *argptr;
unsigned long prid, cpufreq, bclk = 1;
unsigned long prid, cpufreq, bclk;
set_cpuspec();
sp = cur_cpu_spec[0];
......@@ -66,42 +65,39 @@ void __init plat_mem_setup(void)
cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
bclk = sp->cpu_bclk;
if (bclk)
{
if (sp->cpu_bclk) {
/* Enable BCLK switching */
bclk = au_readl(0xB190003C);
au_writel(bclk | 0x60, 0xB190003C);
printk("BCLK switching enabled!\n");
bclk = au_readl(SYS_POWERCTRL);
au_writel(bclk | 0x60, SYS_POWERCTRL);
printk(KERN_INFO "BCLK switching enabled!\n");
}
if (sp->cpu_od) {
/* Various early Au1000 Errata corrected by this */
set_c0_config(1<<19); /* Set Config[OD] */
}
else {
if (sp->cpu_od)
/* Various early Au1xx0 errata corrected by this */
set_c0_config(1 << 19); /* Set Config[OD] */
else
/* Clear to obtain best system bus performance */
clear_c0_config(1<<19); /* Clear Config[OD] */
}
clear_c0_config(1 << 19); /* Clear Config[OD] */
argptr = prom_getcmdline();
#ifdef CONFIG_SERIAL_8250_CONSOLE
if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = strstr(argptr, "console=");
if (argptr == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
}
#endif
#ifdef CONFIG_FB_AU1100
if ((argptr = strstr(argptr, "video=")) == NULL) {
argptr = prom_getcmdline();
/* default panel */
/*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
}
argptr = strstr(argptr, "video=");
if (argptr == NULL) {
argptr = prom_getcmdline();
/* default panel */
/*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
}
#endif
#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
/* au1000 does not support vra, au1500 and au1100 do */
strcat(argptr, " au1000_audio=vra");
......@@ -129,7 +125,7 @@ void __init plat_mem_setup(void)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
/* Don't fixup 36 bit addresses */
/* Don't fixup 36-bit addresses */
if ((phys_addr >> 32) != 0)
return phys_addr;
......@@ -145,17 +141,17 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
}
#endif
/* All Au1x SOCs have a pcmcia controller */
/* We setup our 32 bit pseudo addresses to be equal to the
* 36 bit addr >> 4, to make it easier to check the address
/*
* All Au1xx0 SOCs have a PCMCIA controller.
* We setup our 32-bit pseudo addresses to be equal to the
* 36-bit addr >> 4, to make it easier to check the address
* and fix it.
* The Au1x socket 0 phys attribute address is 0xF 4000 0000.
* The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
* The pseudo address we use is 0xF400 0000. Any address over
* 0xF400 0000 is a pcmcia pseudo address.
* 0xF400 0000 is a PCMCIA pseudo address.
*/
if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF))
return (phys_t)(phys_addr << 4);
}
/* default nop */
return phys_addr;
......
arch/mips/au1000/common/time.c
View file @ 8d97b849
......@@ -25,11 +25,9 @@
*
* Setting up the clock on the MIPS boards.
*
* Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
* will use the user interface gettimeofday() functions from the
* arch/mips/kernel/time.c, and we provide the clock interrupt processing
* and the timer offset compute functions. If CONFIG_PM is selected,
* we also ensure the 32KHz timer is available. -- Dan
* We provide the clock interrupt processing and the timer offset compute
* functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is
* available. -- Dan
*/
#include <linux/types.h>
......@@ -47,8 +45,7 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */
#if HZ < 100 || HZ > 1000
#error "unsupported HZ value! Must be in [100,1000]"
#endif
#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
extern void startup_match20_interrupt(irq_handler_t handler);
#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
static unsigned long last_pc0, last_match20;
#endif
......@@ -61,7 +58,7 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
{
unsigned long pc0;
int time_elapsed;
static int jiffie_drift = 0;
static int jiffie_drift;
if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
/* should never happen! */
......@@ -70,13 +67,11 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
}
pc0 = au_readl(SYS_TOYREAD);
if (pc0 < last_match20) {
if (pc0 < last_match20)
/* counter overflowed */
time_elapsed = (0xffffffff - last_match20) + pc0;
}
else {
else
time_elapsed = pc0 - last_match20;
}
while (time_elapsed > 0) {
do_timer(1);
......@@ -92,8 +87,9 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
/* our counter ticks at 10.009765625 ms/tick, we we're running
* almost 10uS too slow per tick.
/*
* Our counter ticks at 10.009765625 ms/tick, we we're running
* almost 10 uS too slow per tick.
*/
if (jiffie_drift >= 999) {
......@@ -117,20 +113,17 @@ struct irqaction counter0_action = {
/* When we wakeup from sleep, we have to "catch up" on all of the
* timer ticks we have missed.
*/
void
wakeup_counter0_adjust(void)
void wakeup_counter0_adjust(void)
{
unsigned long pc0;
int time_elapsed;
pc0 = au_readl(SYS_TOYREAD);
if (pc0 < last_match20) {
if (pc0 < last_match20)
/* counter overflowed */
time_elapsed = (0xffffffff - last_match20) + pc0;
}
else {
else
time_elapsed = pc0 - last_match20;
}
while (time_elapsed > 0) {
time_elapsed -= MATCH20_INC;
......@@ -143,10 +136,8 @@ wakeup_counter0_adjust(void)
}
/* This is just for debugging to set the timer for a sleep delay.
*/
void
wakeup_counter0_set(int ticks)
/* This is just for debugging to set the timer for a sleep delay. */
void wakeup_counter0_set(int ticks)
{
unsigned long pc0;
......@@ -157,21 +148,22 @@ wakeup_counter0_set(int ticks)
}
#endif
/* I haven't found anyone that doesn't use a 12 MHz source clock,
/*
* I haven't found anyone that doesn't use a 12 MHz source clock,
* but just in case.....
*/
#define AU1000_SRC_CLK 12000000
/*
* We read the real processor speed from the PLL. This is important
* because it is more accurate than computing it from the 32KHz
* because it is more accurate than computing it from the 32 KHz
* counter, if it exists. If we don't have an accurate processor
* speed, all of the peripherals that derive their clocks based on
* this advertised speed will introduce error and sometimes not work
* properly. This function is futher convoluted to still allow configurations
* to do that in case they have really, really old silicon with a
* write-only PLL register, that we need the 32KHz when power management
* "wait" is enabled, and we need to detect if the 32KHz isn't present
* write-only PLL register, that we need the 32 KHz when power management
* "wait" is enabled, and we need to detect if the 32 KHz isn't present
* but requested......got it? :-) -- Dan
*/
unsigned long calc_clock(void)
......@@ -182,8 +174,7 @@ unsigned long calc_clock(void)
spin_lock_irqsave(&time_lock, flags);
/* Power management cares if we don't have a 32KHz counter.
*/
/* Power management cares if we don't have a 32 KHz counter. */
no_au1xxx_32khz = 0;
counter = au_readl(SYS_COUNTER_CNTRL);
if (counter & SYS_CNTRL_E0) {
......@@ -193,7 +184,7 @@ unsigned long calc_clock(void)
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
/* RTC now ticks at 32.768/16 kHz */
au_writel(trim_divide-1, SYS_RTCTRIM);
au_writel(trim_divide - 1, SYS_RTCTRIM);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
......@@ -215,9 +206,11 @@ unsigned long calc_clock(void)
#endif
else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
/* On Alchemy CPU:counter ratio is 1:1 */
mips_hpt_frequency = cpu_speed;
// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
& 0x03) + 2) * 16));
spin_unlock_irqrestore(&time_lock, flags);
return cpu_speed;
}
......@@ -228,10 +221,10 @@ void __init plat_time_init(void)
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
set_au1x00_speed(est_freq);
set_au1x00_lcd_clock(); // program the LCD clock
printk(KERN_INFO "CPU frequency %u.%02u MHz\n",
est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
set_au1x00_speed(est_freq);
set_au1x00_lcd_clock(); /* program the LCD clock */
#ifdef CONFIG_PM
/*
......@@ -243,30 +236,29 @@ void __init plat_time_init(void)
* counter 0 interrupt as a special irq and it doesn't show
* up under /proc/interrupts.
*
* Check to ensure we really have a 32KHz oscillator before
* Check to ensure we really have a 32 KHz oscillator before
* we do this.
*/
if (no_au1xxx_32khz)
printk("WARNING: no 32KHz clock found.\n");
printk(KERN_WARNING "WARNING: no 32KHz clock found.\n");
else {
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
au_writel(0, SYS_TOYWRITE);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
au_writel(~0, SYS_WAKESRC);
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
/* setup match20 to interrupt once every HZ */
/* Setup match20 to interrupt once every HZ */
last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
/* We can use the real 'wait' instruction.
*/
/* We can use the real 'wait' instruction. */
allow_au1k_wait = 1;
}
......
arch/mips/au1000/db1x00/Makefile
View file @ 8d97b849
#
# Copyright 2000 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
#
# Makefile for the Alchemy Semiconductor Db1x00 board.
lib-y := init.o board_setup.o irqmap.o
arch/mips/au1000/db1x00/board_setup.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* Alchemy Db1x00 board setup.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -37,49 +36,49 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
/* Hit BCSR.SW_RESET[RESET] */
bcsr->swreset = 0x0000;
}
void __init board_setup(void)
{
u32 pin_func;
u32 pin_func = 0;
pin_func = 0;
/* not valid for 1550 */
#if defined(CONFIG_IRDA) && (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
/* set IRFIRSEL instead of GPIO15 */
pin_func = au_readl(SYS_PINFUNC) | (u32)((1<<8));
/* Not valid for Au1550 */
#if defined(CONFIG_IRDA) && \
(defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
/* Set IRFIRSEL instead of GPIO15 */
pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
au_writel(pin_func, SYS_PINFUNC);
/* power off until the driver is in use */
/* Power off until the driver is in use */
bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK;
bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF;
bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF;
au_sync();
#endif
bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
#ifdef CONFIG_MIPS_MIRAGE
/* enable GPIO[31:0] inputs */
/* Enable GPIO[31:0] inputs */
au_writel(0, SYS_PININPUTEN);
/* GPIO[20] is output, tristate the other input primary GPIO's */
au_writel((u32)(~(1<<20)), SYS_TRIOUTCLR);
/* GPIO[20] is output, tristate the other input primary GPIOs */
au_writel(~(1 << 20), SYS_TRIOUTCLR);
/* set GPIO[210:208] instead of SSI_0 */
pin_func = au_readl(SYS_PINFUNC) | (u32)(1);
/* Set GPIO[210:208] instead of SSI_0 */
pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
/* set GPIO[215:211] for LED's */
pin_func |= (u32)((5<<2));
/* Set GPIO[215:211] for LEDs */
pin_func |= 5 << 2;
/* set GPIO[214:213] for more LED's */
pin_func |= (u32)((5<<12));
/* Set GPIO[214:213] for more LEDs */
pin_func |= 5 << 12;
/* set GPIO[207:200] instead of PCMCIA/LCD */
pin_func |= (u32)((3<<17));
/* Set GPIO[207:200] instead of PCMCIA/LCD */
pin_func |= SYS_PF_LCD | SYS_PF_PC;
au_writel(pin_func, SYS_PINFUNC);
/* Enable speaker amplifier. This should
/*
* Enable speaker amplifier. This should
* be part of the audio driver.
*/
au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR);
......@@ -89,21 +88,21 @@ void __init board_setup(void)
au_sync();
#ifdef CONFIG_MIPS_DB1000
printk("AMD Alchemy Au1000/Db1000 Board\n");
printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
#endif
#ifdef CONFIG_MIPS_DB1500
printk("AMD Alchemy Au1500/Db1500 Board\n");
printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
#endif
#ifdef CONFIG_MIPS_DB1100
printk("AMD Alchemy Au1100/Db1100 Board\n");
printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
#endif
#ifdef CONFIG_MIPS_BOSPORUS
printk("AMD Alchemy Bosporus Board\n");
printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
#endif
#ifdef CONFIG_MIPS_MIRAGE
printk("AMD Alchemy Mirage Board\n");
printk(KERN_INFO "AMD Alchemy Mirage Board\n");
#endif
#ifdef CONFIG_MIPS_DB1550
printk("AMD Alchemy Au1550/Db1550 Board\n");
printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
#endif
}
arch/mips/au1000/db1x00/init.c
View file @ 8d97b849
......@@ -2,9 +2,8 @@
* BRIEF MODULE DESCRIPTION
* PB1000 board setup
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -49,8 +48,8 @@ void __init prom_init(void)
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
......@@ -58,6 +57,6 @@ void __init prom_init(void)
if (!memsize_str)
memsize = 0x04000000;
else
memsize = simple_strtol(memsize_str, NULL, 0);
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/db1x00/irqmap.c
View file @ 8d97b849
......@@ -32,32 +32,32 @@
#ifdef CONFIG_MIPS_DB1500
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371 */
[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
};
#endif
#ifdef CONFIG_MIPS_BOSPORUS
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
[12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
[11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI */
[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741 */
[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
};
#endif
#ifdef CONFIG_MIPS_MIRAGE
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
[12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
[13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
[11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
[12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
[13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
};
#endif
#ifdef CONFIG_MIPS_DB1550
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
[12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
[11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
[12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
#endif
......
arch/mips/au1000/mtx-1/Makefile
View file @ 8d97b849
#
# Copyright 2003 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Author: MontaVista Software, Inc. <source@mvista.com>
# Bruno Randolf <bruno.randolf@4g-systems.biz>
#
# Makefile for 4G Systems MTX-1 board.
......
arch/mips/au1000/mtx-1/board_setup.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* 4G Systems MTX-1 board setup.
*
* Copyright 2003 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
* Bruno Randolf <bruno.randolf@4g-systems.biz>
*
* This program is free software; you can redistribute it and/or modify it
......@@ -34,7 +33,7 @@
#include <asm/mach-au1x00/au1000.h>
extern int (*board_pci_idsel)(unsigned int devsel, int assert);
int mtx1_pci_idsel(unsigned int devsel, int assert);
int mtx1_pci_idsel(unsigned int devsel, int assert);
void board_reset(void)
{
......@@ -45,36 +44,36 @@ void board_reset(void)
void __init board_setup(void)
{
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
// enable USB power switch
au_writel( au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR );
au_writel( 0x100000, GPIO2_OUTPUT );
/* Enable USB power switch */
au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
au_writel(0x100000, GPIO2_OUTPUT);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
#endif
// initialize sys_pinfunc:
au_writel( SYS_PF_NI2, SYS_PINFUNC );
/* Initialize sys_pinfunc */
au_writel(SYS_PF_NI2, SYS_PINFUNC);
// initialize GPIO
au_writel( 0xFFFFFFFF, SYS_TRIOUTCLR );
au_writel( 0x00000001, SYS_OUTPUTCLR ); // set M66EN (PCI 66MHz) to OFF
au_writel( 0x00000008, SYS_OUTPUTSET ); // set PCI CLKRUN# to OFF
au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON
au_writel( 0x00000020, SYS_OUTPUTCLR ); // set eth PHY TX_ER to OFF
/* Initialize GPIO */
au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */
au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */
au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */
// enable LED and set it to green
au_writel( au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR );
au_writel( 0x18000800, GPIO2_OUTPUT );
/* Enable LED and set it to green */
au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR);
au_writel(0x18000800, GPIO2_OUTPUT);
board_pci_idsel = mtx1_pci_idsel;
printk("4G Systems MTX-1 Board\n");
printk(KERN_INFO "4G Systems MTX-1 Board\n");
}
int
......@@ -82,20 +81,18 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
{
#define MTX_IDSEL_ONLY_0_AND_3 0
#if MTX_IDSEL_ONLY_0_AND_3
if (devsel != 0 && devsel != 3) {
printk("*** not 0 or 3\n");
return 0;
}
if (devsel != 0 && devsel != 3) {
printk(KERN_ERR "*** not 0 or 3\n");
return 0;
}
#endif
if (assert && devsel != 0) {
// suppress signal to cardbus
au_writel( 0x00000002, SYS_OUTPUTCLR ); // set EXT_IO3 OFF
}
else {
au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON
}
au_sync_udelay(1);
return 1;
if (assert && devsel != 0)
/* Suppress signal to Cardbus */
au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */
else
au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
au_sync_udelay(1);
return 1;
}
arch/mips/au1000/mtx-1/init.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* 4G Systems MTX-1 board setup
*
* Copyright 2003 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
* Bruno Randolf <bruno.randolf@4g-systems.biz>
*
* This program is free software; you can redistribute it and/or modify it
......@@ -47,8 +46,8 @@ void __init prom_init(void)
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
......@@ -56,6 +55,6 @@ void __init prom_init(void)
if (!memsize_str)
memsize = 0x04000000;
else
memsize = simple_strtol(memsize_str, NULL, 0);
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/mtx-1/irqmap.c
View file @ 8d97b849
......@@ -31,18 +31,18 @@
#include <asm/mach-au1x00/au1000.h>
char irq_tab_alchemy[][5] __initdata = {
[0] = { -1, INTA, INTA, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
[1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
[2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
[3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
[4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
[5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
[6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
[7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
[0] = { -1, INTA, INTA, INTX, INTX }, /* IDSEL 00 - AdapterA-Slot0 (top) */
[1] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
[2] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 02 - AdapterB-Slot0 (top) */
[3] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
[4] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 04 - AdapterC-Slot0 (top) */
[5] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
[6] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 06 - AdapterD-Slot0 (top) */
[7] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
};
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
......
arch/mips/au1000/mtx-1/platform.c
View file @ 8d97b849
......@@ -21,11 +21,10 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <asm/gpio.h>
static struct gpio_keys_button mtx1_gpio_button[] = {
{
.gpio = 207,
......
arch/mips/au1000/pb1000/Makefile
View file @ 8d97b849
#
# Copyright 2000 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Semiconductor Pb1000 board.
#
# Makefile for the Alchemy Semiconductor PB1000 board.
lib-y := init.o board_setup.o irqmap.o
arch/mips/au1000/pb1000/board_setup.c
View file @ 8d97b849
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -40,128 +39,126 @@ void __init board_setup(void)
u32 sys_freqctrl, sys_clksrc;
u32 prid = read_c0_prid();
// set AUX clock to 12MHz * 8 = 96 MHz
/* Set AUX clock to 12 MHz * 8 = 96 MHz */
au_writel(8, SYS_AUXPLL);
au_writel(0, SYS_PINSTATERD);
udelay(100);
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* zero and disable FREQ2 */
/* Zero and disable FREQ2 */
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
/* Zero and disable USBH/USBD clocks */
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
au_writel(sys_clksrc, SYS_CLKSRC);
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
switch (prid & 0x000000FF)
{
switch (prid & 0x000000FF) {
case 0x00: /* DA */
case 0x01: /* HA */
case 0x02: /* HB */
/* CPU core freq to 48MHz to slow it way down... */
au_writel(4, SYS_CPUPLL);
/* CPU core freq to 48 MHz to slow it way down... */
au_writel(4, SYS_CPUPLL);
/*
* Setup 48MHz FREQ2 from CPUPLL for USB Host
*/
/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/*
* Setup 48 MHz FREQ2 from CPUPLL for USB Host
* FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
*/
sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* CPU core freq to 384MHz */
au_writel(0x20, SYS_CPUPLL);
/* CPU core freq to 384 MHz */
au_writel(0x20, SYS_CPUPLL);
printk("Au1000: 48MHz OHCI workaround enabled\n");
printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
break;
default: /* HC and newer */
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
au_writel(sys_freqctrl, SYS_FREQCTRL0);
default: /* HC and newer */
/* FREQ2 = aux / 2 = 48 MHz */
sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
SYS_FC_FE2 | SYS_FC_FS2;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
break;
}
/*
* Route 48MHz FREQ2 into USB Host and/or Device
* Route 48 MHz FREQ2 into USB Host and/or Device
*/
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
#endif
sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
au_writel(sys_clksrc, SYS_CLKSRC);
// configure pins GPIO[14:9] as GPIO
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
/* Configure pins GPIO[14:9] as GPIO */
pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
// 2nd USB port is USB host
pin_func |= 0x8000;
/* 2nd USB port is USB host */
pin_func |= SYS_PF_USB;
au_writel(pin_func, SYS_PINFUNC);
au_writel(0x2800, SYS_TRIOUTCLR);
au_writel(0x0030, SYS_OUTPUTCLR);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
// make gpio 15 an input (for interrupt line)
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
// we don't need I2S, so make it available for GPIO[31:29]
pin_func |= (1<<5);
/* Make GPIO 15 an input (for interrupt line) */
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
/* We don't need I2S, so make it available for GPIO[31:29] */
pin_func |= SYS_PF_I2S;
au_writel(pin_func, SYS_PINFUNC);
au_writel(0x8000, SYS_TRIOUTCLR);
static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
au_writel(static_cfg0, MEM_STCFG0);
// configure RCE2* for LCD
/* configure RCE2* for LCD */
au_writel(0x00000004, MEM_STCFG2);
// MEM_STTIME2
/* MEM_STTIME2 */
au_writel(0x09000000, MEM_STTIME2);
// Set 32-bit base address decoding for RCE2*
/* Set 32-bit base address decoding for RCE2* */
au_writel(0x10003ff0, MEM_STADDR2);
// PCI CPLD setup
// expand CE0 to cover PCI
/*
* PCI CPLD setup
* Expand CE0 to cover PCI
*/
au_writel(0x11803e40, MEM_STADDR1);
// burst visibility on
/* Burst visibility on */
au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
/* setup the static bus controller */
/* Setup the static bus controller */
au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
#ifdef CONFIG_PCI
au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
au_writel(0, SDRAM_MBAR); // set mbar to 0
au_writel(0x2, SDRAM_CMD); // enable memory accesses
au_sync_delay(1);
#endif
/* Enable Au1000 BCLK switching - note: sed1356 must not use
* its BCLK (Au1000 LCLK) for any timings */
switch (prid & 0x000000FF)
{
/*
* Enable Au1000 BCLK switching - note: sed1356 must not use
* its BCLK (Au1000 LCLK) for any timings
*/
switch (prid & 0x000000FF) {
case 0x00: /* DA */
case 0x01: /* HA */
case 0x02: /* HB */
break;
default: /* HC and newer */
/* Enable sys bus clock divider when IDLE state or no bus
activity. */
/*
* Enable sys bus clock divider when IDLE state or no bus
* activity.
*/
au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
break;
}
......
arch/mips/au1000/pb1000/init.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* PB1000 board setup
* Pb1000 board setup
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -44,16 +43,15 @@ void __init prom_init(void)
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int) fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
if (!memsize_str)
memsize = 0x04000000;
} else {
memsize = simple_strtol(memsize_str, NULL, 0);
}
else
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/pb1100/Makefile
View file @ 8d97b849
#
# Copyright 2000,2001 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2001, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Semiconductor Pb1100 board.
#
lib-y := init.o board_setup.o irqmap.o
arch/mips/au1000/pb1100/board_setup.c
View file @ 8d97b849
/*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2002, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -32,15 +31,15 @@
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
/* Hit BCSR.RST_VDDI[SOFT_RESET] */
au_writel(0x00000000, PB1100_RST_VDDI);
}
void __init board_setup(void)
{
volatile void __iomem * base = (volatile void __iomem *) 0xac000000UL;
volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
// set AUX clock to 12MHz * 8 = 96 MHz
/* Set AUX clock to 12 MHz * 8 = 96 MHz */
au_writel(8, SYS_AUXPLL);
au_writel(0, SYS_PININPUTEN);
udelay(100);
......@@ -49,44 +48,47 @@ void __init board_setup(void)
{
u32 pin_func, sys_freqctrl, sys_clksrc;
// configure pins GPIO[14:9] as GPIO
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80);
/* Configure pins GPIO[14:9] as GPIO */
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
/* zero and disable FREQ2 */
/* Zero and disable FREQ2 */
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD/IrDA clock */
/* Zero and disable USBH/USBD/IrDA clock */
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x0000001F;
sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
au_writel(sys_clksrc, SYS_CLKSRC);
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x0000001F;
sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
/* FREQ2 = aux / 2 = 48 MHz */
sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
SYS_FC_FE2 | SYS_FC_FS2;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/*
* Route 48MHz FREQ2 into USBH/USBD/IrDA
* Route 48 MHz FREQ2 into USBH/USBD/IrDA
*/
sys_clksrc |= ((4<<2) | (0<<1) | 0 );
sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
au_writel(sys_clksrc, SYS_CLKSRC);
/* setup the static bus controller */
/* Setup the static bus controller */
au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
// get USB Functionality pin state (device vs host drive pins)
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
// 2nd USB port is USB host
pin_func |= 0x8000;
/*
* Get USB Functionality pin state (device vs host drive pins).
*/
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
/* 2nd USB port is USB host. */
pin_func |= SYS_PF_USB;
au_writel(pin_func, SYS_PINFUNC);
}
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
......@@ -94,12 +96,12 @@ void __init board_setup(void)
/* Enable sys bus clock divider when IDLE state or no bus activity. */
au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
// Enable the RTC if not already enabled
/* Enable the RTC if not already enabled. */
if (!(readb(base + 0x28) & 0x20)) {
writeb(readb(base + 0x28) | 0x20, base + 0x28);
au_sync();
}
// Put the clock in BCD mode
/* Put the clock in BCD mode. */
if (readb(base + 0x2C) & 0x4) { /* reg B */
writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
au_sync();
......
arch/mips/au1000/pb1100/init.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* Pb1100 board setup
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2002, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -46,8 +45,8 @@ void __init prom_init(void)
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg3;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg3;
prom_init_cmdline();
......@@ -55,7 +54,7 @@ void __init prom_init(void)
if (!memsize_str)
memsize = 0x04000000;
else
memsize = simple_strtol(memsize_str, NULL, 0);
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/pb1100/irqmap.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* Au1xxx irq map table
* Au1xx0 IRQ map table
*
* Copyright 2003 Embedded Edge, LLC
* dan@embeddededge.com
......@@ -31,10 +31,10 @@
#include <asm/mach-au1x00/au1000.h>
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
{ AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ#
{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */
{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */
{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */
{ AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */
};
int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
arch/mips/au1000/pb1200/Makefile
View file @ 8d97b849
#
# Makefile for the Alchemy Semiconductor PB1200 board.
# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
#
lib-y := init.o board_setup.o irqmap.o
......
arch/mips/au1000/pb1200/board_setup.c
View file @ 8d97b849
......@@ -27,16 +27,8 @@
#include <linux/init.h>
#include <linux/sched.h>
#include <au1000.h>
#include <prom.h>
#ifdef CONFIG_MIPS_PB1200
#include <asm/mach-pb1x00/pb1200.h>
#endif
#ifdef CONFIG_MIPS_DB1200
#include <asm/mach-db1x00/db1200.h>
#endif
#include <au1xxx.h>
extern void _board_init_irq(void);
extern void (*board_init_irq)(void);
......@@ -53,56 +45,57 @@ void __init board_setup(void)
#if 0
{
u32 pin_func;
/* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
* but it is board specific code, so put it here.
*/
pin_func = au_readl(SYS_PINFUNC);
au_sync();
pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
au_writel(pin_func, SYS_PINFUNC);
au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
au_sync();
u32 pin_func;
/*
* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
* but it is board specific code, so put it here.
*/
pin_func = au_readl(SYS_PINFUNC);
au_sync();
pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
au_writel(pin_func, SYS_PINFUNC);
au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
au_sync();
}
#endif
#if defined(CONFIG_I2C_AU1550)
{
u32 freq0, clksrc;
u32 pin_func;
/* Select SMBUS in CPLD */
bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
pin_func = au_readl(SYS_PINFUNC);
au_sync();
pin_func &= ~(3<<17 | 1<<4);
/* Set GPIOs correctly */
pin_func |= 2<<17;
au_writel(pin_func, SYS_PINFUNC);
au_sync();
/* The i2c driver depends on 50Mhz clock */
freq0 = au_readl(SYS_FREQCTRL0);
au_sync();
freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
freq0 |= (3<<SYS_FC_FRDIV1_BIT);
/* 396Mhz / (3+1)*2 == 49.5Mhz */
au_writel(freq0, SYS_FREQCTRL0);
au_sync();
freq0 |= SYS_FC_FE1;
au_writel(freq0, SYS_FREQCTRL0);
au_sync();
clksrc = au_readl(SYS_CLKSRC);
au_sync();
clksrc &= ~0x01f00000;
/* bit 22 is EXTCLK0 for PSC0 */
clksrc |= (0x3 << 22);
au_writel(clksrc, SYS_CLKSRC);
au_sync();
u32 freq0, clksrc;
u32 pin_func;
/* Select SMBus in CPLD */
bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
pin_func = au_readl(SYS_PINFUNC);
au_sync();
pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
/* Set GPIOs correctly */
pin_func |= 2 << 17;
au_writel(pin_func, SYS_PINFUNC);
au_sync();
/* The I2C driver depends on 50 MHz clock */
freq0 = au_readl(SYS_FREQCTRL0);
au_sync();
freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
freq0 |= 3 << SYS_FC_FRDIV1_BIT;
/* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
au_writel(freq0, SYS_FREQCTRL0);
au_sync();
freq0 |= SYS_FC_FE1;
au_writel(freq0, SYS_FREQCTRL0);
au_sync();
clksrc = au_readl(SYS_CLKSRC);
au_sync();
clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
/* Bit 22 is EXTCLK0 for PSC0 */
clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
au_writel(clksrc, SYS_CLKSRC);
au_sync();
}
#endif
......@@ -116,27 +109,27 @@ void __init board_setup(void)
#endif
#endif
/* The Pb1200 development board uses external MUX for PSC0 to
support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
*/
/*
* The Pb1200 development board uses external MUX for PSC0 to
* support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
*/
#ifdef CONFIG_I2C_AU1550
bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
#endif
au_sync();
#ifdef CONFIG_MIPS_PB1200
printk("AMD Alchemy Pb1200 Board\n");
printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
#endif
#ifdef CONFIG_MIPS_DB1200
printk("AMD Alchemy Db1200 Board\n");
printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
#endif
/* Setup Pb1200 External Interrupt Controller */
board_init_irq = _board_init_irq;
}
int
board_au1200fb_panel(void)
int board_au1200fb_panel(void)
{
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
int p;
......@@ -147,23 +140,23 @@ board_au1200fb_panel(void)
return p;
}
int
board_au1200fb_panel_init(void)
int board_au1200fb_panel_init(void)
{
/* Apply power */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
/*printk("board_au1200fb_panel_init()\n"); */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
/* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
return 0;
}
int
board_au1200fb_panel_shutdown(void)
int board_au1200fb_panel_shutdown(void)
{
/* Remove power */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
/*printk("board_au1200fb_panel_shutdown()\n"); */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
BCSR_BOARD_LCDBL);
/* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
return 0;
}
arch/mips/au1000/pb1200/init.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* PB1200 board setup
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -45,16 +44,15 @@ void __init prom_init(void)
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int) fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
if (!memsize_str)
memsize = 0x08000000;
} else {
memsize = simple_strtol(memsize_str, NULL, 0);
}
else
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/pb1200/irqmap.c
View file @ 8d97b849
......@@ -39,25 +39,25 @@
#endif
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
/* This is external interrupt cascade */
{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 },
};
int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
/*
* Support for External interrupts on the PbAu1200 Development platform.
* Support for External interrupts on the Pb1200 Development platform.
*/
static volatile int pb1200_cascade_en=0;
static volatile int pb1200_cascade_en;
irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
irqreturn_t pb1200_cascade_handler(int irq, void *dev_id)
{
unsigned short bisr = bcsr->int_status;
int extirq_nr = 0;
/* Clear all the edge interrupts. This has no effect on level */
/* Clear all the edge interrupts. This has no effect on level. */
bcsr->int_status = bisr;
for( ; bisr; bisr &= (bisr-1) )
{
for ( ; bisr; bisr &= bisr - 1) {
extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
/* Ack and dispatch IRQ */
do_IRQ(extirq_nr);
......@@ -68,26 +68,20 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
inline void pb1200_enable_irq(unsigned int irq_nr)
{
bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
}
inline void pb1200_disable_irq(unsigned int irq_nr)
{
bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
}
static unsigned int pb1200_setup_cascade(void)
{
int err;
err = request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
0, "Pb1200 Cascade", &pb1200_cascade_handler);
if (err)
return err;
return 0;
return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
0, "Pb1200 Cascade", &pb1200_cascade_handler);
}
static unsigned int pb1200_startup_irq(unsigned int irq)
......@@ -132,23 +126,23 @@ void _board_init_irq(void)
unsigned int irq;
#ifdef CONFIG_MIPS_PB1200
/* We have a problem with CPLD rev3. Enable a workaround */
/* We have a problem with CPLD rev 3. */
if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
printk("updated to latest revision. This software will not\n");
printk("work on anything less than CPLD rev4\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk("\nWARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
printk(KERN_ERR "updated to latest revision. This software will\n");
printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
printk(KERN_ERR "WARNING!!!\n");
panic("Game over. Your score is 0.");
}
#endif
......@@ -161,6 +155,6 @@ void _board_init_irq(void)
/*
* GPIO_7 can not be hooked here, so it is hooked upon first
* request of any source attached to the cascade
* request of any source attached to the cascade.
*/
}
arch/mips/au1000/pb1500/Makefile
View file @ 8d97b849
#
# Copyright 2000,2001 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2001, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Semiconductor Pb1500 board.
#
lib-y := init.o board_setup.o irqmap.o
arch/mips/au1000/pb1500/board_setup.c
View file @ 8d97b849
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -32,8 +31,8 @@
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
/* Hit BCSR.RST_VDDI[SOFT_RESET] */
au_writel(0x00000000, PB1500_RST_VDDI);
}
void __init board_setup(void)
......@@ -42,7 +41,7 @@ void __init board_setup(void)
u32 sys_freqctrl, sys_clksrc;
sys_clksrc = sys_freqctrl = pin_func = 0;
// set AUX clock to 12MHz * 8 = 96 MHz
/* Set AUX clock to 12 MHz * 8 = 96 MHz */
au_writel(8, SYS_AUXPLL);
au_writel(0, SYS_PINSTATERD);
udelay(100);
......@@ -51,51 +50,48 @@ void __init board_setup(void)
/* GPIO201 is input for PCMCIA card detect */
/* GPIO203 is input for PCMCIA interrupt request */
au_writel(au_readl(GPIO2_DIR) & (u32)(~((1<<1)|(1<<3))), GPIO2_DIR);
au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR);
/* zero and disable FREQ2 */
/* Zero and disable FREQ2 */
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
au_writel(sys_clksrc, SYS_CLKSRC);
sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
/* FREQ2 = aux/2 = 48 MHz */
sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
au_writel(sys_freqctrl, SYS_FREQCTRL0);
/*
* Route 48MHz FREQ2 into USB Host and/or Device
*/
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
#endif
sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
au_writel(sys_clksrc, SYS_CLKSRC);
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
// 2nd USB port is USB host
pin_func |= 0x8000;
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
/* 2nd USB port is USB host */
pin_func |= SYS_PF_USB;
au_writel(pin_func, SYS_PINFUNC);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
// Setup PCI bus controller
/* Setup PCI bus controller */
au_writel(0, Au1500_PCI_CMEM);
au_writel(0x00003fff, Au1500_CFG_BASE);
#if defined(__MIPSEB__)
au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
......@@ -112,11 +108,11 @@ void __init board_setup(void)
/* Enable the RTC if not already enabled */
if (!(au_readl(0xac000028) & 0x20)) {
printk("enabling clock ...\n");
printk(KERN_INFO "enabling clock ...\n");
au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
}
/* Put the clock in BCD mode */
if (au_readl(0xac00002C) & 0x4) { /* reg B */
if (au_readl(0xac00002c) & 0x4) { /* reg B */
au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
au_sync();
}
......
arch/mips/au1000/pb1500/init.c
View file @ 8d97b849
/*
*
* BRIEF MODULE DESCRIPTION
* PB1500 board setup
* Pb1500 board setup
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -45,16 +44,15 @@ void __init prom_init(void)
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int) fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
if (!memsize_str)
memsize = 0x04000000;
} else {
memsize = simple_strtol(memsize_str, NULL, 0);
}
else
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/pb1500/irqmap.c
View file @ 8d97b849
......@@ -31,12 +31,12 @@
#include <asm/mach-au1x00/au1000.h>
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
};
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
......
arch/mips/au1000/pb1550/Makefile
View file @ 8d97b849
#
# Copyright 2000 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Copyright 2000, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for the Alchemy Semiconductor PB1000 board.
# Makefile for the Alchemy Semiconductor Pb1550 board.
#
lib-y := init.o board_setup.o irqmap.o
arch/mips/au1000/pb1550/board_setup.c
View file @ 8d97b849
......@@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* Alchemy Pb1550 board setup.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -35,15 +34,16 @@
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
/* Hit BCSR.SYSTEM[RESET] */
au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
}
void __init board_setup(void)
{
u32 pin_func;
/* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
/*
* Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
* but it is board specific code, so put it here.
*/
pin_func = au_readl(SYS_PINFUNC);
......@@ -51,8 +51,8 @@ void __init board_setup(void)
pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
au_writel(pin_func, SYS_PINFUNC);
au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
au_sync();
printk("AMD Alchemy Pb1550 Board\n");
printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
}
arch/mips/au1000/pb1550/init.c
View file @ 8d97b849
/*
*
* BRIEF MODULE DESCRIPTION
* PB1550 board setup
* Pb1550 board setup
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -45,16 +44,15 @@ void __init prom_init(void)
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int) fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
if (!memsize_str)
memsize = 0x08000000;
} else {
memsize = simple_strtol(memsize_str, NULL, 0);
}
else
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/pb1550/irqmap.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* Au1xxx irq map table
* Au1xx0 IRQ map table
*
* Copyright 2003 Embedded Edge, LLC
* dan@embeddededge.com
......@@ -31,8 +31,8 @@
#include <asm/mach-au1x00/au1000.h>
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
[12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
......
arch/mips/au1000/xxs1500/Makefile
View file @ 8d97b849
#
# Copyright 2003 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for MyCable XXS1500 board.
#
......
arch/mips/au1000/xxs1500/board_setup.c
View file @ 8d97b849
/*
* Copyright 2000-2003 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000-2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -39,40 +38,40 @@ void __init board_setup(void)
{
u32 pin_func;
// set multiple use pins (UART3/GPIO) to UART (it's used as UART too)
pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3);
/* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
pin_func |= SYS_PF_UR3;
au_writel(pin_func, SYS_PINFUNC);
// enable UART
au_writel(0x01, UART3_ADDR+UART_MOD_CNTRL); // clock enable (CE)
/* Enable UART */
au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
mdelay(10);
au_writel(0x03, UART3_ADDR+UART_MOD_CNTRL); // CE and "enable"
au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
mdelay(10);
// enable DTR = USB power up
au_writel(0x01, UART3_ADDR+UART_MCR); //? UART_MCR_DTR is 0x01???
/* Enable DTR = USB power up */
au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
#ifdef CONFIG_PCMCIA_XXS1500
/* setup pcmcia signals */
/* Setup PCMCIA signals */
au_writel(0, SYS_PININPUTEN);
/* gpio 0, 1, and 4 are inputs */
au_writel(1 | (1<<1) | (1<<4), SYS_TRIOUTCLR);
/* GPIO 0, 1, and 4 are inputs */
au_writel(1 | (1 << 1) | (1 << 4), SYS_TRIOUTCLR);
/* enable GPIO2 if not already enabled */
/* Enable GPIO2 if not already enabled */
au_writel(1, GPIO2_ENABLE);
/* gpio2 208/9/10/11 are inputs */
au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR);
/* GPIO2 208/9/10/11 are inputs */
au_writel((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11), GPIO2_DIR);
/* turn off power */
au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT);
/* Turn off power */
au_writel((au_readl(GPIO2_PINSTATE) & ~(1 << 14)) | (1 << 30),
GPIO2_OUTPUT);
#endif
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
......
arch/mips/au1000/xxs1500/init.c
View file @ 8d97b849
......@@ -2,9 +2,8 @@
* BRIEF MODULE DESCRIPTION
* XXS1500 board setup
*
* Copyright 2003 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -45,8 +44,8 @@ void __init prom_init(void)
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
......@@ -54,6 +53,6 @@ void __init prom_init(void)
if (!memsize_str)
memsize = 0x04000000;
else
memsize = simple_strtol(memsize_str, NULL, 0);
memsize = strict_strtol(memsize_str, 0, NULL);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/au1000/xxs1500/irqmap.c
View file @ 8d97b849
......@@ -31,7 +31,7 @@
#include <asm/mach-au1x00/au1000.h>
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
{ AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
......
arch/mips/emma2rh/markeins/setup.c
View file @ 8d97b849
......@@ -76,7 +76,9 @@ static void markeins_machine_power_off(void)
while (1) ;
}
static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 };
static unsigned long __initdata emma2rh_clock[4] = {
166500000, 187312500, 199800000, 210600000
};
static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
{
......@@ -85,7 +87,8 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
/* detect from boot strap */
reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
reg = (reg >> 4) & 0x3;
return clock[reg];
return emma2rh_clock[reg];
}
void __init plat_time_init(void)
......
arch/mips/kernel/Makefile
View file @ 8d97b849
......@@ -56,9 +56,9 @@ obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
obj-$(CONFIG_CPU_MIPSR2) += spram.o
obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
obj-$(CONFIG_I8259) += i8259.o
obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
......
arch/mips/kernel/cpu-bugs64.c
View file @ 8d97b849
......@@ -38,7 +38,7 @@ static inline void align_mod(const int align, const int mod)
".endr\n\t"
".set pop"
:
: GCC_IMM_ASM(align), GCC_IMM_ASM(mod));
: GCC_IMM_ASM() (align), GCC_IMM_ASM() (mod));
}
static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
......
arch/mips/kernel/irixelf.c
View file @ 8d97b849
......@@ -578,7 +578,7 @@ static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp,
* process and the system, here we map the page and fill the
* structure
*/
static void irix_map_prda_page(void)
static int irix_map_prda_page(void)
{
unsigned long v;
struct prda *pp;
......@@ -587,8 +587,8 @@ static void irix_map_prda_page(void)
v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
up_write(&current->mm->mmap_sem);
if (v < 0)
return;
if (v != PRDA_ADDRESS)
return v; /* v must be an error code */
pp = (struct prda *) v;
pp->prda_sys.t_pid = task_pid_vnr(current);
......@@ -596,6 +596,8 @@ static void irix_map_prda_page(void)
pp->prda_sys.t_rpid = task_pid_vnr(current);
/* We leave the rest set to zero */
return 0;
}
......@@ -781,7 +783,8 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
* IRIX maps a page at 0x200000 which holds some system
* information. Programs depend on this.
*/
irix_map_prda_page();
if (irix_map_prda_page())
goto out_free_dentry;
padzero(elf_bss);
......
arch/mips/kernel/kspd.c
View file @ 8d97b849
......@@ -257,7 +257,7 @@ void sp_work_handle_request(void)
vcwd = vpe_getcwd(tclimit);
/* change to the cwd of the process that loaded the SP program */
/* change to cwd of the process that loaded the SP program */
old_fs = get_fs();
set_fs(KERNEL_DS);
sys_chdir(vcwd);
......@@ -323,6 +323,9 @@ static void sp_cleanup(void)
set >>= 1;
}
}
/* Put daemon cwd back to root to avoid umount problems */
sys_chdir("/");
}
static int channel_open = 0;
......
arch/mips/kernel/rtlx.c
View file @ 8d97b849
......@@ -72,6 +72,15 @@ static void rtlx_dispatch(void)
static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
{
int i;
unsigned int flags, vpeflags;
/* Ought not to be strictly necessary for SMTC builds */
local_irq_save(flags);
vpeflags = dvpe();
set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
irq_enable_hazard();
evpe(vpeflags);
local_irq_restore(flags);
for (i = 0; i < RTLX_CHANNELS; i++) {
wake_up(&channel_wqs[i].lx_queue);
......@@ -108,7 +117,8 @@ static void __used dump_rtlx(void)
static int rtlx_init(struct rtlx_info *rtlxi)
{
if (rtlxi->id != RTLX_ID) {
printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id);
printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n",
rtlxi, rtlxi->id);
return -ENOEXEC;
}
......@@ -162,18 +172,17 @@ int rtlx_open(int index, int can_sleep)
if (rtlx == NULL) {
if( (p = vpe_get_shared(tclimit)) == NULL) {
if (can_sleep) {
__wait_event_interruptible(channel_wqs[index].lx_queue,
(p = vpe_get_shared(tclimit)),
ret);
if (ret)
goto out_fail;
} else {
printk(KERN_DEBUG "No SP program loaded, and device "
"opened with O_NONBLOCK\n");
ret = -ENOSYS;
if (can_sleep) {
__wait_event_interruptible(channel_wqs[index].lx_queue,
(p = vpe_get_shared(tclimit)), ret);
if (ret)
goto out_fail;
}
} else {
printk(KERN_DEBUG "No SP program loaded, and device "
"opened with O_NONBLOCK\n");
ret = -ENOSYS;
goto out_fail;
}
}
smp_rmb();
......@@ -182,7 +191,9 @@ int rtlx_open(int index, int can_sleep)
DEFINE_WAIT(wait);
for (;;) {
prepare_to_wait(&channel_wqs[index].lx_queue, &wait, TASK_INTERRUPTIBLE);
prepare_to_wait(
&channel_wqs[index].lx_queue,
&wait, TASK_INTERRUPTIBLE);
smp_rmb();
if (*p != NULL)
break;
......@@ -195,7 +206,7 @@ int rtlx_open(int index, int can_sleep)
}
finish_wait(&channel_wqs[index].lx_queue, &wait);
} else {
printk(" *vpe_get_shared is NULL. "
pr_err(" *vpe_get_shared is NULL. "
"Has an SP program been loaded?\n");
ret = -ENOSYS;
goto out_fail;
......@@ -203,8 +214,9 @@ int rtlx_open(int index, int can_sleep)
}
if ((unsigned int)*p < KSEG0) {
printk(KERN_WARNING "vpe_get_shared returned an invalid pointer "
"maybe an error code %d\n", (int)*p);
printk(KERN_WARNING "vpe_get_shared returned an "
"invalid pointer maybe an error code %d\n",
(int)*p);
ret = -ENOSYS;
goto out_fail;
}
......@@ -232,6 +244,10 @@ int rtlx_open(int index, int can_sleep)
int rtlx_release(int index)
{
if (rtlx == NULL) {
pr_err("rtlx_release() with null rtlx\n");
return 0;
}
rtlx->channel[index].lx_state = RTLX_STATE_UNUSED;
return 0;
}
......@@ -251,8 +267,8 @@ unsigned int rtlx_read_poll(int index, int can_sleep)
int ret = 0;
__wait_event_interruptible(channel_wqs[index].lx_queue,
chan->lx_read != chan->lx_write || sp_stopping,
ret);
(chan->lx_read != chan->lx_write) ||
sp_stopping, ret);
if (ret)
return ret;
......@@ -282,7 +298,9 @@ static inline int write_spacefree(int read, int write, int size)
unsigned int rtlx_write_poll(int index)
{
struct rtlx_channel *chan = &rtlx->channel[index];
return write_spacefree(chan->rt_read, chan->rt_write, chan->buffer_size);
return write_spacefree(chan->rt_read, chan->rt_write,
chan->buffer_size);
}
ssize_t rtlx_read(int index, void __user *buff, size_t count)
......@@ -344,8 +362,8 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
rt_read = rt->rt_read;
/* total number of bytes to copy */
count = min(count,
(size_t)write_spacefree(rt_read, rt->rt_write, rt->buffer_size));
count = min(count, (size_t)write_spacefree(rt_read, rt->rt_write,
rt->buffer_size));
/* first bit from write pointer to the end of the buffer, or count */
fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
......@@ -514,6 +532,11 @@ static int __init rtlx_module_init(void)
if (cpu_has_vint)
set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
else {
pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
err = -ENODEV;
goto out_chrdev;
}
rtlx_irq.dev_id = rtlx;
setup_irq(rtlx_irq_num, &rtlx_irq);
......
arch/mips/kernel/setup.c
View file @ 8d97b849
......@@ -331,6 +331,7 @@ static void __init bootmem_init(void)
/*
* Determine low and high memory ranges
*/
max_pfn = max_low_pfn;
if (max_low_pfn > PFN_DOWN(HIGHMEM_START)) {
#ifdef CONFIG_HIGHMEM
highstart_pfn = PFN_DOWN(HIGHMEM_START);
......
arch/mips/kernel/smp.c
View file @ 8d97b849
......@@ -87,8 +87,8 @@ struct plat_smp_ops *mp_ops;
__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
{
if (ops)
printk(KERN_WARNING "Overriding previous set SMP ops\n");
if (mp_ops)
printk(KERN_WARNING "Overriding previously set SMP ops\n");
mp_ops = ops;
}
......
arch/mips/kernel/vpe.c
View file @ 8d97b849
......@@ -269,7 +269,7 @@ static void *alloc_progmem(unsigned long len)
* This means you must tell Linux to use less memory than you
* physically have, for example by passing a mem= boot argument.
*/
addr = pfn_to_kaddr(max_pfn);
addr = pfn_to_kaddr(max_low_pfn);
memset(addr, 0, len);
#else
/* simple grab some mem for now */
......@@ -781,10 +781,15 @@ static int vpe_run(struct vpe * v)
/* take system out of configuration state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
/*
* SMTC/SMVP kernels manage VPE enable independently,
* but uniprocessor kernels need to turn it on, even
* if that wasn't the pre-dvpe() state.
*/
#ifdef CONFIG_SMP
evpe(EVPE_ENABLE);
#else
evpe(vpeflags);
#else
evpe(EVPE_ENABLE);
#endif
emt(dmt_flag);
local_irq_restore(flags);
......@@ -840,7 +845,7 @@ static int vpe_elfload(struct vpe * v)
/* Sanity checks against insmoding binaries or wrong arch,
weird elf version */
if (memcmp(hdr->e_ident, ELFMAG, 4) != 0
if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0
|| (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC)
|| !elf_check_arch(hdr)
|| hdr->e_shentsize != sizeof(*sechdrs)) {
......@@ -947,12 +952,14 @@ static int vpe_elfload(struct vpe * v)
struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
for (i = 0; i < hdr->e_phnum; i++) {
if (phdr->p_type != PT_LOAD)
continue;
memcpy((void *)phdr->p_paddr, (char *)hdr + phdr->p_offset, phdr->p_filesz);
memset((void *)phdr->p_paddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz);
phdr++;
if (phdr->p_type == PT_LOAD) {
memcpy((void *)phdr->p_paddr,
(char *)hdr + phdr->p_offset,
phdr->p_filesz);
memset((void *)phdr->p_paddr + phdr->p_filesz,
0, phdr->p_memsz - phdr->p_filesz);
}
phdr++;
}
for (i = 0; i < hdr->e_shnum; i++) {
......@@ -1107,7 +1114,7 @@ static int vpe_release(struct inode *inode, struct file *filp)
return -ENODEV;
hdr = (Elf_Ehdr *) v->pbuffer;
if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) {
if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) {
if (vpe_elfload(v) >= 0) {
vpe_run(v);
} else {
......
arch/mips/mm/highmem.c
View file @ 8d97b849
......@@ -116,4 +116,3 @@ EXPORT_SYMBOL(__kmap);
EXPORT_SYMBOL(__kunmap);
EXPORT_SYMBOL(__kmap_atomic);
EXPORT_SYMBOL(__kunmap_atomic);
EXPORT_SYMBOL(__kmap_atomic_to_page);
arch/mips/oprofile/op_model_mipsxx.c
View file @ 8d97b849
......@@ -281,7 +281,7 @@ static inline int n_counters(void)
static void reset_counters(void *arg)
{
int counters = (int)arg;
int counters = (int)(long)arg;
switch (counters) {
case 4:
w_c0_perfctrl3(0);
......@@ -313,7 +313,7 @@ static int __init mipsxx_init(void)
if (!cpu_has_mipsmt_pertccounters)
counters = counters_total_to_per_cpu(counters);
#endif
on_each_cpu(reset_counters, (void *)counters, 0, 1);
on_each_cpu(reset_counters, (void *)(long)counters, 0, 1);
op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_type()) {
......@@ -382,7 +382,7 @@ static void mipsxx_exit(void)
int counters = op_model_mipsxx_ops.num_counters;
counters = counters_per_cpu_to_total(counters);
on_each_cpu(reset_counters, (void *)counters, 0, 1);
on_each_cpu(reset_counters, (void *)(long)counters, 0, 1);
perf_irq = save_perf_irq;
}
......
arch/mips/pci/fixup-au1000.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* Board specific pci fixups.
* Board specific PCI fixups.
*
* Copyright 2001-2003 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001-2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......
arch/mips/pci/ops-au1000.c
View file @ 8d97b849
/*
* BRIEF MODULE DESCRIPTION
* Alchemy/AMD Au1x00 PCI support.
* Alchemy/AMD Au1xx0 PCI support.
*
* Copyright 2001-2003, 2007 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* Support for all devices (greater than 16) added by David Gathright.
*
......@@ -28,6 +27,7 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
......@@ -36,9 +36,9 @@
#include <asm/mach-au1x00/au1000.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(KERN_DEBUG x)
#else
#define DBG(x...)
#endif
......@@ -46,7 +46,6 @@
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
int (*board_pci_idsel)(unsigned int devsel, int assert);
void mod_wired_entry(int entry, unsigned long entrylo0,
......@@ -92,10 +91,9 @@ void __init au1x_pci_cfg_init(void)
}
static int config_access(unsigned char access_type, struct pci_bus *bus,
unsigned int dev_fn, unsigned char where,
u32 * data)
unsigned int dev_fn, unsigned char where, u32 *data)
{
#if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
unsigned int device = PCI_SLOT(dev_fn);
unsigned int function = PCI_FUNC(dev_fn);
unsigned long offset, status;
......@@ -114,38 +112,36 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
Au1500_PCI_STATCMD);
au_sync_udelay(1);
/* Allow board vendors to implement their own off-chip idsel.
/*
* Allow board vendors to implement their own off-chip IDSEL.
* If it doesn't succeed, may as well bail out at this point.
*/
if (board_pci_idsel) {
if (board_pci_idsel(device, 1) == 0) {
*data = 0xffffffff;
local_irq_restore(flags);
return -1;
}
if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
*data = 0xffffffff;
local_irq_restore(flags);
return -1;
}
/* setup the config window */
if (bus->number == 0) {
cfg_base = ((1<<device)<<11);
} else {
cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
}
/* Setup the config window */
if (bus->number == 0)
cfg_base = (1 << device) << 11;
else
cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
/* setup the lower bits of the 36 bit address */
offset = (function << 8) | (where & ~0x3);
/* pick up any address that falls below the page mask */
/* Setup the lower bits of the 36-bit address */
offset = (function << 8) | (where & ~0x3);
/* Pick up any address that falls below the page mask */
offset |= cfg_base & ~PAGE_MASK;
/* page boundary */
/* Page boundary */
cfg_base = cfg_base & PAGE_MASK;
/*
* To improve performance, if the current device is the same as
* the last device accessed, we don't touch the TLB.
*/
entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
(unsigned long)pci_cfg_vm->addr, PM_4K);
......@@ -153,38 +149,37 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
last_entryLo1 = entryLo1;
}
if (access_type == PCI_ACCESS_WRITE) {
if (access_type == PCI_ACCESS_WRITE)
au_writel(*data, (int)(pci_cfg_vm->addr + offset));
} else {
else
*data = au_readl((int)(pci_cfg_vm->addr + offset));
}
au_sync_udelay(2);
DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
access_type, bus->number, device, where, *data, offset);
DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
access_type, bus->number, device, where, *data, offset);
/* check master abort */
/* Check master abort */
status = au_readl(Au1500_PCI_STATCMD);
if (status & (1<<29)) {
if (status & (1 << 29)) {
*data = 0xffffffff;
error = -1;
DBG("Au1x Master Abort\n");
} else if ((status >> 28) & 0xf) {
DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));
DBG("PCI ERR detected: device %u, status %lx\n",
device, (status >> 28) & 0xf);
/* clear errors */
/* Clear errors */
au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
*data = 0xffffffff;
error = -1;
}
/* Take away the idsel.
*/
if (board_pci_idsel) {
/* Take away the IDSEL. */
if (board_pci_idsel)
(void)board_pci_idsel(device, 0);
}
local_irq_restore(flags);
return error;
......@@ -192,7 +187,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
}
static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 * val)
int where, u8 *val)
{
u32 data;
int ret;
......@@ -206,9 +201,8 @@ static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
return ret;
}
static int read_config_word(struct pci_bus *bus, unsigned int devfn,
int where, u16 * val)
int where, u16 *val)
{
u32 data;
int ret;
......@@ -221,7 +215,7 @@ static int read_config_word(struct pci_bus *bus, unsigned int devfn,
}
static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 * val)
int where, u32 *val)
{
int ret;
......@@ -229,9 +223,8 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
return ret;
}
static int
write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
u8 val)
static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 val)
{
u32 data = 0;
......@@ -239,7 +232,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
return -1;
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
......@@ -247,9 +240,8 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
u16 val)
static int write_config_word(struct pci_bus *bus, unsigned int devfn,
int where, u16 val)
{
u32 data = 0;
......@@ -257,18 +249,16 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
return -1;
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
u32 val)
static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 val)
{
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
return -1;
......@@ -277,18 +267,20 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
}
static int config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
int where, int size, u32 *val)
{
switch (size) {
case 1: {
u8 _val;
int rc = read_config_byte(bus, devfn, where, &_val);
*val = _val;
return rc;
}
case 2: {
case 2: {
u16 _val;
int rc = read_config_word(bus, devfn, where, &_val);
*val = _val;
return rc;
}
......@@ -310,7 +302,6 @@ static int config_write(struct pci_bus *bus, unsigned int devfn,
}
}
struct pci_ops au1x_pci_ops = {
config_read,
config_write
......
arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
View file @ 8d97b849
......@@ -126,9 +126,6 @@ static irqreturn_t hwbutton_handler(int irq, void *data)
struct hwbutton_interrupt *hirq = data;
unsigned long cic_ext = *CIC_EXT_CFG_REG;
if (irq != hirq->irq)
return IRQ_NONE;
if (CIC_EXT_IS_ACTIVE_HI(cic_ext, hirq->eirq)) {
/* Interrupt: pin is now HI */
CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
......@@ -164,7 +161,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
*CIC_EXT_CFG_REG = cic_ext;
return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED,
hirq->name, (void *)hirq);
hirq->name, hirq);
}
static int __init msp_hwbutton_setup(void)
......
arch/mips/sgi-ip27/ip27-timer.c
View file @ 8d97b849
......@@ -158,7 +158,7 @@ static void rt_set_mode(enum clock_event_mode mode,
}
}
unsigned int rt_timer_irq;
int rt_timer_irq;
static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
{
......@@ -219,7 +219,7 @@ static void __cpuinit hub_rt_clock_event_init(void)
static void __init hub_rt_clock_event_global_init(void)
{
unsigned int irq;
int irq;
do {
smp_wmb();
......
drivers/i2c/busses/i2c-au1550.c
View file @ 8d97b849
......@@ -335,7 +335,7 @@ i2c_au1550_probe(struct platform_device *pdev)
goto out_mem;
}
priv->psc_base = r->start;
priv->psc_base = CKSEG1ADDR(r->start);
priv->xfer_timeout = 200;
priv->ack_timeout = 200;
......
include/asm-mips/bitops.h
View file @ 8d97b849
......@@ -558,11 +558,13 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
__clear_bit(nr, addr);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static inline int __ilog2(unsigned long x)
static inline unsigned long __fls(unsigned long x)
{
int lz;
......@@ -591,13 +593,6 @@ static inline int __ilog2(unsigned long x)
return 63 - lz;
}
static inline unsigned long __fls(unsigned long x)
{
return __ilog2(x);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* __ffs - find first bit in word.
* @word: The word to search
......@@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x)
*/
static inline unsigned long __ffs(unsigned long word)
{
return __ilog2(word & -word);
return __fls(word & -word);
}
/*
......@@ -654,6 +649,7 @@ static inline int ffs(int word)
#else
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>
......
include/asm-mips/compiler.h
View file @ 8d97b849
......@@ -9,10 +9,10 @@
#define _ASM_COMPILER_H
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
#define GCC_IMM_ASM "n"
#define GCC_IMM_ASM() "n"
#define GCC_REG_ACCUM "$0"
#else
#define GCC_IMM_ASM "rn"
#define GCC_IMM_ASM() "rn"
#define GCC_REG_ACCUM "accum"
#endif
......
include/asm-mips/mach-au1x00/au1000.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-au1x00/au1000_dma.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-au1x00/au1000_gpio.h
View file @ 8d97b849
......@@ -2,12 +2,12 @@
* FILE NAME au1000_gpio.h
*
* BRIEF MODULE DESCRIPTION
* API to Alchemy Au1000 GPIO device.
* API to Alchemy Au1xx0 GPIO device.
*
* Author: MontaVista Software, Inc. <source@mvista.com>
* Steve Longerbeam <stevel@mvista.com>
* Steve Longerbeam
*
* Copyright 2001 MontaVista Software Inc.
* Copyright 2001, 2008 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -37,12 +37,12 @@
#define AU1000GPIO_IOC_MAGIC 'A'
#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
#ifdef __KERNEL__
extern u32 get_au1000_avail_gpio_mask(void);
......
include/asm-mips/mach-au1x00/au1550_spi.h
View file @ 8d97b849
/*
* au1550_spi.h - au1550 psc spi controller driver - platform data struct
* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
*/
#ifndef _AU1550_SPI_H_
......
include/asm-mips/mach-au1x00/au1xxx.h
View file @ 8d97b849
......@@ -23,10 +23,10 @@
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
#include <asm/mach-au1x00/au1000.h>
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)
......
include/asm-mips/mach-au1x00/au1xxx_dbdma.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-au1x00/au1xxx_ide.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-au1x00/au1xxx_psc.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-db1x00/db1200.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-db1x00/db1x00.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-pb1x00/pb1000.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-pb1x00/pb1100.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-pb1x00/pb1200.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-pb1x00/pb1500.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/mach-pb1x00/pb1550.h
View file @ 8d97b849
This diff is collapsed.
include/asm-mips/rtlx.h
View file @ 8d97b849
......@@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep);
extern unsigned int rtlx_write_poll(int index);
enum rtlx_state {
RTLX_STATE_UNUSED,
RTLX_STATE_UNUSED = 0,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
#define RTLX_BUFFER_SIZE 1024
#define RTLX_BUFFER_SIZE 2048
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer
......
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