Commit a9579956 authored by Graham Sider's avatar Graham Sider Committed by Alex Deucher

drm/amdgpu: Update mes_v11_api_def.h

Update MES API to support oversubscription without aggregated doorbell
for usermode queues.

v2: Change oversubscription_no_aggregated_en to is_kfd_process (align
with MES)
Signed-off-by: default avatarGraham Sider <Graham.Sider@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e77a541f
...@@ -677,6 +677,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, ...@@ -677,6 +677,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
queue_input.wptr_addr = qprops->wptr_gpu_addr; queue_input.wptr_addr = qprops->wptr_gpu_addr;
queue_input.queue_type = qprops->queue_type; queue_input.queue_type = qprops->queue_type;
queue_input.paging = qprops->paging; queue_input.paging = qprops->paging;
queue_input.is_kfd_process = 0;
r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
if (r) { if (r) {
......
...@@ -214,6 +214,7 @@ struct mes_add_queue_input { ...@@ -214,6 +214,7 @@ struct mes_add_queue_input {
uint32_t gws_size; uint32_t gws_size;
uint64_t tba_addr; uint64_t tba_addr;
uint64_t tma_addr; uint64_t tma_addr;
uint32_t is_kfd_process;
}; };
struct mes_remove_queue_input { struct mes_remove_queue_input {
......
...@@ -165,6 +165,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, ...@@ -165,6 +165,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
mes_add_queue_pkt.gws_size = input->gws_size; mes_add_queue_pkt.gws_size = input->gws_size;
mes_add_queue_pkt.trap_handler_addr = input->tba_addr; mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
mes_add_queue_pkt.tma_addr = input->tma_addr; mes_add_queue_pkt.tma_addr = input->tma_addr;
mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
mes_add_queue_pkt.api_status.api_completion_fence_addr = mes_add_queue_pkt.api_status.api_completion_fence_addr =
mes->ring.fence_drv.gpu_addr; mes->ring.fence_drv.gpu_addr;
...@@ -312,6 +313,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) ...@@ -312,6 +313,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
mes_set_hw_res_pkt.disable_reset = 1; mes_set_hw_res_pkt.disable_reset = 1;
mes_set_hw_res_pkt.disable_mes_log = 1; mes_set_hw_res_pkt.disable_mes_log = 1;
mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.use_different_vmid_compute = 1;
mes_set_hw_res_pkt.oversubscription_timer = 50;
mes_set_hw_res_pkt.api_status.api_completion_fence_addr = mes_set_hw_res_pkt.api_status.api_completion_fence_addr =
mes->ring.fence_drv.gpu_addr; mes->ring.fence_drv.gpu_addr;
......
...@@ -204,6 +204,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, ...@@ -204,6 +204,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
} else } else
queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
queue_input.is_kfd_process = 1;
queue_input.paging = false; queue_input.paging = false;
queue_input.tba_addr = qpd->tba_addr; queue_input.tba_addr = qpd->tba_addr;
queue_input.tma_addr = qpd->tma_addr; queue_input.tma_addr = qpd->tma_addr;
......
...@@ -226,6 +226,7 @@ union MESAPI_SET_HW_RESOURCES { ...@@ -226,6 +226,7 @@ union MESAPI_SET_HW_RESOURCES {
}; };
uint32_t uint32_t_all; uint32_t uint32_t_all;
}; };
uint32_t oversubscription_timer;
}; };
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
...@@ -265,7 +266,8 @@ union MESAPI__ADD_QUEUE { ...@@ -265,7 +266,8 @@ union MESAPI__ADD_QUEUE {
uint32_t is_gang_suspended : 1; uint32_t is_gang_suspended : 1;
uint32_t is_tmz_queue : 1; uint32_t is_tmz_queue : 1;
uint32_t map_kiq_utility_queue : 1; uint32_t map_kiq_utility_queue : 1;
uint32_t reserved : 23; uint32_t is_kfd_process : 1;
uint32_t reserved : 22;
}; };
struct MES_API_STATUS api_status; struct MES_API_STATUS api_status;
uint64_t tma_addr; uint64_t tma_addr;
......
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