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Commit b3a5af43 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM DT updates from Olof Johansson:
 "Ladies and gentlemen, we proudly announce to you the latest branch of
  ARM device tree contents for the mainline kernel.  Come and see, come
  and see!

  No less than twentythree thousand lines of additions! Just imagine the
  joy you will have of using your mainline kernel on newly supported
  hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
  UniPhier hardware!

  For those of you feeling less adventurous, added hardware support on
  platforms such as TI DM814x and Gumstix Overo platforms might be more
  of your liking.

  We've got something for everyone here!

  Ahem.  Cough.  So, anyway...

  This is the usual large batch of DT updates.  Lots and lots of smaller
  changes, some of the larger ones to point out are:

   - Rockchip veyron (Chromebook) support, as well as several other new boards
   - DRM support on Atmel AT91SAM9N12EK
   - USB additions on some Allwinner platforms
   - Mediatek MT6580 support
   - Freescale i.MX6UL support
   - cleanups for Renesas shmobile platforms
   - lots of added devices on LPC18xx
   - lots of added devices and boards on UniPhier

  There's also some dependent code added here, in particular some
  branches that are primarily merged through the clock tree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
  ARM: tegra: Add gpio-ranges property
  ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
  ARM: tegra: Add Tegra124 PMU support
  ARM: tegra: jetson-tk1: Add GK20A GPU DT node
  ARM: tegra: venice2: Add GK20A GPU DT node
  ARM: tegra: Add IOMMU node to GK20A
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Enable the DFLL on the Jetson TK1
  ARM: tegra: Add the DFLL to Tegra124 device tree
  ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
  ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
  ARM: dts: rockchip: correct regulator power states for suspend
  ARM: dts: rockchip: correct regulator PM properties
  ARM: dts: vexpress: Use assigned-clock-parents for sp810
  pinctrl: tegra: Only set the gpio range if needed
  arm: boot: dts: am4372: add ARM timers and SCU nodes
  ARM: dts: AM4372: Add the am4372-rtc compatible string
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ...
parents 10217810 4c80a003
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Documentation/devicetree/bindings/arm/atmel-at91.txt
View file @ b3a5af43
......@@ -52,6 +52,7 @@ System Timer (ST) required properties:
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members.
- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
......@@ -63,7 +64,7 @@ TC/TCLIB Timer required properties:
Note that you can specify several interrupt cells if the TC
block has one interrupt per channel.
- clock-names: tuple listing input clock names.
Required elements: "t0_clk"
Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks.
......@@ -91,12 +92,14 @@ RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
......@@ -119,6 +122,7 @@ required properties:
- compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
- clocks: phandle to input clock.
optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
......@@ -137,9 +141,10 @@ optional at91sam9x5 properties:
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
};
Special Function Registers (SFR)
......
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt 0 → 100644
View file @ b3a5af43
Raspberry Pi VideoCore firmware driver
Required properties:
- compatible: Should be "raspberrypi,bcm2835-firmware"
- mboxes: Phandle to the firmware device's Mailbox.
(See: ../mailbox/mailbox.txt for more information)
Example:
firmware {
compatible = "raspberrypi,bcm2835-firmware";
mboxes = <&mailbox>;
};
Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
View file @ b3a5af43
......@@ -20,6 +20,8 @@ And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,lschlv2"
"buffalo,lswvl"
"buffalo,lswxl"
"buffalo,lsxhl"
"buffalo,lsxl"
"dlink,dns-320"
......
Documentation/devicetree/bindings/arm/mediatek.txt
View file @ b3a5af43
......@@ -5,6 +5,7 @@ Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
Required root node property:
compatible: Must contain one of
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt8127"
......@@ -14,6 +15,9 @@ compatible: Must contain one of
Supported boards:
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
- bq Aquaris5 smart phone:
Required root node properties:
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
View file @ b3a5af43
......@@ -11,6 +11,7 @@ Required properties:
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in
......
Documentation/devicetree/bindings/arm/omap/omap.txt
View file @ b3a5af43
......@@ -135,6 +135,9 @@ Boards:
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
- AM335X phyBOARD-WEGA: Single Board Computer dev kit
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
......
Documentation/devicetree/bindings/arm/rockchip.txt
View file @ b3a5af43
......@@ -26,3 +26,38 @@ Rockchip platforms device tree bindings
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
- Netxeon R89 board:
Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288";
- Google Jerry (Hisense Chromebook C11 and more):
Required root node properties:
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
- Google Minnie (Asus Chromebook Flip C100P):
Required root node properties:
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
"google,veyron-minnie-rev0", "google,veyron-minnie",
"google,veyron", "rockchip,rk3288";
- Google Pinky (dev-board):
Required root node properties:
- compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
"google,veyron", "rockchip,rk3288";
- Google Speedy (Asus C201 Chromebook):
Required root node properties:
- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
- Rockchip R88 board:
Required root node properties:
- compatible = "rockchip,r88", "rockchip,rk3368";
Documentation/devicetree/bindings/clock/imx6ul-clock.txt 0 → 100644
View file @ b3a5af43
* Clock bindings for Freescale i.MX6 UltraLite
Required properties:
- compatible: Should be "fsl,imx6ul-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
for the full list of i.MX6 UltraLite clock IDs.
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
View file @ b3a5af43
......@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
......
Documentation/devicetree/bindings/memory-controllers/synopsys.txt
View file @ b3a5af43
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
This controller has an optional ECC support in half-bus width (16-bit)
configuration. The ECC controller corrects one bit error and detects
two bit errors.
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area
......
Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt 0 → 100644
View file @ b3a5af43
* Freescale i.MX6 UltraLite IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6ul-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
Reference Manual for detailed CONFIG settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (0 << 6)
PAD_CTL_SPEED_MED (1 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_260ohm (1 << 3)
PAD_CTL_DSE_130ohm (2 << 3)
PAD_CTL_DSE_87ohm (3 << 3)
PAD_CTL_DSE_65ohm (4 << 3)
PAD_CTL_DSE_52ohm (5 << 3)
PAD_CTL_DSE_43ohm (6 << 3)
PAD_CTL_DSE_37ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Documentation/devicetree/bindings/reset/socfpga-reset.txt
View file @ b3a5af43
......@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)
- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1
Example:
......@@ -10,4 +11,5 @@ Example:
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
};
Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
View file @ b3a5af43
......@@ -5,6 +5,7 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: rtc alarm/event interrupt
- clocks: phandle to input clock.
Example:
......@@ -12,4 +13,5 @@ rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x100>;
interrupts = <1 4 7>;
clocks = <&clk32k>;
};
Documentation/devicetree/bindings/rtc/rtc-omap.txt
View file @ b3a5af43
......@@ -8,6 +8,7 @@ Required properties:
Wakeup generation for event Alarm. It can also be
used to control an external PMIC via the
pmic_power_en pin.
- "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
- reg: Address range of rtc register set
- interrupts: rtc timer, alarm interrupts in order
- interrupt-parent: phandle for the interrupt controller
......
Documentation/devicetree/bindings/serial/mtk-uart.txt
View file @ b3a5af43
......@@ -7,8 +7,9 @@ Required properties:
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
MT6577)
MT6580, MT6577)
- reg: The base address of the UART register bank.
......
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
View file @ b3a5af43
......@@ -2,7 +2,11 @@ Mediatek MT6577, MT6572 and MT6589 Timers
---------------------------------------
Required properties:
- compatible: Should be "mediatek,mt6577-timer"
- compatible should contain:
* "mediatek,mt6589-timer" for MT6589 compatible timers
* "mediatek,mt6580-timer" for MT6580 compatible timers
* "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
MT6577)
- reg: Should contain location and length for timers register.
- clocks: Clocks driving the timer hardware. This list should include two
clocks. The order is system clock and as second clock the RTC clock.
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ b3a5af43
......@@ -46,6 +46,7 @@ chipone ChipOne
chipspark ChipSPARK
chrp Common Hardware Reference Platform
chunghwa Chunghwa Picture Tubes Ltd.
ciaa Computadora Industrial Abierta Argentina
cirrus Cirrus Logic, Inc.
cloudengines Cloud Engines, Inc.
cnm Chips&Media, Inc.
......@@ -135,6 +136,7 @@ mitsubishi Mitsubishi Electric Corporation
mosaixtech Mosaix Technologies, Inc.
moxa Moxa
mpl MPL AG
msi Micro-Star International Co. Ltd.
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
mundoreader Mundo Reader S.L.
murata Murata Manufacturing Co., Ltd.
......@@ -143,6 +145,7 @@ national National Semiconductor
neonode Neonode Inc.
netgear NETGEAR
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
netxeon Shenzhen Netxeon Technology CO., LTD
newhaven Newhaven Display International
nintendo Nintendo
nokia Nokia
......
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
View file @ b3a5af43
......@@ -6,6 +6,7 @@ Required properties:
- compatible: must be "atmel,at91sam9260-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle to input clock.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
......@@ -39,6 +40,7 @@ Example:
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
timeout-sec = <15>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
......
arch/arm/boot/dts/Makefile
View file @ b3a5af43
......@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
sama5d31ek.dtb \
sama5d33ek.dtb \
......@@ -176,6 +177,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-km_kirkwood.dtb \
kirkwood-laplug.dtb \
kirkwood-lschlv2.dtb \
kirkwood-lswvl.dtb \
kirkwood-lswxl.dtb \
kirkwood-lsxhl.dtb \
kirkwood-mplcec4.dtb \
kirkwood-mv88f6281gtw-ge.dtb \
......@@ -211,6 +214,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ts419-6281.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_LPC18XX) += \
lpc4337-ciaa.dtb \
lpc4350-hitex-eval.dtb \
lpc4357-ea4357-devkit.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
......@@ -331,6 +335,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
......@@ -390,6 +396,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-cm-t3530.dtb \
omap3-cm-t3730.dtb \
omap3-devkit8000.dtb \
omap3-devkit8000-lcd43.dtb \
omap3-devkit8000-lcd70.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04a3.dtb \
......@@ -409,15 +417,19 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-overo-alto35.dtb \
omap3-overo-chestnut43.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-palo35.dtb \
omap3-overo-palo43.dtb \
omap3-overo-storm-alto35.dtb \
omap3-overo-storm-chestnut43.dtb \
omap3-overo-storm-gallop43.dtb \
omap3-overo-storm-palo35.dtb \
omap3-overo-storm-palo43.dtb \
omap3-overo-storm-summit.dtb \
omap3-overo-storm-tobi.dtb \
omap3-overo-storm-tobiduo.dtb \
omap3-overo-summit.dtb \
omap3-overo-tobi.dtb \
omap3-overo-tobiduo.dtb \
omap3-pandora-600mhz.dtb \
omap3-pandora-1ghz.dtb \
omap3-sbc-t3517.dtb \
......@@ -426,6 +438,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-thunder.dtb \
omap3-zoom3.dtb
dtb-$(CONFIG_SOC_TI81XX) += \
dm8148-evm.dtb \
dm8148-t410.dtb \
dm8168-evm.dtb
dtb-$(CONFIG_SOC_AM33XX) += \
am335x-baltos-ir5221.dtb \
......@@ -438,7 +452,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-nano.dtb \
am335x-pepper.dtb \
am335x-lxm.dtb \
am335x-chiliboard.dtb
am335x-chiliboard.dtb \
am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-duovero-parlor.dtb \
omap4-panda.dtb \
......@@ -464,6 +479,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-lacie-d2-network.dtb \
orion5x-lacie-ethernet-disk-mini-v2.dtb \
orion5x-linkstation-lswtgl.dtb \
orion5x-lswsgl.dtb \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-rd88f5182-nas.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
......@@ -488,7 +505,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb
rk3288-firefly.dtb \
rk3288-r89.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \
......@@ -513,12 +535,15 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_vt.dtb
......@@ -541,7 +566,9 @@ dtb-$(CONFIG_ARCH_STI) += \
stih416-b2020.dtb \
stih416-b2020e.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= stm32f429-disco.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32429i-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
......@@ -551,6 +578,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-itead-iteaduino-plus.dts \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
sun4i-a10-mini-xplus.dtb \
......@@ -598,6 +626,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
......@@ -639,10 +668,11 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-ccu8540.dtb \
ste-ccu9540.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-sld8-ref.dtb
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-sld8-ref.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += \
versatile-ab.dtb \
versatile-pb.dtb
......@@ -702,6 +732,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
dove-dove-db.dtb \
dove-sbc-a510.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt8127-moose.dtb \
......
arch/arm/boot/dts/am335x-boneblack.dts
View file @ b3a5af43
......@@ -68,16 +68,26 @@ nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
&lcdc {
status = "okay";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
};
};
};
/ {
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
&i2c0 {
tda19988 {
compatible = "nxp,tda998x";
reg = <0x70>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
status = "okay";
port {
hdmi_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
};
......
arch/arm/boot/dts/am335x-evm.dts
View file @ b3a5af43
......@@ -136,16 +136,29 @@ display-timings {
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <12000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
compatible = "simple-audio-card";
simple-audio-card,name = "AM335x-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <12000000>;
};
};
};
......@@ -342,7 +355,7 @@ lcd_pins_s0: lcd_pins_s0 {
>;
};
am335x_evm_audio_pins: am335x_evm_audio_pins {
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
......@@ -351,6 +364,15 @@ am335x_evm_audio_pins: am335x_evm_audio_pins {
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
......@@ -460,6 +482,7 @@ tmp275: tmp275@48 {
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
......@@ -575,19 +598,21 @@ partition@9 {
#include "tps65910.dtsi"
&mcasp1 {
pinctrl-names = "default";
pinctrl-0 = <&am335x_evm_audio_pins>;
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&tps {
......
arch/arm/boot/dts/am335x-evmsk.dts
View file @ b3a5af43
......@@ -141,14 +141,26 @@ backlight {
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-EVMSK";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <24000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
compatible = "simple-audio-card";
simple-audio-card,name = "AM335x-EVMSK";
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24000000>;
};
};
panel {
......@@ -396,6 +408,15 @@ mcasp1_pins: mcasp1_pins {
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
......@@ -462,6 +483,7 @@ lis331dlh: lis331dlh@18 {
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
......@@ -661,19 +683,21 @@ wlcore: wlcore@2 {
};
&mcasp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcasp1_pins>;
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&tscadc {
......
arch/arm/boot/dts/am335x-phycore-som.dtsi 0 → 100644
View file @ b3a5af43
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am33xx.dtsi"
/ {
model = "Phytec AM335x phyCORE";
compatible = "phytec,am335x-phycore-som", "ti,am33xx";
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rtc;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
};
};
/* Crypto Module */
&aes {
status = "okay";
};
&sham {
status = "okay";
};
/* Ethernet */
&am33xx_pinmux {
ethernet0_pins: pinmux_ethernet0 {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>;
};
mdio_pins: pinmux_mdio {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
};
&mac {
slaves = <1>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet0_pins>;
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
/* I2C Busses */
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0 {
pinctrl-single,pins = <
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
tps: pmic@2d {
reg = <0x2d>;
};
i2c_eeprom: eeprom@52 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
status = "disabled";
};
i2c_rtc: rtc@68 {
compatible = "rv4162";
reg = <0x68>;
status = "disabled";
};
};
/* NAND memory */
&am33xx_pinmux {
nandflash_pins: pinmux_nandflash {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
nandflash: nand@0,0 {
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <30>;
gpmc,cs-wr-off-ns = <30>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <10>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <30>;
gpmc,wr-cycle-ns = <30>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <50>;
gpmc,cycle2cycle-diffcsen;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <30>;
gpmc,wr-data-mux-bus-ns = <0>;
elm_id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "xload";
reg = <0x0 0x20000>;
};
partition@1 {
label = "xload_backup1";
reg = <0x20000 0x20000>;
};
partition@2 {
label = "xload_backup2";
reg = <0x40000 0x20000>;
};
partition@3 {
label = "xload_backup3";
reg = <0x60000 0x20000>;
};
partition@4 {
label = "barebox";
reg = <0x80000 0x80000>;
};
partition@5 {
label = "bareboxenv";
reg = <0x100000 0x40000>;
};
partition@6 {
label = "oftree";
reg = <0x140000 0x40000>;
};
partition@7 {
label = "kernel";
reg = <0x180000 0x800000>;
};
partition@8 {
label = "root";
reg = <0x980000 0x0>;
};
};
};
/* Power */
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-name = "vdig1_1p8v";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&vbat {
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
/* SPI Busses */
&am33xx_pinmux {
spi0_pins: pinmux_spi0 {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
serial_flash: m25p80@0 {
compatible = "m25p80";
spi-max-frequency = <48000000>;
reg = <0x0>;
m25p,fast-read;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "xload";
reg = <0x0 0x20000>;
};
partition@1 {
label = "barebox";
reg = <0x20000 0x80000>;
};
partition@2 {
label = "bareboxenv";
reg = <0xa0000 0x20000>;
};
partition@3 {
label = "oftree";
reg = <0xc0000 0x20000>;
};
partition@4 {
label = "kernel";
reg = <0xe0000 0x0>;
};
};
};
arch/arm/boot/dts/am335x-wega-rdk.dts 0 → 100644
View file @ b3a5af43
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am335x-phycore-som.dtsi"
#include "am335x-wega.dtsi"
/* SoM */
&i2c_eeprom {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
arch/arm/boot/dts/am335x-wega.dtsi 0 → 100644
View file @ b3a5af43
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
model = "Phytec AM335x phyBOARD-WEGA";
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
};
/* CAN Busses */
&am33xx_pinmux {
dcan1_pins: pinmux_dcan1 {
pinctrl-single,pins = <
0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
>;
};
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};
/* Ethernet */
&am33xx_pinmux {
ethernet1_pins: pinmux_ethernet1 {
pinctrl-single,pins = <
0x40 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
0x48 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
0x4c (PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
0x50 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
0x54 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
>;
};
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};
&mac {
slaves = <2>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
dual_emac = <1>;
};
/* MMC */
&am33xx_pinmux {
mmc1_pins: pinmux_mmc1 {
pinctrl-single,pins = <
0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
>;
};
};
&mmc1 {
vmmc-supply = <&vmmc_reg>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* UARTs */
&am33xx_pinmux {
uart0_pins: pinmux_uart0 {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* USB */
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};
arch/arm/boot/dts/am33xx.dtsi
View file @ b3a5af43
......@@ -103,6 +103,15 @@ l4_wkup: l4_wkup@44c00000 {
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
reg = <0x200000 0x4000>;
......@@ -144,6 +153,14 @@ scm_clocks: clocks {
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
scm_clockdomains: clockdomains {
};
};
......@@ -762,14 +779,6 @@ ocmcram: ocmcram@40300000 {
reg = <0x40300000 0x10000>; /* 64k */
};
wkup_m3: wkup_m3@44d00000 {
compatible = "ti,am3353-wkup-m3";
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
ti,no-reset-on-init;
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
......
arch/arm/boot/dts/am4372.dtsi
View file @ b3a5af43
......@@ -23,6 +23,11 @@ aliases {
i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
};
......@@ -59,6 +64,27 @@ wakeupgen: interrupt-controller@48281000 {
interrupt-parent = <&gic>;
};
scu: scu@48240000 {
compatible = "arm,cortex-a9-scu";
reg = <0x48240000 0x100>;
};
global_timer: timer@48240200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x48240200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&dpll_mpu_m2_ck>;
};
local_timer: timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x48240600 0x100>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&dpll_mpu_m2_ck>;
};
l2-cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
......@@ -83,6 +109,15 @@ l4_wkup: l4_wkup@44c00000 {
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
reg = <0x1f0000 0x11000>;
......@@ -128,6 +163,14 @@ scm_clocks: clocks {
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x44>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
scm_clockdomains: clockdomains {
};
};
......@@ -309,7 +352,8 @@ counter32k: counter@44e86000 {
};
rtc: rtc@44e3e000 {
compatible = "ti,am4372-rtc","ti,da830-rtc";
compatible = "ti,am4372-rtc", "ti,am3352-rtc",
"ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
......@@ -528,8 +572,11 @@ GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
<&dpll_clksel_mac_clk>;
clock-names = "fck", "cpts", "50mclk";
assigned-clocks = <&dpll_clksel_mac_clk>;
assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
......@@ -866,7 +913,12 @@ dwc3_1: omap_dwc3@48380000 {
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
......@@ -890,7 +942,12 @@ dwc3_2: omap_dwc3@483c0000 {
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x10000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
......
arch/arm/boot/dts/am437x-gp-evm.dts
View file @ b3a5af43
......@@ -21,12 +21,11 @@ / {
aliases {
display0 = &lcd0;
serial3 = &uart3;
};
vmmcsd_fixed: fixedregulator-sd {
evm_v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-name = "evm_v3_3d";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
......@@ -83,17 +82,6 @@ lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
/*
* SelLCDorHDMI, LOW to select HDMI. This is not really the
* panel's enable GPIO, but we don't have HDMI driver support nor
* support to switch between two displays, so using this gpio as
* panel's enable should be safe.
*/
enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
......@@ -124,6 +112,32 @@ refclk: oscillator {
clock-frequency = <12000000>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM437x-GP-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-frequency = <12000000>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <12000000>;
};
};
};
&am43xx_pinmux {
......@@ -217,7 +231,6 @@ davinci_mdio_sleep: davinci_mdio_sleep {
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
......@@ -270,7 +283,7 @@ dss_pins: dss_pins {
>;
};
lcd_pins: lcd_pins {
display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPIO 5_8 to select LCD / HDMI */
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
......@@ -409,6 +422,60 @@ uart3_pins: uart3_pins {
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
mcasp1_sleep_pins: mcasp1_sleep_pins {
pinctrl-single,pins = <
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
gpio0_pins: gpio0_pins {
pinctrl-single,pins = <
0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
>;
};
emmc_pins_default: emmc_pins_default {
pinctrl-single,pins = <
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
>;
};
emmc_pins_sleep: emmc_pins_sleep {
pinctrl-single,pins = <
0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
>;
};
};
&i2c0 {
......@@ -455,6 +522,8 @@ dcdc5: regulator-dcdc5 {
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
dcdc6: regulator-dcdc6 {
......@@ -462,6 +531,8 @@ dcdc6: regulator-dcdc6 {
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: regulator-ldo1 {
......@@ -521,6 +592,19 @@ ov2659_1: endpoint {
};
};
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
/* Regulators */
IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
};
};
&epwmss0 {
......@@ -542,7 +626,23 @@ &ecap0 {
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins>;
status = "okay";
p23 {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
/* SelEMMCorNAND selects between eMMC and NAND:
* Low: NAND
* High: eMMC
* When changing this line make sure the newly
* selected device node is enabled and the previously
* selected device node is disabled.
*/
output-low;
line-name = "SelEMMCorNAND";
};
};
&gpio1 {
......@@ -558,19 +658,48 @@ &gpio4 {
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
ti,no-reset-on-init;
p8 {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
* High: LCD display with analog audio via aic3111 codec
*/
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SelLCDorHDMI";
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmcsd_fixed>;
vmmc-supply = <&evm_v3_3d>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
/* eMMC sits on mmc2 */
&mmc2 {
/*
* When enabling eMMC, disable GPMC/NAND and set
* SelEMMCorNAND to output-high
*/
status = "disabled";
vmmc-supply = <&evm_v3_3d>;
bus-width = <8>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_sleep>;
ti,non-removable;
};
&mmc3 {
status = "okay";
/* these are on the crossbar and are outlined in the
......@@ -651,6 +780,10 @@ &elm {
};
&gpmc {
/*
* When enabling GPMC, disable eMMC and set
* SelEMMCorNAND to output-low
*/
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
......@@ -790,3 +923,21 @@ vpfe1_ep: endpoint {
};
};
};
&mcasp1 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_sleep_pins>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
arch/arm/boot/dts/am437x-sk-evm.dts
View file @ b3a5af43
......@@ -32,14 +32,29 @@ backlight {
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM437x-SK-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <24000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
compatible = "simple-audio-card";
simple-audio-card,name = "AM437x-SK-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24000000>;
};
};
matrix_keypad: matrix_keypad@0 {
......@@ -364,6 +379,15 @@ mcasp1_pins: mcasp1_pins {
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
lcd_pins: lcd_pins {
pinctrl-single,pins = <
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
......@@ -480,6 +504,7 @@ edt-ft5306@38 {
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
......@@ -640,8 +665,10 @@ &elm {
};
&mcasp1 {
pinctrl-names = "default";
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
......
arch/arm/boot/dts/am43x-epos-evm.dts
View file @ b3a5af43
......@@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
/ {
model = "TI AM43x EPOS EVM";
......@@ -31,21 +32,18 @@ vmmcsd_fixed: fixedregulator-sd {
enable-active-high;
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
/*
* SelLCDorHDMI, LOW to select HDMI. This is not really the
* panel's enable GPIO, but we don't have HDMI driver support nor
* support to switch between two displays, so using this gpio as
* panel's enable should be safe.
*/
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
......@@ -108,6 +106,38 @@ backlight {
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM43-EPOS-EVM";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker";
simple-audio-card,routing =
"MIC1LP", "Microphone Jack",
"MIC1RP", "Microphone Jack",
"MIC1LP", "MICBIAS",
"MIC1RP", "MICBIAS",
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"Speaker", "SPL",
"Speaker", "SPR";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-frequency = <12000000>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3111>;
system-clock-frequency = <12000000>;
};
};
};
&am43xx_pinmux {
......@@ -278,7 +308,7 @@ dss_pins: dss_pins {
>;
};
lcd_pins: lcd_pins {
display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
......@@ -320,6 +350,24 @@ vpfe1_pins_sleep: vpfe1_pins_sleep {
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
>;
};
mcasp1_sleep_pins: mcasp1_sleep_pins {
pinctrl-single,pins = <
0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
};
&mmc1 {
......@@ -399,6 +447,15 @@ dcdc3: regulator-dcdc3 {
regulator-always-on;
};
dcdc4: regulator-dcdc4 {
compatible = "ti,tps65218-dcdc4";
regulator-name = "vdcdc4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
......@@ -441,6 +498,23 @@ pixcir_ts@5c {
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
};
tlv320aic3111: tlv320aic3111@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3111";
reg = <0x18>;
status = "okay";
ai31xx-micbias-vg = <MICBIAS_2_0V>;
/* Regulators */
HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
SPRVDD-supply = <&vbat>; /* vbat */
SPLVDD-supply = <&vbat>; /* vbat */
AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
};
};
&i2c2 {
......@@ -458,7 +532,21 @@ &gpio1 {
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
p1 {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
* High: LCD display with analog audio via aic3111 codec
*/
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SelLCDorHDMI";
};
};
&gpio3 {
......@@ -686,3 +774,21 @@ vpfe1_ep: endpoint {
};
};
};
&mcasp1 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_sleep_pins>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
arch/arm/boot/dts/am43xx-clocks.dtsi
View file @ b3a5af43
......@@ -486,6 +486,15 @@ cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
reg = <0x4238>;
};
dpll_clksel_mac_clk: dpll_clksel_mac_clk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5_ck>;
reg = <0x4234>;
ti,bit-shift = <2>;
ti,dividers = <2>, <5>;
};
clk_32k_mosc_ck: clk_32k_mosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
......
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file @ b3a5af43
......@@ -580,7 +580,6 @@ &mmc1 {
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
pbias-supply = <&pbias_mmc_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
......
arch/arm/boot/dts/armada-375.dtsi
View file @ b3a5af43
......@@ -176,6 +176,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
};
scu@c000 {
......
arch/arm/boot/dts/armada-388-gp.dts
View file @ b3a5af43
......@@ -81,10 +81,6 @@ i2c@11000 {
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
/*
* The EEPROM located at adresse 54 is needed
* for the boot - DO NOT ERASE IT -
*/
expander0: pca9555@20 {
compatible = "nxp,pca9555";
......@@ -111,6 +107,10 @@ expander1: pca9555@21 {
reg = <0x21>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
serial@12000 {
......@@ -301,9 +301,11 @@ reg_usb2_1_vbus: v5-vbus1 {
reg_sata0: pwr-sata0 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata0: v5-sata0 {
......
arch/arm/boot/dts/armada-38x.dtsi
View file @ b3a5af43
......@@ -143,6 +143,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
};
scu@c000 {
......@@ -450,7 +454,7 @@ usb@58000 {
};
xor@60800 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
......@@ -470,7 +474,7 @@ xor01 {
};
xor@60900 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
......
arch/arm/boot/dts/armada-39x.dtsi
View file @ b3a5af43
......@@ -104,6 +104,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
};
scu@c000 {
......@@ -325,7 +329,7 @@ pmsu@22000 {
};
xor@60800 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
......@@ -345,7 +349,7 @@ xor01 {
};
xor@60900 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
......
arch/arm/boot/dts/at91-sama5d2_xplained.dts 0 → 100644
View file @ b3a5af43
/*
* at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
*
* Copyright (C) 2015 Atmel,
* 2015 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d2.dtsi"
/ {
model = "Atmel SAMA5D2 Xplained";
compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x80000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
usb0: gadget@00300000 {
status = "okay";
};
usb1: ohci@00400000 {
num-ports = <3>;
status = "okay";
};
usb2: ehci@00500000 {
status = "okay";
};
apb {
spi0: spi@f8000000 {
status = "okay";
m25p80@0 {
compatible = "atmel,at25df321a";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
macb0: ethernet@f8008000 {
phy-mode = "rmii";
status = "okay";
};
uart1: serial@f8020000 {
status = "okay";
};
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
status = "okay";
};
uart3: serial@fc008000 {
status = "okay";
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
status = "okay";
at24@54 {
compatible = "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
};
};
};
};
};
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View file @ b3a5af43
......@@ -131,6 +131,15 @@ spi1: spi@fc018000 {
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <
/* external trigger conflicts with USBA_VBUS */
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
atmel,adc-vref = <3300>;
status = "okay";
};
......
arch/arm/boot/dts/at91-sama5d4ek.dts
View file @ b3a5af43
......@@ -100,6 +100,15 @@ lcdheo1@f0000340 {
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <
/* external trigger conflicts with USBA_VBUS */
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
/* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
atmel,adc-vref = <3300>;
/*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
......
arch/arm/boot/dts/at91rm9200.dtsi
View file @ b3a5af43
......@@ -359,6 +359,7 @@ st: timer@fffffd00 {
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
reg = <0xfffffd00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
watchdog {
compatible = "atmel,at91rm9200-wdt";
......@@ -369,6 +370,7 @@ rtc: rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled";
};
......@@ -378,8 +380,8 @@ tcb0: timer@fffa0000 {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffa4000 {
......@@ -388,8 +390,8 @@ tcb1: timer@fffa4000 {
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
i2c0: i2c@fffb8000 {
......
arch/arm/boot/dts/at91sam9260.dtsi
View file @ b3a5af43
......@@ -359,11 +359,13 @@ tc5_clk: tc5_clk {
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
};
pit: timer@fffffd30 {
......@@ -379,8 +381,8 @@ tcb0: timer@fffa0000 {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffdc000 {
......@@ -389,8 +391,8 @@ tcb1: timer@fffdc000 {
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pinctrl@fffff400 {
......@@ -973,6 +975,7 @@ watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
......
arch/arm/boot/dts/at91sam9261.dtsi
View file @ b3a5af43
......@@ -119,8 +119,8 @@ tcb0: timer@fffa0000 {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
usb1: gadget@fffa4000 {
......@@ -820,11 +820,13 @@ lcd_clk: lcd_clk {
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&slow_xtal>;
};
pit: timer@fffffd30 {
......@@ -846,6 +848,7 @@ watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled";
};
......
arch/arm/boot/dts/at91sam9263.dtsi
View file @ b3a5af43
......@@ -377,18 +377,20 @@ tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>;
clock-names = "t0_clk";
clocks = <&tcb_clk>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&slow_xtal>;
};
pinctrl@fffff200 {
......@@ -902,6 +904,7 @@ watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
......
arch/arm/boot/dts/at91sam9g15.dtsi
View file @ b3a5af43
......@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
/ {
model = "Atmel AT91SAM9G15 SoC";
......
arch/arm/boot/dts/at91sam9g15ek.dts
View file @ b3a5af43
......@@ -8,9 +8,34 @@
*/
/dts-v1/;
#include "at91sam9g15.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
};
arch/arm/boot/dts/at91sam9g35.dtsi
View file @ b3a5af43
......@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi"
/ {
......
arch/arm/boot/dts/at91sam9g35ek.dts
View file @ b3a5af43
......@@ -8,6 +8,7 @@
*/
/dts-v1/;
#include "at91sam9g35.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
......@@ -20,6 +21,26 @@ macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
};
arch/arm/boot/dts/at91sam9g45.dtsi
View file @ b3a5af43
......@@ -387,6 +387,7 @@ vdec_clk: vdec_clk {
rstc@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
pit: timer@fffffd30 {
......@@ -400,22 +401,23 @@ pit: timer@fffffd30 {
shdwc@fffffd10 {
compatible = "atmel,at91sam9rl-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
dma: dma-controller@ffffec00 {
......@@ -498,23 +500,31 @@ pinctrl_i2c1: i2c1-0 {
};
isi {
pinctrl_isi: isi-0 {
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
pinctrl_isi_data_0_7: isi-0-data-0-7 {
atmel,pins =
<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
};
pinctrl_isi_data_8_9: isi-0-data-8-9 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
};
pinctrl_isi_data_10_11: isi-0-data-10-11 {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
};
};
......@@ -1067,9 +1077,11 @@ isi@fffb4000 {
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi>;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
pwm0: pwm@fffb8000 {
......@@ -1113,6 +1125,7 @@ watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
......@@ -1247,6 +1260,7 @@ rtc@fffffdb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
......
arch/arm/boot/dts/at91sam9m10g45ek.dts
View file @ b3a5af43
......@@ -63,6 +63,25 @@ macb0: ethernet@fffbc000 {
i2c0: i2c@fff84000 {
status = "okay";
ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
clocks = <&pck1>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clock-rates = <25000000>;
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
i2c1: i2c@fff88000 {
......@@ -101,6 +120,22 @@ slot@0 {
};
pinctrl@fffff200 {
camera_sensor {
pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
atmel,pins =
<AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
......@@ -155,6 +190,18 @@ &pinctrl_adc0_ad6
status = "okay";
};
isi@fffb4000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
status = "okay";
port {
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
};
};
};
pwm0: pwm@fffb8000 {
status = "okay";
......
arch/arm/boot/dts/at91sam9n12.dtsi
View file @ b3a5af43
......@@ -376,6 +376,7 @@ trng_clk: trng_clk {
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
};
pit: timer@fffffe30 {
......@@ -388,6 +389,7 @@ pit: timer@fffffe30 {
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
};
sckc@fffffe50 {
......@@ -431,16 +433,44 @@ tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>;
clock-names = "t0_clk";
clocks = <&tcb_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>;
clock-names = "t0_clk";
clocks = <&tcb_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
hlcdc: hlcdc@f8038000 {
compatible = "atmel,at91sam9n12-hlcdc";
reg = <0xf8038000 0x2000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
dma: dma-controller@ffffec00 {
......@@ -475,6 +505,49 @@ pinctrl_dbgu: dbgu-0 {
};
};
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
......@@ -891,6 +964,7 @@ watchdog@fffffe40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
......@@ -901,6 +975,7 @@ rtc@fffffeb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
......
arch/arm/boot/dts/at91sam9n12ek.dts
View file @ b3a5af43
......@@ -128,6 +128,22 @@ m25p80@0 {
};
};
hlcdc: hlcdc@f8038000 {
status = "okay";
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
usb1: gadget@f803c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
......@@ -161,6 +177,23 @@ usb0: ohci@00500000 {
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&bl_reg>;
status = "okay";
};
bl_reg: backlight_regulator {
compatible = "regulator-fixed";
regulator-name = "backlight-power-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "okay";
};
leds {
compatible = "gpio-leds";
......@@ -194,6 +227,34 @@ enter {
};
};
panel: panel {
compatible = "qd,qd43003c0-40", "simple-panel";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
panel_reg: panel_regulator {
compatible = "regulator-fixed";
regulator-name = "panel-power-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "okay";
};
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
......
arch/arm/boot/dts/at91sam9rl.dtsi
View file @ b3a5af43
......@@ -121,8 +121,8 @@ tcb0: timer@fffa0000 {
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
clock-names = "t0_clk", "t1_clk", "t2_clk";
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
mmc0: mmc@fffa4000 {
......@@ -1018,11 +1018,13 @@ lcd_clk: lcd_clk {
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
};
pit: timer@fffffd30 {
......@@ -1036,6 +1038,7 @@ watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
......@@ -1083,6 +1086,7 @@ rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
......
arch/arm/boot/dts/at91sam9x35.dtsi
View file @ b3a5af43
......@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_can.dtsi"
......
arch/arm/boot/dts/at91sam9x35ek.dts
View file @ b3a5af43
......@@ -8,6 +8,7 @@
*/
/dts-v1/;
#include "at91sam9x35.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
......@@ -20,6 +21,25 @@ macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
};
arch/arm/boot/dts/at91sam9x5.dtsi
View file @ b3a5af43
......@@ -376,11 +376,13 @@ ssc0_clk: ssc0_clk {
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
};
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
};
pit: timer@fffffe30 {
......@@ -418,16 +420,16 @@ tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>;
clock-names = "t0_clk";
clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>;
clock-names = "t0_clk";
clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
dma0: dma-controller@ffffec00 {
......@@ -1173,6 +1175,7 @@ watchdog@fffffe40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
......@@ -1183,6 +1186,7 @@ rtc@fffffeb0 {
compatible = "atmel,at91sam9x5-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
......
arch/arm/boot/dts/at91sam9x5_lcd.dtsi
View file @ b3a5af43
......@@ -13,6 +13,137 @@
/ {
ahb {
apb {
hlcdc: hlcdc@f8038000 {
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
pinctrl@fffff400 {
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb444: lcd-rgb-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
};
pinctrl_lcd_rgb565: lcd-rgb-1 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
};
pinctrl_lcd_rgb666: lcd-rgb-2 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
};
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk {
......@@ -20,6 +151,14 @@ lcdc_clk: lcdc_clk {
reg = <25>;
};
};
systemck {
lcdck: lcdck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
};
};
};
};
......
arch/arm/boot/dts/at91sam9x5dm.dtsi 0 → 100644
View file @ b3a5af43
/*
* at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module
*
* Copyright (C) 2014 Atmel,
* 2014 Free Electrons
*
* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
*
* Licensed under GPLv2 or later.
*/
/ {
ahb {
apb {
i2c0: i2c@f8010000 {
qt1070: keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioA>;
interrupts = <7 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
};
hlcdc: hlcdc@f8038000 {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
board {
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&bl_reg>;
status = "disabled";
};
bl_reg: backlight_regulator {
compatible = "regulator-fixed";
regulator-name = "backlight-power-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "disabled";
};
panel: panel {
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
panel_reg: panel_regulator {
compatible = "regulator-fixed";
regulator-name = "panel-power-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
arch/arm/boot/dts/atlas7-evb.dts
View file @ b3a5af43
......@@ -10,6 +10,9 @@
/include/ "atlas7.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "CSR SiRFatlas7 Evaluation Board";
compatible = "sirf,atlas7-cb", "sirf,atlas7";
......@@ -106,5 +109,20 @@ timing0: timing0 {
};
};
};
gpio_keys {
compatible = "gpio-keys";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rearview_key {
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
debounce_interval = <100>;
};
};
};
};
arch/arm/boot/dts/atlas7.dtsi
View file @ b3a5af43
......@@ -21,6 +21,10 @@ aliases {
serial5 = &uart5;
serial6 = &uart6;
serial9 = &usp2;
spi1 = &spi1;
spi2 = &usp1;
spi3 = &usp2;
spi4 = &usp3;
};
cpus {
#address-cells = <1>;
......@@ -53,6 +57,11 @@ xin {
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 29 4>, <0 82 4>;
};
noc {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -1205,7 +1214,8 @@ cgum {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x18641000 0x18641000 0x3000>,
<0x18620000 0x18620000 0x1000>;
<0x18620000 0x18620000 0x1000>,
<0x18630000 0x18630000 0x10000>;
cgum@18641000 {
compatible = "sirf,nocfw-cgum";
......@@ -1218,6 +1228,15 @@ car: clock-controller@18620000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
pwm: pwm@18630000 {
compatible = "sirf,prima2-pwm";
#pwm-cells = <2>;
reg = <0x18630000 0x10000>;
clocks = <&car 138>, <&car 139>, <&car 237>,
<&car 240>, <&car 140>, <&car 246>;
clock-names = "pwmc", "sigsrc0", "sigsrc1",
"sigsrc2", "sigsrc3", "sigsrc4";
};
};
gnssm {
......@@ -1231,6 +1250,7 @@ gnssm {
<0x18040000 0x18040000 0x1000>,
<0x18050000 0x18050000 0x1000>,
<0x18060000 0x18060000 0x1000>,
<0x180b0000 0x180b0000 0x4000>,
<0x18100000 0x18100000 0x3000>,
<0x18250000 0x18250000 0x10000>,
<0x18200000 0x18200000 0x1000>;
......@@ -1314,6 +1334,18 @@ uart5: uart@18060000 {
dma-names = "rx", "tx";
status = "disabled";
};
gmac: eth@180b0000 {
compatible = "snps, dwc-eth-qos";
reg = <0x180b0000 0x4000>;
interrupts = <0 59 0>, <0 70 0>;
interrupt-names = "macirq", "macpmt";
clocks = <&car 39>, <&car 45>,
<&car 86>, <&car 87>;
clock-names = "gnssm_rgmii", "gnssm_gmac",
"rgmii", "gmac";
local-mac-address = [00 00 00 00 00 00];
phy-mode = "rgmii";
};
dspub@18250000 {
compatible = "dx,cc44p";
reg = <0x18250000 0x10000>;
......@@ -1338,18 +1370,51 @@ gpum {
compatible = "arteris, flexnoc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x13000000 0x13000000 0x3000>;
ranges = <0x13000000 0x13000000 0x3000>,
<0x13010000 0x13010000 0x1400>,
<0x13010800 0x13010800 0x100>,
<0x13011000 0x13011000 0x100>;
gpum@0x13000000 {
compatible = "sirf,nocfw-gpum";
reg = <0x13000000 0x3000>;
};
dmacsdrr: dma-controller@13010800 {
cell-index = <5>;
compatible = "sirf,atlas7-dmac-v2";
reg = <0x13010800 0x100>;
interrupts = <0 8 0>;
clocks = <&car 127>;
#dma-cells = <1>;
#dma-channels = <1>;
};
dmacsdrw: dma-controller@13011000 {
cell-index = <6>;
compatible = "sirf,atlas7-dmac-v2";
reg = <0x13011000 0x100>;
interrupts = <0 9 0>;
clocks = <&car 127>;
#dma-cells = <1>;
#dma-channels = <1>;
};
sdr@0x13010000 {
compatible = "sirf,atlas7-sdr";
reg = <0x13010000 0x1400>;
interrupts = <0 7 0>,
<0 8 0>,
<0 9 0>;
clocks = <&car 127>;
dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
dma-names = "tx", "rx";
};
};
mediam {
compatible = "arteris, flexnoc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x16000000 0x16000000 0x00200000>,
ranges = <0x15000000 0x15000000 0x00600000>,
<0x16000000 0x16000000 0x00200000>,
<0x17000000 0x17000000 0x10000>,
<0x17020000 0x17020000 0x1000>,
<0x17030000 0x17030000 0x1000>,
<0x17040000 0x17040000 0x1000>,
......@@ -1360,6 +1425,13 @@ mediam {
<0x17070200 0x17070200 0x100>,
<0x170A0000 0x170A0000 0x3000>;
multimedia@15000000 {
compatible = "sirf,atlas7-video-codec";
reg = <0x15000000 0x10000>;
interrupts = <0 5 0>;
clocks = <&car 102>;
};
mediam@170A0000 {
compatible = "sirf,nocfw-mediam";
reg = <0x170A0000 0x3000>;
......@@ -1386,6 +1458,8 @@ gpio_0: gpio_mediam@17040000 {
nand@17050000 {
compatible = "sirf,atlas7-nand";
reg = <0x17050000 0x10000>;
pinctrl-names = "default";
pinctrl-0 = <&nd_df_pmx>;
interrupts = <0 41 0>;
clocks = <&car 108>, <&car 112>;
clock-names = "nand_io", "nand_nand";
......@@ -1416,6 +1490,14 @@ sd1: sdhci@16100000 {
bus-width = <8>;
};
jpeg@17000000 {
compatible = "sirf,atlas7-jpeg";
reg = <0x17000000 0x10000>;
interrupts = <0 72 0>,
<0 73 0>;
clocks = <&car 103>;
};
usb0: usb@17060000 {
cell-index = <0>;
compatible = "sirf,atlas7-usb";
......@@ -1826,7 +1908,8 @@ disp-iobg {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x13100000 0x13100000 0x20000>,
<0x10e10000 0x10e10000 0x10000>;
<0x10e10000 0x10e10000 0x10000>,
<0x17010000 0x17010000 0x10000>;
lcd@13100000 {
compatible = "sirf,atlas7-lcdc";
......@@ -1848,6 +1931,12 @@ lvds@10e10000 {
clocks = <&car 54>;
resets = <&car 29>;
};
g2d@17010000 {
compatible = "sirf, atlas7-g2d";
reg = <0x17010000 0x10000>;
interrupts = <0 61 0>;
clocks = <&car 104>;
};
};
......
arch/arm/boot/dts/axp152.dtsi 0 → 100644
View file @ b3a5af43
/*
* Copyright 2015 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&axp152 {
compatible = "x-powers,axp152";
interrupt-controller;
#interrupt-cells = <1>;
};
arch/arm/boot/dts/bcm-cygnus-clock.dtsi
View file @ b3a5af43
......@@ -36,56 +36,89 @@ clocks {
ranges;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
};
apb_clk: apb_clk {
compatible = "fixed-clock";
/* Cygnus ARM PLL */
armpll: armpll {
#clock-cells = <0>;
clock-frequency = <1000000000>;
compatible = "brcm,cygnus-armpll";
clocks = <&osc>;
reg = <0x19000000 0x1000>;
};
periph_clk: periph_clk {
compatible = "fixed-clock";
/* peripheral clock for system timer */
periph_clk: arm_periph_clk {
#clock-cells = <0>;
clock-frequency = <500000000>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <2>;
clock-mult = <1>;
};
sdio_clk: lcpll_ch2 {
compatible = "fixed-clock";
/* APB bus clock */
apb_clk: apb_clk {
#clock-cells = <0>;
clock-frequency = <200000000>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <4>;
clock-mult = <1>;
};
axi81_clk: axi81_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
genpll: genpll {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
clocks = <&osc>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
keypad_clk: keypad_clk {
compatible = "fixed-clock";
/* always 1/2 of the axi21 clock */
axi41_clk: axi41_clk {
#clock-cells = <0>;
clock-frequency = <31806>;
compatible = "fixed-factor-clock";
clocks = <&genpll 1>;
clock-div = <2>;
clock-mult = <1>;
};
adc_clk: adc_clk {
compatible = "fixed-clock";
/* always 1/4 of the axi21 clock */
axi81_clk: axi81_clk {
#clock-cells = <0>;
clock-frequency = <1562500>;
compatible = "fixed-factor-clock";
clocks = <&genpll 1>;
clock-div = <4>;
clock-mult = <1>;
};
pwm_clk: pwm_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
lcpll0: lcpll0 {
#clock-cells = <1>;
compatible = "brcm,cygnus-lcpll0";
reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
"usb_phy", "smart_card", "ch5";
};
lcd_clk: mipipll_ch1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
mipipll: mipipll {
#clock-cells = <1>;
compatible = "brcm,cygnus-mipipll";
reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
clocks = <&osc>;
clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
"ch2_v3d", "ch3_unused", "ch4_unused",
"ch5_unused";
};
asiu_clks: asiu_clks {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc>;
clock-output-names = "keypad", "adc/touch", "pwm";
};
};
arch/arm/boot/dts/bcm2835-rpi.dtsi
View file @ b3a5af43
......@@ -14,6 +14,13 @@ act {
linux,default-trigger = "heartbeat";
};
};
soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware";
mboxes = <&mailbox>;
};
};
};
&gpio {
......
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
View file @ b3a5af43
......@@ -135,3 +135,7 @@ eject {
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
View file @ b3a5af43
......@@ -55,3 +55,7 @@ restart {
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View file @ b3a5af43
......@@ -24,16 +24,6 @@ memory {
reg = <0x00000000 0x08000000>;
};
chipcommonA {
uart0: serial@0300 {
status = "okay";
};
uart1: serial@0400 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
......@@ -92,3 +82,7 @@ restart {
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
View file @ b3a5af43
......@@ -118,3 +118,7 @@ restart {
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
View file @ b3a5af43
......@@ -122,3 +122,7 @@ eject {
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/bcm5301x.dtsi
View file @ b3a5af43
......@@ -78,10 +78,20 @@ L2: cache-controller@2000 {
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
cache-unified;
arm,shared-override;
prefetch-data = <1>;
prefetch-instr = <1>;
cache-level = <2>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts =
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/bcm7445.dtsi
View file @ b3a5af43
......@@ -109,6 +109,20 @@ irq0_intc: interrupt-controller@40a780 {
brcm,int-fwd-mask = <0x70000>;
};
irq0_aon_intc: interrupt-controller@417280 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x417280 0x8>;
interrupt-parent = <&gic>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_SPI 0x46 0x0>,
<GIC_SPI 0x44 0x0>,
<GIC_SPI 0x49 0x0>;
brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
brcm,int-fwd-mask = <0x0>;
brcm,irq-can-wake;
};
hif_intr2_intc: interrupt-controller@3e1000 {
compatible = "brcm,l2-intc";
reg = <0x3e1000 0x30>;
......@@ -119,6 +133,16 @@ hif_intr2_intc: interrupt-controller@3e1000 {
interrupt-names = "hif";
};
aon_pm_l2_intc: interrupt-controller@410640 {
compatible = "brcm,l2-intc";
reg = <0x410640 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 0x40 0x0>;
interrupt-parent = <&gic>;
brcm,irq-can-wake;
};
nand: nand@3e2800 {
status = "disabled";
#address-cells = <1>;
......@@ -167,6 +191,32 @@ sata_phy1: sata-phy@1 {
#phy-cells = <0>;
};
};
upg_gio: gpio@40a700 {
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
reg = <0x40a700 0x80>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&irq0_intc>;
interrupts = <6>;
brcm,gpio-bank-widths = <32 32 32 24>;
};
upg_gio_aon: gpio@4172c0 {
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
reg = <0x4172c0 0x40>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupts-extended = <&irq0_aon_intc 0x6>,
<&aon_pm_l2_intc 0x5>;
wakeup-source;
brcm,gpio-bank-widths = <18 4>;
};
};
smpboot {
......
arch/arm/boot/dts/cros-ec-sbs.dtsi 0 → 100644
View file @ b3a5af43
/*
* Smart battery dts fragment for devices that use cros-ec-sbs
*
* Copyright (c) 2015 Google, Inc
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&i2c_tunnel {
battery: sbs-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
arch/arm/boot/dts/cx92755.dtsi
View file @ b3a5af43
......@@ -88,6 +88,13 @@ rtc@f0000c30 {
interrupts = <25>;
};
watchdog@f0000fc0 {
compatible = "cnxt,cx92755-wdt";
reg = <0xf0000fc0 0x8>;
clocks = <&main_clk>;
timeout-sec = <15>;
};
uc_regs: syscon@f00003a0 {
compatible = "cnxt,cx92755-uc", "syscon";
reg = <0xf00003a0 0x10>;
......
arch/arm/boot/dts/cx92755_equinox.dts
View file @ b3a5af43
......@@ -64,8 +64,7 @@ memory@0 {
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
stdout-path = "serial0:115200n8";
};
};
......
arch/arm/boot/dts/dm8148-evm.dts 0 → 100644
View file @ b3a5af43
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dm814x.dtsi"
/ {
model = "DM8148 EVM";
compatible = "ti,dm8148-evm", "ti,dm8148";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
arch/arm/boot/dts/dm8148-t410.dts 0 → 100644
View file @ b3a5af43
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dm814x.dtsi"
/ {
model = "DM8148 EVM";
compatible = "hp,t410", "ti,dm8148";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
arch/arm/boot/dts/dm814x-clocks.dtsi 0 → 100644
View file @ b3a5af43
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scm_clocks {
tclkin_ck: tclkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
devosc_ck: devosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
auxosc_ck: auxosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
mpu_ck: mpu_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1000000000>;
};
sysclk4_ck: sysclk4_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <222000000>;
};
sysclk6_ck: sysclk6_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
sysclk10_ck: sysclk10_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <250000000>;
};
};
&pllss_clocks {
aud_clkin0_ck: aud_clkin0_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
aud_clkin1_ck: aud_clkin1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
aud_clkin2_ck: aud_clkin2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
timer1_mux_ck: timer1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <3>;
reg = <0x2e0>;
};
timer2_mux_ck: timer2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <6>;
reg = <0x2e0>;
};
};
arch/arm/boot/dts/dm814x.dtsi 0 → 100644
View file @ b3a5af43
/*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>
#include "skeleton.dtsi"
/ {
compatible = "ti,dm814";
interrupt-parent = <&intc>;
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
device_type = "cpu";
reg = <0>;
};
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
};
ocp {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
/*
* See TRM "Table 1-317. L4LS Instance Summary", just deduct
* 0x1000 from the 1-317 addresses to get the device address
*/
l4ls: l4ls@48000000 {
compatible = "ti,dm814-l4ls", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x2000000>;
i2c1: i2c@28000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
reg = <0x28000 0x1000>;
interrupts = <70>;
};
elm: elm@80000 {
compatible = "ti,814-elm";
ti,hwmods = "elm";
reg = <0x80000 0x2000>;
interrupts = <4>;
};
gpio1: gpio@32000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
ti,gpio-always-on;
reg = <0x32000 0x2000>;
interrupts = <96>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@4c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
ti,gpio-always-on;
reg = <0x4c000 0x2000>;
interrupts = <98>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c2: i2c@2a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
reg = <0x2a000 0x1000>;
interrupts = <71>;
};
mcspi1: spi@30000 {
compatible = "ti,omap4-mcspi";
reg = <0x30000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <65>;
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17
&edma 18 &edma 19>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
timer1: timer@2e000 {
compatible = "ti,dm814-timer";
reg = <0x2e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
uart1: uart@20000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
reg = <0x20000 0x2000>;
clock-frequency = <48000000>;
interrupts = <72>;
dmas = <&edma 26 &edma 27>;
dma-names = "tx", "rx";
};
uart2: uart@22000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
reg = <0x22000 0x2000>;
clock-frequency = <48000000>;
interrupts = <73>;
dmas = <&edma 28 &edma 29>;
dma-names = "tx", "rx";
};
uart3: uart@24000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
reg = <0x24000 0x2000>;
clock-frequency = <48000000>;
interrupts = <74>;
dmas = <&edma 30 &edma 31>;
dma-names = "tx", "rx";
};
timer2: timer@40000 {
compatible = "ti,dm814-timer";
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
};
timer3: timer@42000 {
compatible = "ti,dm814-timer";
reg = <0x42000 0x2000>;
interrupts = <69>;
ti,hwmods = "timer3";
};
control: control@160000 {
compatible = "ti,dm814-scm", "simple-bus";
reg = <0x160000 0x16d000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x160000 0x16d000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scm_clockdomains: clockdomains {
};
};
pincntl: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0xc38>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x300ff>;
};
};
prcm: prcm@180000 {
compatible = "ti,dm814-prcm", "simple-bus";
reg = <0x180000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
pllss: pllss@1c5000 {
compatible = "ti,dm814-pllss", "simple-bus";
reg = <0x1c5000 0x2000>;
pllss_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
pllss_clockdomains: clockdomains {
};
};
wdt1: wdt@1c7000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer";
reg = <0x1c7000 0x1000>;
interrupts = <91>;
};
};
intc: interrupt-controller@48200000 {
compatible = "ti,dm814-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x48200000 0x1000>;
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x40>;
interrupts = <12 13 14>;
#dma-cells = <1>;
};
/* See TRM "Table 1-318. L4HS Instance Summary" */
l4hs: l4hs@4a000000 {
compatible = "ti,dm814-l4hs", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x1b4040>;
};
/* REVISIT: Move to live under l4hs once driver is fixed */
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x4a100000 0x800
0x4a100900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a100800 0x100>;
};
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@0x48160650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x48160650 0x4>;
reg-names = "gmii-sel";
};
};
};
};
#include "dm814x-clocks.dtsi"
arch/arm/boot/dts/dm816x.dtsi
View file @ b3a5af43
......@@ -58,7 +58,7 @@ mpu {
* the whole bus hierarchy.
*/
ocp {
compatible = "ti,omap3-l3-smx", "simple-bus";
compatible = "simple-bus";
reg = <0x44000000 0x10000>;
interrupts = <9 10>;
#address-cells = <1>;
......
arch/arm/boot/dts/dove.dtsi
View file @ b3a5af43
This diff is collapsed.
arch/arm/boot/dts/dra7-evm.dts
View file @ b3a5af43
......@@ -19,6 +19,15 @@ memory {
reg = <0x80000000 0x60000000>; /* 1536 MB */
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
mmc2_3v3: fixedregulator-mmc2 {
compatible = "regulator-fixed";
regulator-name = "mmc2_3v3";
......@@ -349,6 +358,7 @@ ldo1_reg: ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
......@@ -462,8 +472,14 @@ &uart3 {
&mmc1 {
status = "okay";
vmmc-supply = <&ldo1_reg>;
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 0>;
};
&mmc2 {
......
arch/arm/boot/dts/dra7.dtsi
View file @ b3a5af43
This diff is collapsed.
arch/arm/boot/dts/dra72-evm.dts
View file @ b3a5af43
......@@ -30,6 +30,15 @@ evm_3v3: fixedregulator-evm_3v3 {
regulator-max-microvolt = <3300000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
......@@ -286,6 +295,7 @@ ldo1_reg: ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
......@@ -343,6 +353,12 @@ pcf_gpio_21: gpio@21 {
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
cpsw_sel_s0 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
......@@ -491,14 +507,15 @@ &mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 0>;
max-frequency = <192000000>;
};
&mmc2 {
......@@ -510,6 +527,7 @@ &mmc2 {
vmmc-supply = <&evm_3v3>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
};
&dra7_pmx_core {
......@@ -571,9 +589,10 @@ &mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <1>;
};
&cpsw_emac1 {
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
......@@ -582,7 +601,6 @@ &davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
active_slave = <1>;
};
&dcan1 {
......
arch/arm/boot/dts/dra74x.dtsi
View file @ b3a5af43
......@@ -65,7 +65,12 @@ omap_dwc3_4: omap_dwc3_4@48940000 {
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
......
arch/arm/boot/dts/emev2-kzm9d.dts
View file @ b3a5af43
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arch/arm/boot/dts/emev2.dtsi
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arch/arm/boot/dts/exynos4412-trats2.dts
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arch/arm/boot/dts/exynos5250-pinctrl.dtsi
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arch/arm/boot/dts/exynos5250.dtsi
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arch/arm/boot/dts/exynos5410-smdk5410.dts
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arch/arm/boot/dts/exynos5420-pinctrl.dtsi
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arch/arm/boot/dts/exynos5420.dtsi
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arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi 0 → 100644
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arch/arm/boot/dts/imx27.dtsi
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arch/arm/boot/dts/imx53-qsb-common.dtsi
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arch/arm/boot/dts/imx53-qsrb.dts
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arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View file @ b3a5af43
......@@ -248,7 +248,6 @@ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
......
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
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