Commit bb021cda authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard

clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 790d929b
...@@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", ...@@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
static const char * const cpux_parents[] = { "osc32k", "osc24M", static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" }; "pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_IS_CRITICAL); 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
......
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