Commit f83ccb93 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "A large part of the arm-soc patches are nowadays DT changes, adding
  support for new SoCs, boards and devices without changing kernel
  source.  The plan is still to move the devicetree files out of the
  kernel tree and reduce the amount of churn going on here, but we keep
  finding reasons to delay doing that.

  Changes are really all over the place, with little sticking out
  particularly.  We have contributions from a total of 116 people in
  this branch.

  Unfortunately, the size of this branch also causes a significant
  number of conflicts at the moment, typically when subsystem
  maintainers merge patches that change the driver at the same time as
  the dts files.  In most cases this could be avoided because the dts
  changes are supposed to be compatible in both ways, and we are asking
  everyone to send ARM dts changes through our tree only"

* tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits)
  dts: stmmac: Document the clocks property in the stmmac base document
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  ARM: STi: stih41x: Add support for the FSM Serial Flash Controller
  ARM: STi: stih416: Add support for the FSM Serial Flash Controller
  ARM: tegra: fix Dalmore pinctrl configuration
  ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm
  ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND
  ARM: dts: Build all keystone dt blobs
  ARM: dts: keystone: Fix control register range for clktsip
  ARM: dts: keystone: Fix domain register range for clkfftc1
  ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot
  ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap
  ARM: dts: bcm21664: Add device tree files.
  ARM: DT: bcm21664: Device tree bindings
  ARM: efm32: properly namespace i2c location property
  ARM: efm32: fix unit address part in USART2 device nodes' names
  ARM: mvebu: Enable NAND controller in Armada 385-DB
  ARM: mvebu: Add support for NAND controller in Armada 38x SoC
  ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs
  ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs
  ...
parents 930b440c 50b4af41
Broadcom BCM21664 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM21664
SoC.
Required root node property:
- compatible: brcm,bcm21664
Example:
/ {
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
[...]
}
Broadcom Kona Family Reset Manager
----------------------------------
The reset manager is used on the Broadcom BCM21664 SoC.
Required properties:
- compatible: brcm,bcm21664-resetmgr
- reg: memory address & range
Example:
brcm,resetmgr@35001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x35001f00 0x24>;
};
...@@ -8,3 +8,13 @@ Required properties: ...@@ -8,3 +8,13 @@ Required properties:
- compatible: All TI specific devices present in Keystone SOC should be in - compatible: All TI specific devices present in Keystone SOC should be in
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices. type UART should use the specified compatible for those devices.
Boards:
- Keystone 2 Hawking/Kepler EVM
compatible = "ti,k2hk-evm","ti,keystone"
- Keystone 2 Lamarr EVM
compatible = "ti,k2l-evm","ti,keystone"
- Keystone 2 Edison EVM
compatible = "ti,k2e-evm","ti,keystone"
OMAP Dynamic Memory Manager (DMM) bindings
The dynamic memory manager (DMM) is a module located immediately in front of the
SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
accesses such as priority generation amongst initiators, configuration of SDRAM
interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
translation for initiators which need contiguous dma bus addresses.
Required properties:
- compatible: Should contain "ti,omap4-dmm" for OMAP4 family
Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family
- reg: Contains DMM register address range (base address and length)
- interrupts: Should contain an interrupt-specifier for DMM_IRQ.
- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm"
Example:
dmm@4e000000 {
compatible = "ti,omap4-dmm";
reg = <0x4e000000 0x800>;
ti,hwmods = "dmm";
};
...@@ -99,6 +99,9 @@ Boards: ...@@ -99,6 +99,9 @@ Boards:
- OMAP4 PandaBoard : Low cost community board - OMAP4 PandaBoard : Low cost community board
compatible = "ti,omap4-panda", "ti,omap4430" compatible = "ti,omap4-panda", "ti,omap4430"
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
compatible = "ti,omap3-evm", "ti,omap3" compatible = "ti,omap3-evm", "ti,omap3"
...@@ -114,5 +117,8 @@ Boards: ...@@ -114,5 +117,8 @@ Boards:
- AM43x EPOS EVM - AM43x EPOS EVM
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
- AM437x GP EVM
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
- DRA7 EVM: Software Developement Board for DRA7XX - DRA7 EVM: Software Developement Board for DRA7XX
compatible = "ti,dra7-evm", "ti,dra7" compatible = "ti,dra7-evm", "ti,dra7"
SAMSUNG Exynos SoC series PMU Registers
Properties:
- compatible : should contain two values. First value must be one from following list:
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x10040000 0x5000>;
};
...@@ -15,259 +15,12 @@ Required Properties: ...@@ -15,259 +15,12 @@ Required Properties:
- #clock-cells: should be 1. - #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is Each clock is assigned an identifier and client nodes can use this identifier
assigned an identifier and client nodes use this identifier to specify the to specify the clock which they consume.
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
[Core Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
xxti 1
xusbxti 2
fin_pll 3
fout_apll 4
fout_mpll 5
fout_epll 6
fout_vpll 7
sclk_apll 8
sclk_mpll 9
sclk_epll 10
sclk_vpll 11
arm_clk 12
aclk200 13
aclk100 14
aclk160 15
aclk133 16
mout_mpll_user_t 17 Exynos4x12
mout_mpll_user_c 18 Exynos4x12
mout_core 19
mout_apll 20
[Clock Gate for Special Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
sclk_fimc0 128
sclk_fimc1 129
sclk_fimc2 130
sclk_fimc3 131
sclk_cam0 132
sclk_cam1 133
sclk_csis0 134
sclk_csis1 135
sclk_hdmi 136
sclk_mixer 137
sclk_dac 138
sclk_pixel 139
sclk_fimd0 140
sclk_mdnie0 141 Exynos4412
sclk_mdnie_pwm0 12 142 Exynos4412
sclk_mipi0 143
sclk_audio0 144
sclk_mmc0 145
sclk_mmc1 146
sclk_mmc2 147
sclk_mmc3 148
sclk_mmc4 149
sclk_sata 150 Exynos4210
sclk_uart0 151
sclk_uart1 152
sclk_uart2 153
sclk_uart3 154
sclk_uart4 155
sclk_audio1 156
sclk_audio2 157
sclk_spdif 158
sclk_spi0 159
sclk_spi1 160
sclk_spi2 161
sclk_slimbus 162
sclk_fimd1 163 Exynos4210
sclk_mipi1 164 Exynos4210
sclk_pcm1 165
sclk_pcm2 166
sclk_i2s1 167
sclk_i2s2 168
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
sclk_g3d 172
sclk_pwm_isp 173 Exynos4x12
sclk_spi0_isp 174 Exynos4x12
sclk_spi1_isp 175 Exynos4x12
sclk_uart_isp 176 Exynos4x12
sclk_fimg2d 177
[Peripheral Clock Gates]
Clock ID SoC (if specific)
-----------------------------------------------
fimc0 256
fimc1 257
fimc2 258
fimc3 259
csis0 260
csis1 261
jpeg 262
smmu_fimc0 263
smmu_fimc1 264
smmu_fimc2 265
smmu_fimc3 266
smmu_jpeg 267
vp 268
mixer 269
tvenc 270 Exynos4210
hdmi 271
smmu_tv 272
mfc 273
smmu_mfcl 274
smmu_mfcr 275
g3d 276
g2d 277
rotator 278 Exynos4210
mdma 279 Exynos4210
smmu_g2d 280 Exynos4210
smmu_rotator 281 Exynos4210
smmu_mdma 282 Exynos4210
fimd0 283
mie0 284
mdnie0 285 Exynos4412
dsim0 286
smmu_fimd0 287
fimd1 288 Exynos4210
mie1 289 Exynos4210
dsim1 290 Exynos4210
smmu_fimd1 291 Exynos4210
pdma0 292
pdma1 293
pcie_phy 294
sata_phy 295 Exynos4210
tsi 296
sdmmc0 297
sdmmc1 298
sdmmc2 299
sdmmc3 300
sdmmc4 301
sata 302 Exynos4210
sromc 303
usb_host 304
usb_device 305
pcie 306
onenand 307
nfcon 308
smmu_pcie 309
gps 310
smmu_gps 311
uart0 312
uart1 313
uart2 314
uart3 315
uart4 316
i2c0 317
i2c1 318
i2c2 319
i2c3 320
i2c4 321
i2c5 322
i2c6 323
i2c7 324
i2c_hdmi 325
tsadc 326
spi0 327
spi1 328
spi2 329
i2s1 330
i2s2 331
pcm0 332
i2s0 333
pcm1 334
pcm2 335
pwm 336
slimbus 337
spdif 338
ac97 339
modemif 340
chipid 341
sysreg 342
hdmi_cec 343
mct 344
wdt 345
rtc 346
keyif 347
audss 348
mipi_hsi 349 Exynos4210
mdma2 350 Exynos4210
pixelasyncm0 351
pixelasyncm1 352
fimc_lite0 353 Exynos4x12
fimc_lite1 354 Exynos4x12
ppmuispx 355 Exynos4x12
ppmuispmx 356 Exynos4x12
fimc_isp 357 Exynos4x12
fimc_drc 358 Exynos4x12
fimc_fd 359 Exynos4x12
mcuisp 360 Exynos4x12
gicisp 361 Exynos4x12
smmu_isp 362 Exynos4x12
smmu_drc 363 Exynos4x12
smmu_fd 364 Exynos4x12
smmu_lite0 365 Exynos4x12
smmu_lite1 366 Exynos4x12
mcuctl_isp 367 Exynos4x12
mpwm_isp 368 Exynos4x12
i2c0_isp 369 Exynos4x12
i2c1_isp 370 Exynos4x12
mtcadc_isp 371 Exynos4x12
pwm_isp 372 Exynos4x12
wdt_isp 373 Exynos4x12
uart_isp 374 Exynos4x12
asyncaxim 375 Exynos4x12
smmu_ispcx 376 Exynos4x12
spi0_isp 377 Exynos4x12
spi1_isp 378 Exynos4x12
pwm_isp_sclk 379 Exynos4x12
spi0_isp_sclk 380 Exynos4x12
spi1_isp_sclk 381 Exynos4x12
uart_isp_sclk 382 Exynos4x12
tmu_apbif 383
[Mux Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
mout_fimc0 384
mout_fimc1 385
mout_fimc2 386
mout_fimc3 387
mout_cam0 388
mout_cam1 389
mout_csis0 390
mout_csis1 391
mout_g3d0 392
mout_g3d1 393
mout_g3d 394
aclk400_mcuisp 395 Exynos4x12
[Div Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
div_isp0 450 Exynos4x12
div_isp1 451 Exynos4x12
div_mcuisp0 452 Exynos4x12
div_mcuisp1 453 Exynos4x12
div_aclk200 454 Exynos4x12
div_aclk400_mcuisp 455 Exynos4x12
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos4.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below. Example 1: An example of a clock controller node is listed below.
...@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock ...@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>; reg = <0x13820000 0x100>;
interrupts = <0 54 0>; interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0"; clock-names = "uart", "clk_uart_baud0";
}; };
...@@ -13,163 +13,12 @@ Required Properties: ...@@ -13,163 +13,12 @@ Required Properties:
- #clock-cells: should be 1. - #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is Each clock is assigned an identifier and client nodes can use this identifier
assigned an identifier and client nodes use this identifier to specify the to specify the clock which they consume.
clock which they consume.
[Core Clocks]
Clock ID
----------------------------
fin_pll 1
[Clock Gate for Special Clocks]
Clock ID
----------------------------
sclk_cam_bayer 128
sclk_cam0 129
sclk_cam1 130
sclk_gscl_wa 131
sclk_gscl_wb 132
sclk_fimd1 133
sclk_mipi1 134
sclk_dp 135
sclk_hdmi 136
sclk_pixel 137
sclk_audio0 138
sclk_mmc0 139
sclk_mmc1 140
sclk_mmc2 141
sclk_mmc3 142
sclk_sata 143
sclk_usb3 144
sclk_jpeg 145
sclk_uart0 146
sclk_uart1 147
sclk_uart2 148
sclk_uart3 149
sclk_pwm 150
sclk_audio1 151
sclk_audio2 152
sclk_spdif 153
sclk_spi0 154
sclk_spi1 155
sclk_spi2 156
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
div_pcm0 160
[Peripheral Clock Gates]
Clock ID
----------------------------
gscl0 256
gscl1 257
gscl2 258
gscl3 259
gscl_wa 260
gscl_wb 261
smmu_gscl0 262
smmu_gscl1 263
smmu_gscl2 264
smmu_gscl3 265
mfc 266
smmu_mfcl 267
smmu_mfcr 268
rotator 269
jpeg 270
mdma1 271
smmu_rotator 272
smmu_jpeg 273
smmu_mdma1 274
pdma0 275
pdma1 276
sata 277
usbotg 278
mipi_hsi 279
sdmmc0 280
sdmmc1 281
sdmmc2 282
sdmmc3 283
sromc 284
usb2 285
usb3 286
sata_phyctrl 287
sata_phyi2c 288
uart0 289
uart1 290
uart2 291
uart3 292
uart4 293
i2c0 294
i2c1 295
i2c2 296
i2c3 297
i2c4 298
i2c5 299
i2c6 300
i2c7 301
i2c_hdmi 302
adc 303
spi0 304
spi1 305
spi2 306
i2s1 307
i2s2 308
pcm1 309
pcm2 310
pwm 311
spdif 312
ac97 313
hsi2c0 314
hsi2c1 315
hs12c2 316
hs12c3 317
chipid 318
sysreg 319
pmu 320
cmu_top 321
cmu_core 322
cmu_mem 323
tzpc0 324
tzpc1 325
tzpc2 326
tzpc3 327
tzpc4 328
tzpc5 329
tzpc6 330
tzpc7 331
tzpc8 332
tzpc9 333
hdmi_cec 334
mct 335
wdt 336
rtc 337
tmu 338
fimd1 339
mie1 340
dsim0 341
dp 342
mixer 343
hdmi 344
g2d 345
mdma0 346
smmu_mdma0 347
[Clock Muxes]
Clock ID
----------------------------
mout_hdmi 1024
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5250.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below. Example 1: An example of a clock controller node is listed below.
...@@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock ...@@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>; reg = <0x13820000 0x100>;
interrupts = <0 54 0>; interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0"; clock-names = "uart", "clk_uart_baud0";
}; };
...@@ -13,184 +13,12 @@ Required Properties: ...@@ -13,184 +13,12 @@ Required Properties:
- #clock-cells: should be 1. - #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is Each clock is assigned an identifier and client nodes can use this identifier
assigned an identifier and client nodes use this identifier to specify the to specify the clock which they consume.
clock which they consume.
All available clocks are defined as preprocessor macros in
[Core Clocks] dt-bindings/clock/exynos5420.h header and can be used in device
tree sources.
Clock ID
----------------------------
fin_pll 1
[Clock Gate for Special Clocks]
Clock ID
----------------------------
sclk_uart0 128
sclk_uart1 129
sclk_uart2 130
sclk_uart3 131
sclk_mmc0 132
sclk_mmc1 133
sclk_mmc2 134
sclk_spi0 135
sclk_spi1 136
sclk_spi2 137
sclk_i2s1 138
sclk_i2s2 139
sclk_pcm1 140
sclk_pcm2 141
sclk_spdif 142
sclk_hdmi 143
sclk_pixel 144
sclk_dp1 145
sclk_mipi1 146
sclk_fimd1 147
sclk_maudio0 148
sclk_maupcm0 149
sclk_usbd300 150
sclk_usbd301 151
sclk_usbphy300 152
sclk_usbphy301 153
sclk_unipro 154
sclk_pwm 155
sclk_gscl_wa 156
sclk_gscl_wb 157
sclk_hdmiphy 158
[Peripheral Clock Gates]
Clock ID
----------------------------
aclk66_peric 256
uart0 257
uart1 258
uart2 259
uart3 260
i2c0 261
i2c1 262
i2c2 263
i2c3 264
i2c4 265
i2c5 266
i2c6 267
i2c7 268
i2c_hdmi 269
tsadc 270
spi0 271
spi1 272
spi2 273
keyif 274
i2s1 275
i2s2 276
pcm1 277
pcm2 278
pwm 279
spdif 280
i2c8 281
i2c9 282
i2c10 283
aclk66_psgen 300
chipid 301
sysreg 302
tzpc0 303
tzpc1 304
tzpc2 305
tzpc3 306
tzpc4 307
tzpc5 308
tzpc6 309
tzpc7 310
tzpc8 311
tzpc9 312
hdmi_cec 313
seckey 314
mct 315
wdt 316
rtc 317
tmu 318
tmu_gpu 319
pclk66_gpio 330
aclk200_fsys2 350
mmc0 351
mmc1 352
mmc2 353
sromc 354
ufs 355
aclk200_fsys 360
tsi 361
pdma0 362
pdma1 363
rtic 364
usbh20 365
usbd300 366
usbd301 377
aclk400_mscl 380
mscl0 381
mscl1 382
mscl2 383
smmu_mscl0 384
smmu_mscl1 385
smmu_mscl2 386
aclk333 400
mfc 401
smmu_mfcl 402
smmu_mfcr 403
aclk200_disp1 410
dsim1 411
dp1 412
hdmi 413
aclk300_disp1 420
fimd1 421
smmu_fimd1 422
aclk166 430
mixer 431
aclk266 440
rotator 441
mdma1 442
smmu_rotator 443
smmu_mdma1 444
aclk300_jpeg 450
jpeg 451
jpeg2 452
smmu_jpeg 453
aclk300_gscl 460
smmu_gscl0 461
smmu_gscl1 462
gscl_wa 463
gscl_wb 464
gscl0 465
gscl1 466
clk_3aa 467
aclk266_g2d 470
sss 471
slim_sss 472
mdma0 473
aclk333_g2d 480
g2d 481
aclk333_432_gscl 490
smmu_3aa 491
smmu_fimcl0 492
smmu_fimcl1 493
smmu_fimcl3 494
fimc_lite3 495
aclk_g3d 500
g3d 501
smmu_mixer 502
Mux ID
----------------------------
mout_hdmi 640
Divider ID
----------------------------
dout_pixel 768
Example 1: An example of a clock controller node is listed below. Example 1: An example of a clock controller node is listed below.
...@@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock ...@@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>; reg = <0x13820000 0x100>;
interrupts = <0 54 0>; interrupts = <0 54 0>;
clocks = <&clock 259>, <&clock 130>; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0"; clock-names = "uart", "clk_uart_baud0";
}; };
...@@ -12,45 +12,12 @@ Required Properties: ...@@ -12,45 +12,12 @@ Required Properties:
- #clock-cells: should be 1. - #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is Each clock is assigned an identifier and client nodes can use this identifier
assigned an identifier and client nodes use this identifier to specify the to specify the clock which they consume.
clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5440.h header and can be used in device
[Core Clocks] tree sources.
Clock ID
----------------------------
xtal 1
arm_clk 2
[Peripheral Clock Gates]
Clock ID
----------------------------
spi_baud 16
pb0_250 17
pr0_250 18
pr1_250 19
b_250 20
b_125 21
b_200 22
sata 23
usb 24
gmac0 25
cs250 26
pb0_250_o 27
pr0_250_o 28
pr1_250_o 29
b_250_o 30
b_125_o 31
b_200_o 32
sata_o 33
usb_o 34
gmac0_o 35
cs250_o 36
Example: An example of a clock controller node is listed below. Example: An example of a clock controller node is listed below.
......
...@@ -59,6 +59,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch ...@@ -59,6 +59,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
ramtron,24c64 i2c serial eeprom (24cxx) ramtron,24c64 i2c serial eeprom (24cxx)
ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
sii,s35390a 2-wire CMOS real-time clock
st-micro,24c256 i2c serial eeprom (24cxx) st-micro,24c256 i2c serial eeprom (24cxx)
stm,m41t00 Serial Access TIMEKEEPER stm,m41t00 Serial Access TIMEKEEPER
stm,m41t62 Serial real-time clock (RTC) with alarm stm,m41t62 Serial real-time clock (RTC) with alarm
......
...@@ -8,32 +8,32 @@ Required properties: ...@@ -8,32 +8,32 @@ Required properties:
- clock-names: tuple listing input clock names. - clock-names: tuple listing input clock names.
Required elements: "adc_clk", "adc_op_clk". Required elements: "adc_clk", "adc_op_clk".
- clocks: phandles to input clocks. - clocks: phandles to input clocks.
- atmel,adc-channels-used: Bitmask of the channels muxed and enable for this - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
device device
- atmel,adc-startup-time: Startup Time of the ADC in microseconds as - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
defined in the datasheet defined in the datasheet
- atmel,adc-vref: Reference voltage in millivolts for the conversions - atmel,adc-vref: Reference voltage in millivolts for the conversions
- atmel,adc-res: List of resolution in bits supported by the ADC. List size - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
must be two at least. must be two at least.
- atmel,adc-res-names: Contains one identifier string for each resolution - atmel,adc-res-names: Contains one identifier string for each resolution
in atmel,adc-res property. "lowres" and "highres" in atmel,adc-res property. "lowres" and "highres"
identifiers are required. identifiers are required.
Optional properties: Optional properties:
- atmel,adc-use-external: Boolean to enable of external triggers - atmel,adc-use-external-triggers: Boolean to enable the external triggers
- atmel,adc-use-res: String corresponding to an identifier from - atmel,adc-use-res: String corresponding to an identifier from
atmel,adc-res-names property. If not specified, the highest atmel,adc-res-names property. If not specified, the highest
resolution will be used. resolution will be used.
- atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion
- atmel,adc-sample-hold-time: Sample and Hold Time in microseconds - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds
- atmel,adc-ts-wires: Number of touch screen wires. Should be 4 or 5. If this - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this
value is set, then adc driver will enable touch screen value is set, then the adc driver will enable touchscreen
support. support.
NOTE: when adc touch screen enabled, the adc hardware trigger will be NOTE: when adc touchscreen is enabled, the adc hardware trigger will be
disabled. Since touch screen will occupied the trigger register. disabled. Since touchscreen will occupy the trigger register.
- atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It
make touch detect more precision. makes touch detection more precise.
Optional trigger Nodes: Optional trigger Nodes:
- Required properties: - Required properties:
* trigger-name: Name of the trigger exposed to the user * trigger-name: Name of the trigger exposed to the user
...@@ -44,42 +44,43 @@ Optional trigger Nodes: ...@@ -44,42 +44,43 @@ Optional trigger Nodes:
Examples: Examples:
adc0: adc@fffb0000 { adc0: adc@fffb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc"; compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>; reg = <0xfffb0000 0x100>;
interrupts = <20 4>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>, <&adc_op_clk>; clocks = <&adc_clk>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk"; clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channel-base = <0x30>;
atmel,adc-channels-used = <0xff>; atmel,adc-channels-used = <0xff>;
atmel,adc-drdy-mask = <0x10000>;
atmel,adc-num-channels = <8>;
atmel,adc-startup-time = <40>; atmel,adc-startup-time = <40>;
atmel,adc-status-register = <0x1c>; atmel,adc-use-external-triggers;
atmel,adc-trigger-register = <0x08>;
atmel,adc-use-external;
atmel,adc-vref = <3300>; atmel,adc-vref = <3300>;
atmel,adc-res = <8 10>; atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres"; atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "lowres"; atmel,adc-use-res = "lowres";
trigger@0 { trigger@0 {
reg = <0>;
trigger-name = "external-rising"; trigger-name = "external-rising";
trigger-value = <0x1>; trigger-value = <0x1>;
trigger-external; trigger-external;
}; };
trigger@1 { trigger@1 {
reg = <1>;
trigger-name = "external-falling"; trigger-name = "external-falling";
trigger-value = <0x2>; trigger-value = <0x2>;
trigger-external; trigger-external;
}; };
trigger@2 { trigger@2 {
reg = <2>;
trigger-name = "external-any"; trigger-name = "external-any";
trigger-value = <0x3>; trigger-value = <0x3>;
trigger-external; trigger-external;
}; };
trigger@3 { trigger@3 {
reg = <3>;
trigger-name = "continuous"; trigger-name = "continuous";
trigger-value = <0x6>; trigger-value = <0x6>;
}; };
......
Altera SOCFPGA SoC DWMAC controller
This is a variant of the dwmac/stmmac driver an inherits all descriptions
present in Documentation/devicetree/bindings/net/stmmac.txt.
The device node has additional properties:
Required properties:
- compatible : Should contain "altr,socfpga-stmmac" along with
"snps,dwmac" and any applicable more detailed
designware version numbers documented in stmmac.txt
- altr,sysmgr-syscon : Should be the phandle to the system manager node that
encompasses the glue register, the register offset, and the register shift.
Example:
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
status = "disabled";
reg = <0xff700000 0x2000>;
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac_0_clk>;
clocks-names = "stmmaceth";
};
...@@ -31,6 +31,10 @@ Optional properties: ...@@ -31,6 +31,10 @@ Optional properties:
- reset-names: Should contain the reset signal name "stmmaceth", if a - reset-names: Should contain the reset signal name "stmmaceth", if a
reset phandle is given reset phandle is given
- max-frame-size: See ethernet.txt file in the same directory - max-frame-size: See ethernet.txt file in the same directory
- clocks: If present, the first clock should be the GMAC main clock,
further clocks may be specified in derived bindings.
- clocks-names: One name for each entry in the clocks property, the
first one should be "stmmaceth".
Examples: Examples:
...@@ -43,4 +47,6 @@ Examples: ...@@ -43,4 +47,6 @@ Examples:
mac-address = [000000000000]; /* Filled in by U-Boot */ mac-address = [000000000000]; /* Filled in by U-Boot */
max-frame-size = <3800>; max-frame-size = <3800>;
phy-mode = "gmii"; phy-mode = "gmii";
clocks = <&clock>;
clock-names = "stmmaceth">;
}; };
...@@ -42,6 +42,10 @@ Required properties: ...@@ -42,6 +42,10 @@ Required properties:
- 0xc2000000: prefetchable memory region - 0xc2000000: prefetchable memory region
Please refer to the standard PCI bus binding document for a more detailed Please refer to the standard PCI bus binding document for a more detailed
explanation. explanation.
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
Please refer to the standard PCI bus binding document for a more detailed
explanation.
- clocks: Must contain an entry for each entry in clock-names. - clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries: - clock-names: Must include the following entries:
...@@ -86,6 +90,10 @@ SoC DTSI: ...@@ -86,6 +90,10 @@ SoC DTSI:
0 99 0x04>; /* MSI interrupt */ 0 99 0x04>; /* MSI interrupt */
interrupt-names = "intr", "msi"; interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>; bus-range = <0x00 0xff>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
......
STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
=============================================================================
This binding describes a reset controller device that is used to enable and
disable on-chip peripheral controllers such as USB and SATA, using
"powerdown" control bits found in the STi family SoC system configuration
registers. These have been grouped together into a single reset controller
device for convenience.
The actual action taken when powerdown is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
Please refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "st,<chip>-powerdown"
ex: "st,stih415-powerdown", "st,stih416-powerdown"
- #reset-cells: 1, see below
example:
powerdown: powerdown-controller {
#reset-cells = <1>;
compatible = "st,stih415-powerdown";
};
Specifying powerdown control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the powerdown device node and an
index specifying which channel to use, as described in reset.txt
example:
usb1: usb@fe200000 {
resets = <&powerdown STIH41X_USB1_POWERDOWN>;
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset-controller/stih415-resets.h
include/dt-bindings/reset-controller/stih416-resets.h
STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
=============================================================================
This binding describes a reset controller device that is used to enable and
disable on-chip peripheral controllers such as USB and SATA, using
"softreset" control bits found in the STi family SoC system configuration
registers.
The actual action taken when softreset is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
Please refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "st,<chip>-softreset" example:
"st,stih415-softreset" or "st,stih416-softreset";
- #reset-cells: 1, see below
example:
softreset: softreset-controller {
#reset-cells = <1>;
compatible = "st,stih415-softreset";
};
Specifying softreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the softreset device node and an
index specifying which channel to use, as described in reset.txt
example:
ethernet0{
resets = <&softreset STIH415_ETH0_SOFTRESET>;
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset-controller/stih415-resets.h
include/dt-bindings/reset-controller/stih416-resets.h
...@@ -57,8 +57,8 @@ Required properties: ...@@ -57,8 +57,8 @@ Required properties:
- ep childnode: To specify the number of endpoints and their properties. - ep childnode: To specify the number of endpoints and their properties.
Optional properties: Optional properties:
- atmel,vbus-gpio: If present, specifies a gpio that needs to be - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
activated for the bus to be powered. vbus is present (USB is connected).
Required child node properties: Required child node properties:
- name: Name of the endpoint. - name: Name of the endpoint.
......
...@@ -21,7 +21,7 @@ Documentation/devicetree/bindings/mfd/omap-usb-host.txt ...@@ -21,7 +21,7 @@ Documentation/devicetree/bindings/mfd/omap-usb-host.txt
Example for OMAP4: Example for OMAP4:
usbhsehci: ehci@4a064c00 { usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap", "usb-ehci"; compatible = "ti,ehci-omap";
reg = <0x4a064c00 0x400>; reg = <0x4a064c00 0x400>;
interrupts = <0 77 0x4>; interrupts = <0 77 0x4>;
}; };
......
...@@ -9,7 +9,7 @@ Required properties: ...@@ -9,7 +9,7 @@ Required properties:
Example for OMAP4: Example for OMAP4:
usbhsohci: ohci@4a064800 { usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3", "usb-ohci"; compatible = "ti,ohci-omap3";
reg = <0x4a064800 0x400>; reg = <0x4a064800 0x400>;
interrupts = <0 76 0x4>; interrupts = <0 76 0x4>;
}; };
...@@ -35,11 +35,13 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor) ...@@ -35,11 +35,13 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc. davicom DAVICOM Semiconductor, Inc.
dlink D-Link Systems, Inc. dlink D-Link Systems, Inc.
denx Denx Software Engineering denx Denx Software Engineering
dmo Data Modul AG
edt Emerging Display Technologies edt Emerging Display Technologies
emmicro EM Microelectronic emmicro EM Microelectronic
epfl Ecole Polytechnique Fédérale de Lausanne epfl Ecole Polytechnique Fédérale de Lausanne
epson Seiko Epson Corp. epson Seiko Epson Corp.
est ESTeem Wireless Modems est ESTeem Wireless Modems
eukrea Eukréa Electromatique
fsl Freescale Semiconductor fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
...@@ -83,10 +85,12 @@ picochip Picochip Ltd ...@@ -83,10 +85,12 @@ picochip Picochip Ltd
powervr PowerVR (deprecated, use img) powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc. qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc qcom Qualcomm Technologies, Inc
qnap QNAP Systems, Inc.
ralink Mediatek/Ralink Technology Corp. ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International ramtron Ramtron International
realtek Realtek Semiconductor Corp. realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation renesas Renesas Electronics Corporation
ricoh Ricoh Co. Ltd.
rockchip Fuzhou Rockchip Electronics Co., Ltd rockchip Fuzhou Rockchip Electronics Co., Ltd
samsung Samsung Semiconductor samsung Samsung Semiconductor
sbs Smart Battery System sbs Smart Battery System
...@@ -94,6 +98,7 @@ schindler Schindler ...@@ -94,6 +98,7 @@ schindler Schindler
sil Silicon Image sil Silicon Image
silabs Silicon Laboratories silabs Silicon Laboratories
simtek simtek
sii Seiko Instruments, Inc.
sirf SiRF Technology, Inc. sirf SiRF Technology, Inc.
smsc Standard Microsystems Corporation smsc Standard Microsystems Corporation
snps Synopsys, Inc. snps Synopsys, Inc.
...@@ -101,12 +106,14 @@ spansion Spansion Inc. ...@@ -101,12 +106,14 @@ spansion Spansion Inc.
st STMicroelectronics st STMicroelectronics
ste ST-Ericsson ste ST-Ericsson
stericsson ST-Ericsson stericsson ST-Ericsson
synology Synology, Inc.
ti Texas Instruments ti Texas Instruments
tlm Trusted Logic Mobility tlm Trusted Logic Mobility
toshiba Toshiba Corporation toshiba Toshiba Corporation
toumaz Toumaz toumaz Toumaz
v3 V3 Semiconductor v3 V3 Semiconductor
via VIA Technologies, Inc. via VIA Technologies, Inc.
voipac Voipac Technologies s.r.o.
winbond Winbond Electronics corp. winbond Winbond Electronics corp.
wlf Wolfson Microelectronics wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc. wm Wondermedia Technologies, Inc.
......
...@@ -51,19 +51,15 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb ...@@ -51,19 +51,15 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
bcm28155-ap.dtb bcm21664-garnet.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \ berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb berlin2cd-google-chromecast.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb da850-evm.dtb
dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \ exynos4210-smdkv310.dtb \
...@@ -86,7 +82,11 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ...@@ -86,7 +82,11 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb integratorcp.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
k2e-evm.dtb
kirkwood := \ kirkwood := \
kirkwood-b3.dtb \
kirkwood-cloudbox.dtb \ kirkwood-cloudbox.dtb \
kirkwood-db-88f6281.dtb \ kirkwood-db-88f6281.dtb \
kirkwood-db-88f6282.dtb \ kirkwood-db-88f6282.dtb \
...@@ -94,6 +94,18 @@ kirkwood := \ ...@@ -94,6 +94,18 @@ kirkwood := \
kirkwood-dns325.dtb \ kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \ kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \ kirkwood-dreamplug.dtb \
kirkwood-ds109.dtb \
kirkwood-ds110jv10.dtb \
kirkwood-ds111.dtb \
kirkwood-ds209.dtb \
kirkwood-ds210.dtb \
kirkwood-ds212.dtb \
kirkwood-ds212j.dtb \
kirkwood-ds409.dtb \
kirkwood-ds409slim.dtb \
kirkwood-ds411.dtb \
kirkwood-ds411j.dtb \
kirkwood-ds411slim.dtb \
kirkwood-goflexnet.dtb \ kirkwood-goflexnet.dtb \
kirkwood-guruplug-server-plus.dtb \ kirkwood-guruplug-server-plus.dtb \
kirkwood-ib62x0.dtb \ kirkwood-ib62x0.dtb \
...@@ -116,54 +128,74 @@ kirkwood := \ ...@@ -116,54 +128,74 @@ kirkwood := \
kirkwood-nsa310a.dtb \ kirkwood-nsa310a.dtb \
kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a6.dtb \
kirkwood-openblocks_a7.dtb \ kirkwood-openblocks_a7.dtb \
kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-a0.dtb \
kirkwood-rd88f6281-a1.dtb \
kirkwood-rs212.dtb \
kirkwood-rs409.dtb \
kirkwood-rs411.dtb \
kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug.dtb \
kirkwood-sheevaplug-esata.dtb \ kirkwood-sheevaplug-esata.dtb \
kirkwood-t5325.dtb \
kirkwood-topkick.dtb \ kirkwood-topkick.dtb \
kirkwood-ts219-6281.dtb \ kirkwood-ts219-6281.dtb \
kirkwood-ts219-6282.dtb kirkwood-ts219-6282.dtb \
kirkwood-ts419-6281.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
armada-370-rd.dtb \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-netgear-rn2120.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_ARCH_MXC) += \ dtb-$(CONFIG_ARCH_MXC) += \
imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-karo-tx25.dtb \ imx25-karo-tx25.dtb \
imx25-pdk.dtb \ imx25-pdk.dtb \
imx27-apf27.dtb \ imx27-apf27.dtb \
imx27-apf27dev.dtb \ imx27-apf27dev.dtb \
imx27-pdk.dtb \ imx27-pdk.dtb \
imx27-phytec-phycore-som.dtb \
imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-som.dtb \
imx27-phytec-phycard-s-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \ imx31-bug.dtb \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx50-evk.dtb \
imx51-apf51.dtb \ imx51-apf51.dtb \
imx51-apf51dev.dtb \ imx51-apf51dev.dtb \
imx51-babbage.dtb \ imx51-babbage.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx53-ard.dtb \ imx53-ard.dtb \
imx53-evk.dtb \
imx53-m53evk.dtb \ imx53-m53evk.dtb \
imx53-mba53.dtb \ imx53-mba53.dtb \
imx53-qsb.dtb \ imx53-qsb.dtb \
imx53-qsrb.dtb \
imx53-smd.dtb \ imx53-smd.dtb \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
imx53-voipac-bsb.dtb \
imx6dl-cubox-i.dtb \ imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
imx6dl-gw54xx.dtb \
imx6dl-hummingboard.dtb \ imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-sabreauto.dtb \ imx6dl-sabreauto.dtb \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \ imx6dl-sabresd.dtb \
imx6dl-wandboard.dtb \ imx6dl-wandboard.dtb \
imx6q-arm2.dtb \ imx6q-arm2.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \ imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
imx6q-gw52xx.dtb \
imx6q-gw53xx.dtb \
imx6q-gw5400-a.dtb \
imx6q-gw54xx.dtb \
imx6q-nitrogen6x.dtb \
imx6q-phytec-pbab01.dtb \ imx6q-phytec-pbab01.dtb \
imx6q-sabreauto.dtb \ imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \ imx6q-sabrelite.dtb \
...@@ -187,6 +219,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ ...@@ -187,6 +219,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-cfa10056.dtb \ imx28-cfa10056.dtb \
imx28-cfa10057.dtb \ imx28-cfa10057.dtb \
imx28-cfa10058.dtb \ imx28-cfa10058.dtb \
imx28-duckbill.dtb \
imx28-eukrea-mbmx283lc.dtb \
imx28-eukrea-mbmx287lc.dtb \
imx28-evk.dtb \ imx28-evk.dtb \
imx28-m28cu3.dtb \ imx28-m28cu3.dtb \
imx28-m28evk.dtb \ imx28-m28evk.dtb \
...@@ -203,6 +238,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ ...@@ -203,6 +238,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap2420-n810-wimax.dtb \ omap2420-n810-wimax.dtb \
omap3430-sdp.dtb \ omap3430-sdp.dtb \
omap3-beagle.dtb \ omap3-beagle.dtb \
omap3-cm-t3517.dtb \
omap3-sbc-t3517.dtb \
omap3-cm-t3530.dtb \
omap3-sbc-t3530.dtb \
omap3-cm-t3730.dtb \ omap3-cm-t3730.dtb \
omap3-sbc-t3730.dtb \ omap3-sbc-t3730.dtb \
omap3-devkit8000.dtb \ omap3-devkit8000.dtb \
...@@ -213,12 +252,24 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ ...@@ -213,12 +252,24 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n900.dtb \ omap3-n900.dtb \
omap3-n9.dtb \ omap3-n9.dtb \
omap3-n950.dtb \ omap3-n950.dtb \
omap3-overo-alto35.dtb \
omap3-overo-storm-alto35.dtb \
omap3-overo-chestnut43.dtb \
omap3-overo-storm-chestnut43.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-storm-gallop43.dtb \
omap3-overo-palo43.dtb \
omap3-overo-storm-palo43.dtb \
omap3-overo-summit.dtb \
omap3-overo-storm-summit.dtb \
omap3-overo-tobi.dtb \ omap3-overo-tobi.dtb \
omap3-overo-storm-tobi.dtb \ omap3-overo-storm-tobi.dtb \
omap3-gta04.dtb \ omap3-gta04.dtb \
omap3-igep0020.dtb \ omap3-igep0020.dtb \
omap3-igep0030.dtb \ omap3-igep0030.dtb \
omap3-lilly-dbb056.dtb \
omap3-zoom3.dtb \ omap3-zoom3.dtb \
omap4-duovero-parlor.dtb \
omap4-panda.dtb \ omap4-panda.dtb \
omap4-panda-a4.dtb \ omap4-panda-a4.dtb \
omap4-panda-es.dtb \ omap4-panda-es.dtb \
...@@ -232,9 +283,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ ...@@ -232,9 +283,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-boneblack.dtb \ am335x-boneblack.dtb \
am335x-nano.dtb \ am335x-nano.dtb \
am335x-base0033.dtb \ am335x-base0033.dtb \
am3517-craneboard.dtb \
am3517-evm.dtb \ am3517-evm.dtb \
am3517_mt_ventoux.dtb \ am3517_mt_ventoux.dtb \
am43x-epos-evm.dtb \ am43x-epos-evm.dtb \
am437x-gp-evm.dtb \
dra7-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
...@@ -291,6 +344,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ ...@@ -291,6 +344,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-cubieboard.dtb \ sun4i-a10-cubieboard.dtb \
sun4i-a10-mini-xplus.dtb \ sun4i-a10-mini-xplus.dtb \
sun4i-a10-hackberry.dtb \ sun4i-a10-hackberry.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-olinuxino-micro.dtb \
sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-olinuxino-micro.dtb \
...@@ -329,6 +385,29 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ ...@@ -329,6 +385,29 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \ zynq-zc706.dtb \
zynq-zed.dtb zynq-zed.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
armada-370-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db.dtb \
armada-385-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-netgear-rn2120.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
targets += dtbs dtbs_install targets += dtbs dtbs_install
targets += $(dtb-y) targets += $(dtb-y)
......
...@@ -260,6 +260,12 @@ davinci_mdio_sleep: davinci_mdio_sleep { ...@@ -260,6 +260,12 @@ davinci_mdio_sleep: davinci_mdio_sleep {
>; >;
}; };
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
lcd_pins_s0: lcd_pins_s0 { lcd_pins_s0: lcd_pins_s0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
...@@ -434,9 +440,9 @@ &gpmc { ...@@ -434,9 +440,9 @@ &gpmc {
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 { nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */ reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8"; ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true"; ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>; gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>; gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <0>;
...@@ -460,50 +466,51 @@ nand@0,0 { ...@@ -460,50 +466,51 @@ nand@0,0 {
gpmc,wait-monitoring-ns = <0>; gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>; gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
elm_id = <&elm>;
/* MTD partition table */
partition@0 { partition@0 {
label = "SPL1"; label = "NAND.SPL";
reg = <0x00000000 0x000020000>; reg = <0x00000000 0x000020000>;
}; };
partition@1 { partition@1 {
label = "SPL2"; label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>; reg = <0x00020000 0x00020000>;
}; };
partition@2 { partition@2 {
label = "SPL3"; label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>; reg = <0x00040000 0x00020000>;
}; };
partition@3 { partition@3 {
label = "SPL4"; label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>; reg = <0x00060000 0x00020000>;
}; };
partition@4 { partition@4 {
label = "U-boot"; label = "NAND.u-boot-spl";
reg = <0x00080000 0x001e0000>; reg = <0x00080000 0x00040000>;
}; };
partition@5 { partition@5 {
label = "environment"; label = "NAND.u-boot";
reg = <0x00260000 0x00020000>; reg = <0x000C0000 0x00100000>;
}; };
partition@6 { partition@6 {
label = "Kernel"; label = "NAND.u-boot-env";
reg = <0x00280000 0x00500000>; reg = <0x001C0000 0x00020000>;
}; };
partition@7 { partition@7 {
label = "File-System"; label = "NAND.u-boot-env.backup1";
reg = <0x00780000 0x0F880000>; reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
}; };
}; };
}; };
...@@ -643,6 +650,9 @@ &mmc1 { ...@@ -643,6 +650,9 @@ &mmc1 {
status = "okay"; status = "okay";
vmmc-supply = <&vmmc_reg>; vmmc-supply = <&vmmc_reg>;
bus-width = <4>; bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
}; };
&sham { &sham {
......
...@@ -45,6 +45,18 @@ lis3_reg: fixedregulator@1 { ...@@ -45,6 +45,18 @@ lis3_reg: fixedregulator@1 {
regulator-boot-on; regulator-boot-on;
}; };
wl12xx_vmmc: fixedregulator@2 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 29 0>;
startup-delay-us = <70000>;
enable-active-high;
};
leds { leds {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>; pinctrl-0 = <&user_leds_s0>;
...@@ -270,6 +282,24 @@ mcasp1_pins: mcasp1_pins { ...@@ -270,6 +282,24 @@ mcasp1_pins: mcasp1_pins {
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>; >;
}; };
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
>;
};
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
>;
};
}; };
&uart0 { &uart0 {
...@@ -342,9 +372,22 @@ usb-phy@47401300 { ...@@ -342,9 +372,22 @@ usb-phy@47401300 {
status = "okay"; status = "okay";
}; };
usb-phy@47401b00 {
status = "okay";
};
usb@47401000 { usb@47401000 {
status = "okay"; status = "okay";
}; };
usb@47401800 {
status = "okay";
dr_mode = "host";
};
dma-controller@07402000 {
status = "okay";
};
}; };
&epwmss2 { &epwmss2 {
...@@ -440,6 +483,7 @@ &mac { ...@@ -440,6 +483,7 @@ &mac {
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>; pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>; pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
}; };
&davinci_mdio { &davinci_mdio {
...@@ -451,11 +495,13 @@ &davinci_mdio { ...@@ -451,11 +495,13 @@ &davinci_mdio {
&cpsw_emac0 { &cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>; phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid"; phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
}; };
&cpsw_emac1 { &cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>; phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid"; phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
}; };
&mmc1 { &mmc1 {
...@@ -479,6 +525,16 @@ &gpio0 { ...@@ -479,6 +525,16 @@ &gpio0 {
ti,no-reset-on-init; ti,no-reset-on-init;
}; };
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
ti,non-removable;
bus-width = <4>;
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
};
&mcasp1 { &mcasp1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mcasp1_pins>; pinctrl-0 = <&mcasp1_pins>;
......
...@@ -58,6 +58,10 @@ cpu@0 { ...@@ -58,6 +58,10 @@ cpu@0 {
275000 1125000 275000 1125000
>; >;
voltage-tolerance = <2>; /* 2 percentage */ voltage-tolerance = <2>; /* 2 percentage */
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */ clock-latency = <300000>; /* From omap-cpufreq driver */
}; };
}; };
...@@ -318,6 +322,7 @@ hwspinlock: spinlock@480ca000 { ...@@ -318,6 +322,7 @@ hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock"; compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>; reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock"; ti,hwmods = "spinlock";
#hwlock-cells = <1>;
}; };
wdt2: wdt@44e35000 { wdt2: wdt@44e35000 {
...@@ -399,7 +404,7 @@ timer7: timer@4804a000 { ...@@ -399,7 +404,7 @@ timer7: timer@4804a000 {
ti,timer-pwm; ti,timer-pwm;
}; };
rtc@44e3e000 { rtc: rtc@44e3e000 {
compatible = "ti,da830-rtc"; compatible = "ti,da830-rtc";
reg = <0x44e3e000 0x1000>; reg = <0x44e3e000 0x1000>;
interrupts = <75 interrupts = <75
...@@ -582,6 +587,8 @@ ecap0: ecap@48300100 { ...@@ -582,6 +587,8 @@ ecap0: ecap@48300100 {
compatible = "ti,am33xx-ecap"; compatible = "ti,am33xx-ecap";
#pwm-cells = <3>; #pwm-cells = <3>;
reg = <0x48300100 0x80>; reg = <0x48300100 0x80>;
interrupts = <31>;
interrupt-names = "ecap0";
ti,hwmods = "ecap0"; ti,hwmods = "ecap0";
status = "disabled"; status = "disabled";
}; };
...@@ -610,6 +617,8 @@ ecap1: ecap@48302100 { ...@@ -610,6 +617,8 @@ ecap1: ecap@48302100 {
compatible = "ti,am33xx-ecap"; compatible = "ti,am33xx-ecap";
#pwm-cells = <3>; #pwm-cells = <3>;
reg = <0x48302100 0x80>; reg = <0x48302100 0x80>;
interrupts = <47>;
interrupt-names = "ecap1";
ti,hwmods = "ecap1"; ti,hwmods = "ecap1";
status = "disabled"; status = "disabled";
}; };
...@@ -638,6 +647,8 @@ ecap2: ecap@48304100 { ...@@ -638,6 +647,8 @@ ecap2: ecap@48304100 {
compatible = "ti,am33xx-ecap"; compatible = "ti,am33xx-ecap";
#pwm-cells = <3>; #pwm-cells = <3>;
reg = <0x48304100 0x80>; reg = <0x48304100 0x80>;
interrupts = <61>;
interrupt-names = "ecap2";
ti,hwmods = "ecap2"; ti,hwmods = "ecap2";
status = "disabled"; status = "disabled";
}; };
......
/*
* See craneboard.org for more details
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am3517.dtsi"
/ {
model = "TI AM3517 CraneBoard (TMDSEVM3517)";
compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
};
&davinci_emac {
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&i2c1 {
clock-frequency = <2600000>;
tps: tps@2d {
reg = <0x2d>;
};
};
&i2c2 {
clock-frequency = <400000>;
/* goes to expansion connector */
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
/* goes to expansion connector */
status = "disabled";
};
&mmc1 {
vmmc-supply = <&vdd2_reg>;
bus-width = <8>;
};
&mmc2 {
/* goes to expansion connector */
status = "disabled";
};
&mmc3 {
/* goes to expansion connector */
status = "disabled";
};
#include "tps65910.dtsi"
&omap3_pmx_core {
tps_pins: pinmux_tps_pins {
pinctrl-single,pins = <
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
>;
};
};
&tps {
pinctrl-names = "default";
pinctrl-0 = <&tps_pins>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
ti,en-ck32k-xtal;
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
/*
* Unused:
* VDIG1=2.7V,300mA max
* VDIG2=1.8V,300mA max
*/
vpll_reg: regulator@7 {
/* VDDS_DPLL_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vaux1_reg: regulator@9 {
/* VDDS_SRAM_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vaux2_reg: regulator@10 {
/* VDDA1P8V_USBPHY */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
/* VAUX33 unused */
vdac_reg: regulator@8 {
/* VDDA_DAC_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vmmc_reg: regulator@12 {
/* VDDA3P3V_USBPHY */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_CORE */
regulator-name = "vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDDSHV_3V3 */
regulator-name = "vdd_shv";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* VDD3 unused */
};
};
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
* kind, whether express or implied. * kind, whether express or implied.
*/ */
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
...@@ -33,6 +34,11 @@ cpu@0 { ...@@ -33,6 +34,11 @@ cpu@0 {
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
}; };
}; };
...@@ -351,6 +357,13 @@ gpio5: gpio@48322000 { ...@@ -351,6 +357,13 @@ gpio5: gpio@48322000 {
status = "disabled"; status = "disabled";
}; };
hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
i2c0: i2c@44e0b000 { i2c0: i2c@44e0b000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c"; compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x44e0b000 0x1000>; reg = <0x44e0b000 0x1000>;
...@@ -521,6 +534,7 @@ epwmss0: epwmss@48300000 { ...@@ -521,6 +534,7 @@ epwmss0: epwmss@48300000 {
ecap0: ecap@48300100 { ecap0: ecap@48300100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap"; compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>; reg = <0x48300100 0x80>;
ti,hwmods = "ecap0"; ti,hwmods = "ecap0";
status = "disabled"; status = "disabled";
...@@ -528,6 +542,7 @@ ecap0: ecap@48300100 { ...@@ -528,6 +542,7 @@ ecap0: ecap@48300100 {
ehrpwm0: ehrpwm@48300200 { ehrpwm0: ehrpwm@48300200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>; reg = <0x48300200 0x80>;
ti,hwmods = "ehrpwm0"; ti,hwmods = "ehrpwm0";
status = "disabled"; status = "disabled";
...@@ -545,6 +560,7 @@ epwmss1: epwmss@48302000 { ...@@ -545,6 +560,7 @@ epwmss1: epwmss@48302000 {
ecap1: ecap@48302100 { ecap1: ecap@48302100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap"; compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>; reg = <0x48302100 0x80>;
ti,hwmods = "ecap1"; ti,hwmods = "ecap1";
status = "disabled"; status = "disabled";
...@@ -552,6 +568,7 @@ ecap1: ecap@48302100 { ...@@ -552,6 +568,7 @@ ecap1: ecap@48302100 {
ehrpwm1: ehrpwm@48302200 { ehrpwm1: ehrpwm@48302200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>; reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1"; ti,hwmods = "ehrpwm1";
status = "disabled"; status = "disabled";
...@@ -569,6 +586,7 @@ epwmss2: epwmss@48304000 { ...@@ -569,6 +586,7 @@ epwmss2: epwmss@48304000 {
ecap2: ecap@48304100 { ecap2: ecap@48304100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap"; compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>; reg = <0x48304100 0x80>;
ti,hwmods = "ecap2"; ti,hwmods = "ecap2";
status = "disabled"; status = "disabled";
...@@ -576,6 +594,7 @@ ecap2: ecap@48304100 { ...@@ -576,6 +594,7 @@ ecap2: ecap@48304100 {
ehrpwm2: ehrpwm@48304200 { ehrpwm2: ehrpwm@48304200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>; reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2"; ti,hwmods = "ehrpwm2";
status = "disabled"; status = "disabled";
...@@ -593,6 +612,7 @@ epwmss3: epwmss@48306000 { ...@@ -593,6 +612,7 @@ epwmss3: epwmss@48306000 {
ehrpwm3: ehrpwm@48306200 { ehrpwm3: ehrpwm@48306200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>; reg = <0x48306200 0x80>;
ti,hwmods = "ehrpwm3"; ti,hwmods = "ehrpwm3";
status = "disabled"; status = "disabled";
...@@ -610,6 +630,7 @@ epwmss4: epwmss@48308000 { ...@@ -610,6 +630,7 @@ epwmss4: epwmss@48308000 {
ehrpwm4: ehrpwm@48308200 { ehrpwm4: ehrpwm@48308200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>; reg = <0x48308200 0x80>;
ti,hwmods = "ehrpwm4"; ti,hwmods = "ehrpwm4";
status = "disabled"; status = "disabled";
...@@ -627,6 +648,7 @@ epwmss5: epwmss@4830a000 { ...@@ -627,6 +648,7 @@ epwmss5: epwmss@4830a000 {
ehrpwm5: ehrpwm@4830a200 { ehrpwm5: ehrpwm@4830a200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>; reg = <0x4830a200 0x80>;
ti,hwmods = "ehrpwm5"; ti,hwmods = "ehrpwm5";
status = "disabled"; status = "disabled";
...@@ -689,6 +711,30 @@ mcasp1: mcasp@4803C000 { ...@@ -689,6 +711,30 @@ mcasp1: mcasp@4803C000 {
<&edma 11>; <&edma 11>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
};
}; };
}; };
......
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* AM437x GP EVM */
/dts-v1/;
#include "am4372.dtsi"
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "TI AM437x GP EVM";
compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
vmmcsd_fixed: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
linux,keymap = <0x00000201 /* P1 */
0x00010202 /* P2 */
0x01000067 /* UP */
0x0101006a /* RIGHT */
0x02000069 /* LEFT */
0x0201006c>; /* DOWN */
};
};
&am43xx_pinmux {
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&epwmss0 {
status = "okay";
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};
&gpio0 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "am4372.dtsi" #include "am4372.dtsi"
#include <dt-bindings/pinctrl/am43xx.h> #include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
/ { / {
model = "TI AM43x EPOS EVM"; model = "TI AM43x EPOS EVM";
...@@ -79,6 +80,64 @@ i2c0_pins: pinmux_i2c0_pins { ...@@ -79,6 +80,64 @@ i2c0_pins: pinmux_i2c0_pins {
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>; >;
}; };
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
}; };
matrix_keypad: matrix_keypad@0 { matrix_keypad: matrix_keypad@0 {
...@@ -113,12 +172,22 @@ &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ ...@@ -113,12 +172,22 @@ &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
0x0203006c /* DOWN */ 0x0203006c /* DOWN */
0x03030069>; /* LEFT */ 0x03030069>; /* LEFT */
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
}; };
&mmc1 { &mmc1 {
status = "okay"; status = "okay";
vmmc-supply = <&vmmcsd_fixed>; vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>; bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
}; };
&mac { &mac {
...@@ -169,6 +238,12 @@ pixcir_ts@5c { ...@@ -169,6 +238,12 @@ pixcir_ts@5c {
}; };
}; };
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&gpio0 { &gpio0 {
status = "okay"; status = "okay";
}; };
...@@ -184,3 +259,111 @@ &gpio2 { ...@@ -184,3 +259,111 @@ &gpio2 {
&gpio3 { &gpio3 {
status = "okay"; status = "okay";
}; };
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>; /* cs-on-ns */
gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
gpmc,we-on-ns = <0>; /* cs-on-ns */
gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
gpmc,access-ns = <30>; /* tCEA + 4*/
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000C0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002C0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00800000 0x1F600000>;
};
};
};
&epwmss0 {
status = "okay";
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
};
...@@ -64,6 +64,22 @@ ethernet@74000 { ...@@ -64,6 +64,22 @@ ethernet@74000 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
}; };
i2c@11000 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
audio_codec: audio-codec@4a {
compatible = "cirrus,cs42l51";
reg = <0x4a>;
};
};
audio-controller@30000 {
pinctrl-0 = <&i2s_pins2>;
pinctrl-names = "default";
status = "okay";
};
mvsdio@d4000 { mvsdio@d4000 {
pinctrl-0 = <&sdio_pins1>; pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -80,6 +96,30 @@ mvsdio@d4000 { ...@@ -80,6 +96,30 @@ mvsdio@d4000 {
broken-cd; broken-cd;
}; };
pinctrl {
/*
* These pins might be muxed as I2S by
* the bootloader, but it conflicts
* with the real I2S pins that are
* muxed using i2s_pins. We must mux
* those pins to a function other than
* I2S.
*/
pinctrl-0 = <&hog_pins1 &hog_pins2>;
pinctrl-names = "default";
hog_pins1: hog-pins1 {
marvell,pins = "mpp6", "mpp8", "mpp10",
"mpp12", "mpp13";
marvell,function = "gpio";
};
hog_pins2: hog-pins2 {
marvell,pins = "mpp5", "mpp7", "mpp9";
marvell,function = "gpo";
};
};
usb@50000 { usb@50000 {
status = "okay"; status = "okay";
}; };
...@@ -112,10 +152,26 @@ pcie@1,0 { ...@@ -112,10 +152,26 @@ pcie@1,0 {
/* Port 0, Lane 0 */ /* Port 0, Lane 0 */
status = "okay"; status = "okay";
}; };
pcie@2,0 { pcie@2,0 {
/* Port 1, Lane 0 */ /* Port 1, Lane 0 */
status = "okay"; status = "okay";
}; };
}; };
}; };
sound {
compatible = "marvell,a370db-audio";
marvell,audio-controller = <&audio_controller>;
marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
status = "okay";
};
spdif_out: spdif-out {
compatible = "linux,spdif-dit";
};
spdif_in: spdif-in {
compatible = "linux,spdif-dir";
};
}; };
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi" #include "armada-370.dtsi"
/ { / {
...@@ -73,19 +74,19 @@ gpio_leds { ...@@ -73,19 +74,19 @@ gpio_leds {
green_pwr_led { green_pwr_led {
label = "mirabox:green:pwr"; label = "mirabox:green:pwr";
gpios = <&gpio1 31 1>; gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
default-state = "keep"; default-state = "keep";
}; };
blue_stat_led { blue_stat_led {
label = "mirabox:blue:stat"; label = "mirabox:blue:stat";
gpios = <&gpio2 0 1>; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
default-state = "off"; default-state = "off";
}; };
green_stat_led { green_stat_led {
label = "mirabox:green:stat"; label = "mirabox:green:stat";
gpios = <&gpio2 1 1>; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
default-state = "off"; default-state = "off";
}; };
}; };
......
...@@ -12,6 +12,8 @@ ...@@ -12,6 +12,8 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi" #include "armada-370.dtsi"
/ { / {
...@@ -100,8 +102,8 @@ gpio-keys { ...@@ -100,8 +102,8 @@ gpio-keys {
#size-cells = <0>; #size-cells = <0>;
button@1 { button@1 {
label = "Software Button"; label = "Software Button";
linux,code = <116>; linux,code = <KEY_POWER>;
gpios = <&gpio0 6 1>; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
}; };
}; };
......
...@@ -44,8 +44,8 @@ soc { ...@@ -44,8 +44,8 @@ soc {
#size-cells = <1>; #size-cells = <1>;
controller = <&mbusc>; controller = <&mbusc>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
pcie-mem-aperture = <0xe0000000 0x8000000>; pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xe8000000 0x100000>; pcie-io-aperture = <0xffe00000 0x100000>;
devbus-bootcs { devbus-bootcs {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
...@@ -199,6 +199,10 @@ timer@20300 { ...@@ -199,6 +199,10 @@ timer@20300 {
interrupts = <37>, <38>, <39>, <40>, <5>, <6>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
}; };
watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
usb@50000 { usb@50000 {
compatible = "marvell,orion-ehci"; compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>; reg = <0x50000 0x500>;
......
...@@ -132,6 +132,25 @@ sdio_pins3: sdio-pins3 { ...@@ -132,6 +132,25 @@ sdio_pins3: sdio-pins3 {
"mpp51", "mpp52", "mpp53"; "mpp51", "mpp52", "mpp53";
marvell,function = "sd0"; marvell,function = "sd0";
}; };
i2c0_pins: i2c0-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c0";
};
i2s_pins1: i2s-pins1 {
marvell,pins = "mpp5", "mpp6", "mpp7",
"mpp8", "mpp9", "mpp10",
"mpp12", "mpp13";
marvell,function = "audio";
};
i2s_pins2: i2s-pins2 {
marvell,pins = "mpp49", "mpp47", "mpp50",
"mpp59", "mpp57", "mpp61",
"mpp62", "mpp60", "mpp58";
marvell,function = "audio";
};
}; };
gpio0: gpio@18100 { gpio0: gpio@18100 {
...@@ -196,6 +215,20 @@ timer@20300 { ...@@ -196,6 +215,20 @@ timer@20300 {
clocks = <&coreclk 2>; clocks = <&coreclk 2>;
}; };
watchdog@20300 {
compatible = "marvell,armada-370-wdt";
clocks = <&coreclk 2>;
};
audio_controller: audio-controller@30000 {
compatible = "marvell,armada370-audio";
reg = <0x30000 0x4000>;
interrupts = <93>;
clocks = <&gateclk 0>;
clock-names = "internal";
status = "disabled";
};
usb@50000 { usb@50000 {
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
}; };
......
/*
* Device Tree file for Marvell Armada 375 evaluation board
* (DB-88F6720)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-375.dtsi"
/ {
model = "Marvell Armada 375 Development Board";
compatible = "marvell,a375-db", "marvell,armada375";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
/*
* SPI conflicts with NAND, so we disable it
* here, and select NAND as the enabled device
* by default.
*/
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
i2c@11100 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
pinctrl {
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
nand: nand@d0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
This diff is collapsed.
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 380 family SoC";
compatible = "marvell,armada380", "marvell,armada38x";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
};
soc {
internal-regs {
pinctrl {
compatible = "marvell,mv88f6810-pinctrl";
reg = <0x18000 0x20>;
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
/* x1 port */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
};
};
};
};
/*
* Device Tree file for Marvell Armada 385 evaluation board
* (DB-88F6820)
*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 385 Development Board";
compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@11100 {
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
ethernet@30000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
/*
* Device Tree file for Marvell Armada 385 Reference Design board
* (RD-88F6820-AP)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 385 Reference Design";
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
ethernet@30000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@70000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
pcie-controller {
status = "okay";
/*
* One PCIe units is accessible through
* standard PCIe slot on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 385 family SoC";
compatible = "marvell,armada385", "marvell,armada38x";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
soc {
internal-regs {
pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
reg = <0x18000 0x20>;
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
/*
* This port can be either x4 or x1. When
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
};
/*
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 7>;
status = "disabled";
};
};
};
};
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada38x";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
eth0 = &eth0;
eth1 = &eth1;
eth2 = &eth2;
};
soc {
compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
reg = <0x18000 0x20>;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-380-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;
#clock-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
interrupts-extended = <&mpic 10>;
clocks = <&gateclk 3>;
status = "disabled";
};
eth2: ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts-extended = <&mpic 12>;
clocks = <&gateclk 2>;
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
};
coredivclk: clock@e4250 {
compatible = "marvell,armada-380-corediv-clock";
reg = <0xe4250 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
flash@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
};
};
clocks {
/* 2 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
};
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
...@@ -16,6 +16,8 @@ ...@@ -16,6 +16,8 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-xp-mv78230.dtsi" #include "armada-xp-mv78230.dtsi"
/ { / {
...@@ -157,8 +159,8 @@ gpio_keys { ...@@ -157,8 +159,8 @@ gpio_keys {
button@1 { button@1 {
label = "Factory Reset Button"; label = "Factory Reset Button";
linux,code = <141>; /* KEY_SETUP */ linux,code = <KEY_SETUP>;
gpios = <&gpio1 1 1>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
}; };
}; };
}; };
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* Device Tree file for Marvell Armada XP evaluation board * Device Tree file for Marvell Armada XP evaluation board
* (DB-78460-BP) * (DB-78460-BP)
* *
* Copyright (C) 2012 Marvell * Copyright (C) 2012-2014 Marvell
* *
* Lior Amsalem <alior@marvell.com> * Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com> * Gregory CLEMENT <gregory.clement@free-electrons.com>
...@@ -11,6 +11,15 @@ ...@@ -11,6 +11,15 @@
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/ */
/dts-v1/; /dts-v1/;
...@@ -30,7 +39,7 @@ memory { ...@@ -30,7 +39,7 @@ memory {
}; };
soc { soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* Device Tree file for Marvell Armada XP development board * Device Tree file for Marvell Armada XP development board
* (DB-MV784MP-GP) * (DB-MV784MP-GP)
* *
* Copyright (C) 2013 Marvell * Copyright (C) 2013-2014 Marvell
* *
* Lior Amsalem <alior@marvell.com> * Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com> * Gregory CLEMENT <gregory.clement@free-electrons.com>
...@@ -11,6 +11,15 @@ ...@@ -11,6 +11,15 @@
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/ */
/dts-v1/; /dts-v1/;
...@@ -30,16 +39,17 @@ memory { ...@@ -30,16 +39,17 @@ memory {
* 8 GB of plug-in RAM modules by default.The amount * 8 GB of plug-in RAM modules by default.The amount
* of memory available can be changed by the * of memory available can be changed by the
* bootloader according the size of the module * bootloader according the size of the module
* actually plugged. Only 7GB are usable because * actually plugged. However, memory between
* addresses from 0xC0000000 to 0xffffffff are used by * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
* the internal registers of the SoC. * the address range used for I/O (internal registers,
* MBus windows).
*/ */
reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
<0x00000001 0x00000000 0x00000001 0x00000000>; <0x00000001 0x00000000 0x00000001 0x00000000>;
}; };
soc { soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
......
...@@ -23,7 +23,12 @@ chosen { ...@@ -23,7 +23,12 @@ chosen {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ /*
* This board has 4 GB of RAM, but the last 256 MB of
* RAM are not usable due to the overlap with the MBus
* Window address range
*/
reg = <0 0x00000000 0 0xf0000000>;
}; };
soc { soc {
......
...@@ -11,6 +11,8 @@ ...@@ -11,6 +11,8 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-xp-mv78260.dtsi" #include "armada-xp-mv78260.dtsi"
/ { / {
...@@ -90,19 +92,19 @@ leds { ...@@ -90,19 +92,19 @@ leds {
red_led { red_led {
label = "red_led"; label = "red_led";
gpios = <&gpio1 17 1>; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
default-state = "off"; default-state = "off";
}; };
yellow_led { yellow_led {
label = "yellow_led"; label = "yellow_led";
gpios = <&gpio1 19 1>; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
default-state = "off"; default-state = "off";
}; };
green_led { green_led {
label = "green_led"; label = "green_led";
gpios = <&gpio1 21 1>; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
default-state = "keep"; default-state = "keep";
}; };
}; };
...@@ -114,8 +116,8 @@ gpio_keys { ...@@ -114,8 +116,8 @@ gpio_keys {
button@1 { button@1 {
label = "Init Button"; label = "Init Button";
linux,code = <116>; linux,code = <KEY_POWER>;
gpios = <&gpio1 28 0>; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
}; };
}; };
......
...@@ -111,6 +111,12 @@ timer@20300 { ...@@ -111,6 +111,12 @@ timer@20300 {
clock-names = "nbclk", "fixed"; clock-names = "nbclk", "fixed";
}; };
watchdog@20300 {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
armada-370-xp-pmsu@22000 { armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu"; compatible = "marvell,armada-370-xp-pmsu";
reg = <0x22100 0x400>, <0x20800 0x20>; reg = <0x22100 0x400>, <0x20800 0x20>;
......
...@@ -129,7 +129,6 @@ uart1: serial@f8044000 { ...@@ -129,7 +129,6 @@ uart1: serial@f8044000 {
adc0: adc@f804c000 { adc0: adc@f804c000 {
status = "okay"; status = "okay";
atmel,adc-channels-used = <0xf>; atmel,adc-channels-used = <0xf>;
atmel,adc-num-channels = <4>;
}; };
dbgu: serial@fffff200 { dbgu: serial@fffff200 {
......
...@@ -64,7 +64,6 @@ i2c0: i2c@f8010000 { ...@@ -64,7 +64,6 @@ i2c0: i2c@f8010000 {
}; };
adc0: adc@f804c000 { adc0: adc@f804c000 {
atmel,adc-clock-rate = <1000000>;
atmel,adc-ts-wires = <4>; atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>; atmel,adc-ts-pressure-threshold = <10000>;
status = "okay"; status = "okay";
......
...@@ -27,7 +27,6 @@ macb0: ethernet@f802c000 { ...@@ -27,7 +27,6 @@ macb0: ethernet@f802c000 {
}; };
adc0: adc@f804c000 { adc0: adc@f804c000 {
atmel,adc-clock-rate = <1000000>;
atmel,adc-ts-wires = <4>; atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>; atmel,adc-ts-pressure-threshold = <10000>;
status = "okay"; status = "okay";
......
...@@ -608,37 +608,38 @@ spi1: spi@fffcc000 { ...@@ -608,37 +608,38 @@ spi1: spi@fffcc000 {
}; };
adc0: adc@fffe0000 { adc0: adc@fffe0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc"; compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>; reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
atmel,adc-use-external-triggers; atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>; atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>; atmel,adc-vref = <3300>;
atmel,adc-num-channels = <4>;
atmel,adc-startup-time = <15>; atmel,adc-startup-time = <15>;
atmel,adc-channel-base = <0x30>;
atmel,adc-drdy-mask = <0x10000>;
atmel,adc-status-register = <0x1c>;
atmel,adc-trigger-register = <0x04>;
atmel,adc-res = <8 10>; atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres"; atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres"; atmel,adc-use-res = "highres";
trigger@0 { trigger@0 {
reg = <0>;
trigger-name = "timer-counter-0"; trigger-name = "timer-counter-0";
trigger-value = <0x1>; trigger-value = <0x1>;
}; };
trigger@1 { trigger@1 {
reg = <1>;
trigger-name = "timer-counter-1"; trigger-name = "timer-counter-1";
trigger-value = <0x3>; trigger-value = <0x3>;
}; };
trigger@2 { trigger@2 {
reg = <2>;
trigger-name = "timer-counter-2"; trigger-name = "timer-counter-2";
trigger-value = <0x5>; trigger-value = <0x5>;
}; };
trigger@3 { trigger@3 {
reg = <3>;
trigger-name = "external"; trigger-name = "external";
trigger-value = <0x13>; trigger-value = <0x13>;
trigger-external; trigger-external;
......
...@@ -632,40 +632,41 @@ ssc1: ssc@fffa0000 { ...@@ -632,40 +632,41 @@ ssc1: ssc@fffa0000 {
}; };
adc0: adc@fffb0000 { adc0: adc@fffb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc"; compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>; reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
atmel,adc-use-external-triggers; atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xff>; atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>; atmel,adc-vref = <3300>;
atmel,adc-num-channels = <8>;
atmel,adc-startup-time = <40>; atmel,adc-startup-time = <40>;
atmel,adc-channel-base = <0x30>;
atmel,adc-drdy-mask = <0x10000>;
atmel,adc-status-register = <0x1c>;
atmel,adc-trigger-register = <0x08>;
atmel,adc-res = <8 10>; atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres"; atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres"; atmel,adc-use-res = "highres";
trigger@0 { trigger@0 {
reg = <0>;
trigger-name = "external-rising"; trigger-name = "external-rising";
trigger-value = <0x1>; trigger-value = <0x1>;
trigger-external; trigger-external;
}; };
trigger@1 { trigger@1 {
reg = <1>;
trigger-name = "external-falling"; trigger-name = "external-falling";
trigger-value = <0x2>; trigger-value = <0x2>;
trigger-external; trigger-external;
}; };
trigger@2 { trigger@2 {
reg = <2>;
trigger-name = "external-any"; trigger-name = "external-any";
trigger-value = <0x3>; trigger-value = <0x3>;
trigger-external; trigger-external;
}; };
trigger@3 { trigger@3 {
reg = <3>;
trigger-name = "continuous"; trigger-name = "continuous";
trigger-value = <0x6>; trigger-value = <0x6>;
}; };
...@@ -817,6 +818,7 @@ nand0: nand@40000000 { ...@@ -817,6 +818,7 @@ nand0: nand@40000000 {
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
atmel,nand-has-dma;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioC 8 GPIO_ACTIVE_HIGH gpios = <&pioC 8 GPIO_ACTIVE_HIGH
......
...@@ -570,6 +570,7 @@ nand0: nand@40000000 { ...@@ -570,6 +570,7 @@ nand0: nand@40000000 {
atmel,pmecc-lookup-table-offset = <0x0 0x8000>; atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
atmel,nand-has-dma;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioD 5 GPIO_ACTIVE_HIGH gpios = <&pioD 5 GPIO_ACTIVE_HIGH
......
...@@ -621,41 +621,42 @@ uart1: serial@f8044000 { ...@@ -621,41 +621,42 @@ uart1: serial@f8044000 {
}; };
adc0: adc@f804c000 { adc0: adc@f804c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc"; compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>; reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
atmel,adc-use-external; atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xffff>; atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>; atmel,adc-vref = <3300>;
atmel,adc-num-channels = <12>;
atmel,adc-startup-time = <40>; atmel,adc-startup-time = <40>;
atmel,adc-channel-base = <0x50>;
atmel,adc-drdy-mask = <0x1000000>;
atmel,adc-status-register = <0x30>;
atmel,adc-trigger-register = <0xc0>;
atmel,adc-res = <8 10>; atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres"; atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres"; atmel,adc-use-res = "highres";
trigger@0 { trigger@0 {
reg = <0>;
trigger-name = "external-rising"; trigger-name = "external-rising";
trigger-value = <0x1>; trigger-value = <0x1>;
trigger-external; trigger-external;
}; };
trigger@1 { trigger@1 {
reg = <1>;
trigger-name = "external-falling"; trigger-name = "external-falling";
trigger-value = <0x2>; trigger-value = <0x2>;
trigger-external; trigger-external;
}; };
trigger@2 { trigger@2 {
reg = <2>;
trigger-name = "external-any"; trigger-name = "external-any";
trigger-value = <0x3>; trigger-value = <0x3>;
trigger-external; trigger-external;
}; };
trigger@3 { trigger@3 {
reg = <3>;
trigger-name = "continuous"; trigger-name = "continuous";
trigger-value = <0x6>; trigger-value = <0x6>;
}; };
...@@ -790,6 +791,7 @@ nand0: nand@40000000 { ...@@ -790,6 +791,7 @@ nand0: nand@40000000 {
atmel,pmecc-lookup-table-offset = <0x0 0x8000>; atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
atmel,nand-has-dma;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioD 5 GPIO_ACTIVE_HIGH gpios = <&pioD 5 GPIO_ACTIVE_HIGH
......
...@@ -14,6 +14,8 @@ ...@@ -14,6 +14,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include "dt-bindings/clock/bcm281xx.h"
#include "skeleton.dtsi" #include "skeleton.dtsi"
/ { / {
...@@ -43,7 +45,7 @@ uart@3e000000 { ...@@ -43,7 +45,7 @@ uart@3e000000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled"; status = "disabled";
reg = <0x3e000000 0x1000>; reg = <0x3e000000 0x1000>;
clocks = <&uartb_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -53,7 +55,7 @@ uart@3e001000 { ...@@ -53,7 +55,7 @@ uart@3e001000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled"; status = "disabled";
reg = <0x3e001000 0x1000>; reg = <0x3e001000 0x1000>;
clocks = <&uartb2_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -63,7 +65,7 @@ uart@3e002000 { ...@@ -63,7 +65,7 @@ uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled"; status = "disabled";
reg = <0x3e002000 0x1000>; reg = <0x3e002000 0x1000>;
clocks = <&uartb3_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -73,7 +75,7 @@ uart@3e003000 { ...@@ -73,7 +75,7 @@ uart@3e003000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled"; status = "disabled";
reg = <0x3e003000 0x1000>; reg = <0x3e003000 0x1000>;
clocks = <&uartb4_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -95,7 +97,7 @@ timer@35006000 { ...@@ -95,7 +97,7 @@ timer@35006000 {
compatible = "brcm,kona-timer"; compatible = "brcm,kona-timer";
reg = <0x35006000 0x1000>; reg = <0x35006000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hub_timer_clk>; clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
}; };
gpio: gpio@35003000 { gpio: gpio@35003000 {
...@@ -118,7 +120,7 @@ sdio1: sdio@3f180000 { ...@@ -118,7 +120,7 @@ sdio1: sdio@3f180000 {
compatible = "brcm,kona-sdhci"; compatible = "brcm,kona-sdhci";
reg = <0x3f180000 0x10000>; reg = <0x3f180000 0x10000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio1_clk>; clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
status = "disabled"; status = "disabled";
}; };
...@@ -126,7 +128,7 @@ sdio2: sdio@3f190000 { ...@@ -126,7 +128,7 @@ sdio2: sdio@3f190000 {
compatible = "brcm,kona-sdhci"; compatible = "brcm,kona-sdhci";
reg = <0x3f190000 0x10000>; reg = <0x3f190000 0x10000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio2_clk>; clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
status = "disabled"; status = "disabled";
}; };
...@@ -134,7 +136,7 @@ sdio3: sdio@3f1a0000 { ...@@ -134,7 +136,7 @@ sdio3: sdio@3f1a0000 {
compatible = "brcm,kona-sdhci"; compatible = "brcm,kona-sdhci";
reg = <0x3f1a0000 0x10000>; reg = <0x3f1a0000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio3_clk>; clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
status = "disabled"; status = "disabled";
}; };
...@@ -142,7 +144,7 @@ sdio4: sdio@3f1b0000 { ...@@ -142,7 +144,7 @@ sdio4: sdio@3f1b0000 {
compatible = "brcm,kona-sdhci"; compatible = "brcm,kona-sdhci";
reg = <0x3f1b0000 0x10000>; reg = <0x3f1b0000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio4_clk>; clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
status = "disabled"; status = "disabled";
}; };
...@@ -157,7 +159,7 @@ i2c@3e016000 { ...@@ -157,7 +159,7 @@ i2c@3e016000 {
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&bsc1_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
status = "disabled"; status = "disabled";
}; };
...@@ -167,7 +169,7 @@ i2c@3e017000 { ...@@ -167,7 +169,7 @@ i2c@3e017000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&bsc2_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
status = "disabled"; status = "disabled";
}; };
...@@ -177,7 +179,7 @@ i2c@3e018000 { ...@@ -177,7 +179,7 @@ i2c@3e018000 {
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&bsc3_clk>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
status = "disabled"; status = "disabled";
}; };
...@@ -187,105 +189,191 @@ i2c@3500d000 { ...@@ -187,105 +189,191 @@ i2c@3500d000 {
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&pmu_bsc_clk>; clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
status = "disabled"; status = "disabled";
}; };
clocks { clocks {
bsc1_clk: bsc1 { #address-cells = <1>;
compatible = "fixed-clock"; #size-cells = <1>;
clock-frequency = <13000000>; ranges;
root_ccu: root_ccu {
compatible = "brcm,bcm11351-root-ccu";
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
hub_ccu: hub_ccu {
compatible = "brcm,bcm11351-hub-ccu";
reg = <0x34000000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "tmon_1m";
};
aon_ccu: aon_ccu {
compatible = "brcm,bcm11351-aon-ccu";
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "hub_timer",
"pmu_bsc",
"pmu_bsc_var";
};
master_ccu: master_ccu {
compatible = "brcm,bcm11351-master-ccu";
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "sdio1",
"sdio2",
"sdio3",
"sdio4",
"usb_ic",
"hsic2_48m",
"hsic2_12m";
};
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4",
"ssp0",
"ssp2",
"bsc1",
"bsc2",
"bsc3",
"pwm";
};
ref_1m_clk: ref_1m {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1000000>;
}; };
bsc2_clk: bsc2 { ref_32k_clk: ref_32k {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <32768>;
};
bbl_32k_clk: bbl_32k {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
}; };
bsc3_clk: bsc3 { ref_13m_clk: ref_13m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <13000000>;
#clock-cells = <0>;
}; };
pmu_bsc_clk: pmu_bsc { var_13m_clk: var_13m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <13000000>;
#clock-cells = <0>;
}; };
hub_timer_clk: hub_timer { dft_19_5m_clk: dft_19_5m {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19500000>;
}; };
pwm_clk: pwm { ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <26000000>; clock-frequency = <26000000>;
#clock-cells = <0>;
}; };
sdio1_clk: sdio1 { ref_cx40_clk: ref_cx40 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
}; };
sdio2_clk: sdio2 { ref_52m_clk: ref_52m {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
}; };
sdio3_clk: sdio3 { var_52m_clk: var_52m {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
}; };
sdio4_clk: sdio4 { usb_otg_ahb_clk: usb_otg_ahb {
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <48000000>; clock-frequency = <52000000>;
#clock-cells = <0>; #clock-cells = <0>;
}; };
tmon_1m_clk: tmon_1m { ref_96m_clk: ref_96m {
compatible = "fixed-clock";
clock-frequency = <1000000>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
}; };
uartb_clk: uartb { var_96m_clk: var_96m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
}; };
uartb2_clk: uartb2 { ref_104m_clk: ref_104m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <104000000>;
};
var_104m_clk: var_104m {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104000000>;
}; };
uartb3_clk: uartb3 { ref_156m_clk: ref_156m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <156000000>;
};
var_156m_clk: var_156m {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156000000>;
}; };
uartb4_clk: uartb4 { ref_208m_clk: ref_208m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <13000000>; clock-frequency = <208000000>;
};
var_208m_clk: var_208m {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <208000000>;
}; };
usb_otg_ahb_clk: usb_otg_ahb { ref_312m_clk: ref_312m {
#clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <52000000>; clock-frequency = <312000000>;
};
var_312m_clk: var_312m {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <312000000>;
}; };
}; };
......
/* /*
* Copyright (C) 2012 Broadcom Corporation * Copyright (C) 2014 Broadcom Corporation
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
...@@ -13,11 +13,13 @@ ...@@ -13,11 +13,13 @@
/dts-v1/; /dts-v1/;
#include "bcm11351.dtsi" #include <dt-bindings/gpio/gpio.h>
#include "bcm21664.dtsi"
/ { / {
model = "BCM11351 BRT board"; model = "BCM21664 Garnet board";
compatible = "brcm,bcm11351-brt", "brcm,bcm11351"; compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
memory { memory {
reg = <0x80000000 0x40000000>; /* 1 GB */ reg = <0x80000000 0x40000000>; /* 1 GB */
...@@ -40,7 +42,7 @@ sdio2: sdio@3f190000 { ...@@ -40,7 +42,7 @@ sdio2: sdio@3f190000 {
sdio4: sdio@3f1b0000 { sdio4: sdio@3f1b0000 {
max-frequency = <48000000>; max-frequency = <48000000>;
cd-gpios = <&gpio 14 0>; cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
/ {
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
interrupt-parent = <&gic>;
chosen {
bootargs = "console=ttyS0,115200n8";
};
gic: interrupt-controller@3ff00100 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x3ff01000 0x1000>,
<0x3ff00100 0x100>;
};
smc@0x3404e000 {
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
};
uart@3e000000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e000000 0x118>;
clocks = <&uartb_clk>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@3e001000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x118>;
clocks = <&uartb2_clk>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@3e002000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x118>;
clocks = <&uartb3_clk>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x3ff20000 0x1000>;
cache-unified;
cache-level = <2>;
};
brcm,resetmgr@35001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x35001f00 0x24>;
};
timer@35006000 {
compatible = "brcm,kona-timer";
reg = <0x35006000 0x1c>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hub_timer_clk>;
};
gpio: gpio@35003000 {
compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x524>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};
sdio1: sdio@3f180000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f180000 0x801c>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio1_clk>;
status = "disabled";
};
sdio2: sdio@3f190000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f190000 0x801c>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio2_clk>;
status = "disabled";
};
sdio3: sdio@3f1a0000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f1a0000 0x801c>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio3_clk>;
status = "disabled";
};
sdio4: sdio@3f1b0000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f1b0000 0x801c>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdio4_clk>;
status = "disabled";
};
i2c@3e016000 {
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
reg = <0x3e016000 0x70>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bsc1_clk>;
status = "disabled";
};
i2c@3e017000 {
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
reg = <0x3e017000 0x70>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bsc2_clk>;
status = "disabled";
};
i2c@3e018000 {
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
reg = <0x3e018000 0x70>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bsc3_clk>;
status = "disabled";
};
i2c@3e01c000 {
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
reg = <0x3e01c000 0x70>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bsc4_clk>;
status = "disabled";
};
clocks {
bsc1_clk: bsc1 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
bsc2_clk: bsc2 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
bsc3_clk: bsc3 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
bsc4_clk: bsc4 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
pmu_bsc_clk: pmu_bsc {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
hub_timer_clk: hub_timer {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
pwm_clk: pwm {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
sdio1_clk: sdio1 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
sdio2_clk: sdio2 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
sdio3_clk: sdio3 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
sdio4_clk: sdio4 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
tmon_1m_clk: tmon_1m {
compatible = "fixed-clock";
clock-frequency = <1000000>;
#clock-cells = <0>;
};
uartb_clk: uartb {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
uartb2_clk: uartb2 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
uartb3_clk: uartb3 {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
usb_otg_ahb_clk: usb_otg_ahb {
compatible = "fixed-clock";
clock-frequency = <52000000>;
#clock-cells = <0>;
};
};
usbotg: usb@3f120000 {
compatible = "snps,dwc2";
reg = <0x3f120000 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_otg_ahb_clk>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
status = "disabled";
};
usbphy: usb-phy@3f130000 {
compatible = "brcm,kona-usb2-phy";
reg = <0x3f130000 0x28>;
#phy-cells = <0>;
status = "disabled";
};
};
...@@ -46,27 +46,32 @@ i2c@3e018000 { ...@@ -46,27 +46,32 @@ i2c@3e018000 {
i2c@3500d000 { i2c@3500d000 {
status="okay"; status="okay";
clock-frequency = <400000>; clock-frequency = <100000>;
};
sdio1: sdio@3f180000 { pmu: pmu@8 {
max-frequency = <48000000>; reg = <0x08>;
status = "okay"; };
}; };
sdio2: sdio@3f190000 { sdio2: sdio@3f190000 {
non-removable; non-removable;
max-frequency = <48000000>; max-frequency = <48000000>;
vmmc-supply = <&camldo1_reg>;
vqmmc-supply = <&iosr1_reg>;
status = "okay"; status = "okay";
}; };
sdio4: sdio@3f1b0000 { sdio4: sdio@3f1b0000 {
max-frequency = <48000000>; max-frequency = <48000000>;
cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
vmmc-supply = <&sdldo_reg>;
vqmmc-supply = <&sdxldo_reg>;
status = "okay"; status = "okay";
}; };
usbotg: usb@3f120000 { usbotg: usb@3f120000 {
vusb_d-supply = <&usbldo_reg>;
vusb_a-supply = <&iosr1_reg>;
status = "okay"; status = "okay";
}; };
...@@ -74,3 +79,39 @@ usbphy: usb-phy@3f130000 { ...@@ -74,3 +79,39 @@ usbphy: usb-phy@3f130000 {
status = "okay"; status = "okay";
}; };
}; };
#include "bcm59056.dtsi"
&pmu {
compatible = "brcm,bcm59056";
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
regulators {
camldo1_reg: camldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sdldo_reg: sdldo {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
sdxldo_reg: sdxldo {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
};
usbldo_reg: usbldo {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
iosr1_reg: iosr1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
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/*
* Broadcom BCM470X / BCM5301X arm platform code.
* DTS for Netgear R6250 V1
*
* Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
/dts-v1/;
#include "bcm4708.dtsi"
/ {
compatible = "netgear,r6250v1", "brcm,bcm4708";
model = "Netgear R6250 V1 (BCM4708)";
chosen {
bootargs = "console=ttyS0,115200";
};
memory {
reg = <0x00000000 0x08000000>;
};
chipcommonA {
uart0: serial@0300 {
status = "okay";
};
uart1: serial@0400 {
status = "okay";
};
};
};
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...@@ -26,7 +26,7 @@ adc@40002000 { ...@@ -26,7 +26,7 @@ adc@40002000 {
}; };
i2c@4000a000 { i2c@4000a000 {
location = <3>; efm32,location = <3>;
status = "ok"; status = "ok";
temp@48 { temp@48 {
......
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