- 26 Jul, 2020 3 commits
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Randy Dunlap authored
Delete the repeated word "the". Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@vger.kernel.org Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Randy Dunlap authored
Delete the repeated word "Returns". Signed-off-by:
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Randy Dunlap authored
Delete the repeated word "on". Signed-off-by:
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- 24 Jul, 2020 5 commits
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Jiri Slaby authored
It references __initdata and is called only from an __init function: trap_init. This avoids section mismatches (which I am seeing with gcc 10). Signed-off-by:
Jiri Slaby <jslaby@suse.cz> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@vger.kernel.org Signed-off-by:
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Álvaro Fernández Rojas authored
There are some CFE variants that start with 'cfe-vd' instead of 'cfe-v', such as the one used in the Huawei HG556a: "cfe-vd081.5003". In this case, the CFE version is stored as is (string vs number bytes). Some newer devices have an additional version number, such as the Comtrend VR-3032u: "1.0.38-112.118-11". Finally, print the string as is if the version doesn't start with "cfe-v" or "cfe-vd", but starts with "cfe-". Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Add "PRID_COMP_INGENIC_13" and "PRID_IMP_XBURST2" for X2000. 2.Add X2000 system type for cat /proc/cpuinfo to give out X2000. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by:
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Yu Kuai authored
if of_find_device_by_node() succeed, dwc3_octeon_device_init() doesn't have a corresponding put_device(). Thus add put_device() to fix the exception handling for this function implementation. Fixes: 93e502b3 ("MIPS: OCTEON: Platform support for OCTEON III USB controller") Signed-off-by:
Yu Kuai <yukuai3@huawei.com> Signed-off-by:
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Jiaxun Yang authored
paravirt machine was introduced for Cavium's partial virtualization technology, however, it's host side support and QEMU support never landed in upstream. As Cavium was acquired by Marvel and they have no intention to maintain their MIPS product line, also paravirt is unlikely to be utilized by community users, it's time to retire it if nobody steps in to maintain it. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
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- 21 Jul, 2020 6 commits
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Serge Semin authored
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS GIC timer and MIPS CPS CPUidle drivers. Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by:
Marc Zyngier <maz@kernel.org> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
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Serge Semin authored
CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being supported for that MIPS arch too. Signed-off-by:
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Serge Semin authored
Since having and mapping the CDMM block is platform specific, then instead of just returning a zero-address, lets make the default CDMM base address search method (mips_cdmm_phys_base()) to do something useful. For instance to find the address in a dedicated dtb-node in order to support of-based platforms by default. Signed-off-by:
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Serge Semin authored
It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Serge Semin authored
Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by:
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Serge Semin authored
It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by:
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- 16 Jul, 2020 22 commits
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Tiezhu Yang authored
In the MIPS architecture, we should clear the security-relevant flag READ_IMPLIES_EXEC in the function SET_PERSONALITY2() of the file arch/mips/include/asm/elf.h. Otherwise, with this flag set, PROT_READ implies PROT_EXEC for mmap to make memory executable that is not safe, because this condition allows an attacker to simply jump to and execute bytes that are considered to be just data [1]. In mm/mmap.c: unsigned long do_mmap(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, vm_flags_t vm_flags, unsigned long pgoff, unsigned long *populate, struct list_head *uf) { [...] if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC)) if (!(file && path_noexec(&file->f_path))) prot |= PROT_EXEC; [...] } By the way, x86 and ARM64 have done the similar thing. After commit 250c2277 ("x86_64: move kernel"), in the file arch/x86/kernel/process_64.c: void set_personality_64bit(void) { [...] current->personality &= ~READ_IMPLIES_EXEC; } After commit 48f99c8e ("arm64: Preventing READ_IMPLIES_EXEC propagation"), in the file arch/arm64/include/asm/elf.h: #define SET_PERSONALITY(ex) \ ({ \ clear_thread_flag(TIF_32BIT); \ current->personality &= ~READ_IMPLIES_EXEC; \ }) [1] https://insights.sei.cmu.edu/cert/2014/02/feeling-insecure-blame-your-parent.htmlReported-by:Juxin Gao <gaojuxin@loongson.cn> Co-developed-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Peng Fan authored
Close "fd" before the return of map_vdso() and close "out_file" in main(). Signed-off-by:
Peng Fan <fanpeng@loongson.cn> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Refresh CU1000-Neo's defconfig to support LED. Tested-by:
周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in compatible should be changed to "ingenic,x1000e". 2.Adjust the order of nodes according to the corresponding address value. 3.Drop unnecessary node in "wlan_pwrseq". 4.Add the leds node to "cu1000-neo.dts". Tested-by:
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周琰杰 (Zhou Yanjie) authored
Add a device tree and a defconfig for the Ingenic X1830 based YSH & ATIL CU Neo board. Tested-by:
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周琰杰 (Zhou Yanjie) authored
1.Add bindings for Ingenic X1830 based board, prepare for later dts. 2.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in bindings should be changed to "ingenic,x1000e", the corresponding dts file modification will be made in a patch later in this series. Tested-by:
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周琰杰 (Zhou Yanjie) authored
Support the Ingenic X1830 SoC using the code under arch/mips/jz4740. This is left unselectable in Kconfig until a X1830 based board is added in a later commit. Tested-by:
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Sunguoyun authored
sparse report build warning as follows: arch/mips/vdso/vdso-n32-image.c:13:35: incorrect type in assignment (different address spaces) @@ expected void *[usertype] vdso @@ got void [noderef] <asn:1> * @@ Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Sunguoyun <sunguoyun@loongson.cn> Signed-off-by:
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by:Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by:
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Jiaxun Yang authored
Load correct devicetree according to PRID and PCH type. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
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Jiaxun Yang authored
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and Generic Loongson64 Quad Core + LS7A boards. Signed-off-by:
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Huacai Chen authored
From previous commits, the machine names with "loongson3-" prefix have renamed to "loongson64c-" prefix in documents, but the .dts files have not been updated as well. So fix it. Signed-off-by:
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Zhi Li authored
Replace hwmon_device_register() with hwmon_device_register_with_info() to fix the following boot warning : [ 9.029924] Loongson Hwmon Enter... [ 9.106850] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). Signed-off-by:
Zhi Li <lizhi01@loongson.cn> Signed-off-by:
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Tiezhu Yang authored
Once the temperature of any CPUs is too high, it can power off immediately, no need to check the rest of CPUs, and it is better to print a log before power off, this is useful when analysis the abnormal issues. Signed-off-by:
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Tiezhu Yang authored
Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: -
Paul Cercueil authored
Add a basic default config for the RS-90 RetroMini board. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Paul Cercueil authored
The RS-90, better known as RetroMini, is a small and pocketable handheld gaming console from YLMChina. It has little more than a JZ4725B SoC, a NAND, a screen, some buttons and a speaker. Signed-off-by:
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Paul Cercueil authored
Add preliminary support for boards based on the JZ4725B SoC from Ingenic. The JZ4725B SoC is supposed to be older than the JZ4740 SoC, but its internals are much closer to what can be found on the JZ4750 and newer SoCs. It is low-power SoC with a MIPS32r1 SoC running at ~360 MHz, and no FPU. Signed-off-by:
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Paul Cercueil authored
Use an enum instead of macros to represent the various versions of the Ingenic SoCs, and add some of the SoC versions that were previously missing. Signed-off-by:
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Paul Cercueil authored
Add compatible strings for the PWM and watchdog IPs on the Ingenic JZ4725B SoC. Signed-off-by:
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Paul Cercueil authored
Add an entry to ingenic/devices.yaml for the JZ4725B-based YLM "RetroMini" RS-90. Signed-off-by:
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Paul Cercueil authored
Shenzhen Yangliming Electronic Technology Co., Ltd., abbreviated YLM or YLMChina, and known as Anbernic in the rest of the world, is a Chinese manufacturer of handheld game consoles, some of which are known to be running Linux. Signed-off-by:
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- 08 Jul, 2020 4 commits
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Wei Yongjun authored
sparse report build warning as follows: drivers/platform/mips/rs780e-acpi.c:72:6: warning: symbol 'acpi_registers_setup' was not declared. Should it be static? And function acpi_registers_setup() is not used outside of this file, so marks it static. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Huacai Chen authored
The size of ioports in the current RS780E dts file is not enough, which sometimes causes device initialize fail. So we increase the size of ISA/ LPC ioports to 0x4000, and increase the size of PCI ioports to 0x8000. Signed-off-by:
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Huacai Chen authored
Document loongson64c-4core-ls7a and loongson64g-4core-ls7a, two boards with LS7A PCH. Signed-off-by:
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Huacai Chen authored
Loongson-3A R1/R2/R3 and Loongson-3B R1/R2 use the same package naming in dts, and Loongson-3A R4 will be different. In cpu.h the classic 64bit Loongson processors are called Loongson64C (C for classic, pre Loongson- 3A R4), and the new 64bit Loongson processors are called Loongson64G (G for generic, Loongson-3A R4+). To keep consistency and make extensible, we rename the classic "loongson3" prefix to "loongson64c", and the new prefix for Loongson-3A R4+ will be "loongson64g". Signed-off-by:
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